update TDC design, add SPI

diff --git a/template/config.vhd b/template/config.vhd
index db13f2fedcdbeb755602175a2fd1cdb544a96df7..9d4a422fe9e97e5e586465691f5e2ccfc0945f59 100644 (file)
--- a/template/config.vhd
+++ b/template/config.vhd
@@ -17,7 +17,7 @@ package config is
 --TDC settings
   constant FPGA_TYPE               : integer  := 5;  --3: ECP3, 5: ECP5
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
-  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 9;  -- number of tdc channels per module
+  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 33;  -- number of tdc channels per module
   constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 5;  --the nearest power of two, for convenience reasons 
   constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 3;  --double edge type:  0, 1, 2,  3
   -- 0: single edge only,
@@ -44,8 +44,8 @@ package config is
     constant USE_RXCLOCK            : integer := c_NO;
    
 --Address settings   
-    constant INIT_ADDRESS           : std_logic_vector := x"F350";
-    constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"80";
+    constant INIT_ADDRESS           : std_logic_vector := x"F570";
+    constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"81";
    
     constant INCLUDE_UART           : integer  := c_YES;  --300 slices
     constant INCLUDE_SPI            : integer  := c_YES; --300 slices

diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl
index a681cf6611387148832507e40831f68ac55574f4..d2e0437d7d2045a69d13c73e5c4a9cf98519bae3 100644 (file)
--- a/template/config_compile_frankfurt.pl
+++ b/template/config_compile_frankfurt.pl
@@ -11,7 +11,7 @@ lattice_path                 => '/d/jspc29/lattice/diamond/3.10_x64',
 synplify_path                => '/d/jspc29/lattice/synplify/O-2018.09-SP1/',
 
 nodelist_file                => '../nodelist_frankfurt.txt',
-pinout_file                  => 'trb5sc_tdc',
+pinout_file                  => 'trb5sc_pqdc',
 par_options                  => '../par.p2t',
 
 

diff --git a/template/nodelist_frankfurt.txt b/template/nodelist_frankfurt.txt
new file mode 100644 (file)
index 0000000..2e858da
--- /dev/null
+++ b/template/nodelist_frankfurt.txt
@@ -0,0 +1,13 @@
+// nodes file for parallel place&route
+
+[jspc37]
+SYSTEM = linux
+CORENUM = 7
+ENV = /d/jspc29/lattice/310_settings.sh
+WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir
+
+[jspc57]
+SYSTEM = linux
+CORENUM = 3
+ENV = /d/jspc29/lattice/310_settings.sh
+WORKDIR = /d/jspc22/trb/git/trb5sc/template/workdir

diff --git a/template/trb5sc_template.prj b/template/trb5sc_template.prj
index 8330e8047bdff97fab92b5549dffa78d5bf95496..ffa8d9a33c77c6c1ba6eeccbe9598a459362eb21 100644 (file)
--- a/template/trb5sc_template.prj
+++ b/template/trb5sc_template.prj
@@ -221,7 +221,7 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FI
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd"
-add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd"
 #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
 
 

diff --git a/template/trb5sc_template.vhd b/template/trb5sc_template.vhd
index 6769d5ebca49fe102078c7b6b5f83f13522cbcbd..36132553a8e029eb8ac0eb9ed1ad18de325b28fc 100644 (file)
--- a/template/trb5sc_template.vhd
+++ b/template/trb5sc_template.vhd
@@ -27,11 +27,17 @@ entity trb5sc_template is
     SFP_LOS    : in  std_logic;
     SFP_MOD_0  : in  std_logic;
     
-    FE_GPIO    : inout std_logic_vector(11 downto 0);
-    FE_CLK     : out   std_logic_vector( 2 downto 1);
-    FE_DIFF    : inout std_logic_vector(63 downto 0);
+    --AddOn
+--     FE_GPIO    : inout std_logic_vector(11 downto 0);
+--     FE_CLK     : out   std_logic_vector( 2 downto 1);
+--     FE_DIFF    : inout std_logic_vector(63 downto 0);
+    INP : in std_logic_vector(63 downto 0);
+
+    CS    : out std_logic_vector(4 downto 1);
+    MISO  : in  std_logic_vector(4 downto 1);
+    MOSI  : out std_logic;
+    SCK   : out std_logic;
     
-
     --ADC
     ADC_SCLK     : out   std_logic;
     ADC_NCS      : out   std_logic;
@@ -106,7 +112,7 @@ architecture arch of trb5sc_template is
   signal sed_error_i       : std_logic;
   signal clock_select      : std_logic;
   signal bus_master_active : std_logic;
-  signal flash_clk_i       : std_logic;
+  signal flash_ncs_i       : std_logic;
 
   signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);
   signal header_io_i      : std_logic_vector(10 downto 1);
@@ -155,7 +161,7 @@ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and no
 
 
 
-THE_CAL_PLL : entity work.pll_in125_out33
+THE_CAL_PLL : entity work.pll_in125_out50
   port map(
     CLKI  => CLK_125,
     CLKOP => clk_cal
@@ -302,7 +308,7 @@ THE_CAL_PLL : entity work.pll_in125_out33
       RESET => reset_i,
 
       --Flash & Reload
-      FLASH_CS          => FLASH_NCS,
+      FLASH_CS          => flash_ncs_i,
       FLASH_CLK         => FLASH_SCLK,
       FLASH_IN          => FLASH_MISO,
       FLASH_OUT         => FLASH_MOSI,
@@ -349,15 +355,32 @@ THE_CAL_PLL : entity work.pll_in125_out33
 -- I/O
 ---------------------------------------------------------------------------
 
-  monitor_inputs_i <= FE_DIFF(MONITOR_INPUT_NUM-1 downto 0);
-  trigger_inputs_i <= FE_DIFF(TRIG_GEN_INPUT_NUM-1 downto 0);
-  hit_in_i         <= FE_DIFF(NUM_TDC_CHANNELS-2 downto 0);
+  CS <= spi_cs(3 downto 0);
+  spi_miso(3 downto 0) <= MISO;
+  
+  MOSI <= spi_mosi(0) when spi_cs(0) = '0' 
+     else spi_mosi(1) when spi_cs(1) = '0' 
+     else spi_mosi(2) when spi_cs(2) = '0' 
+     else spi_mosi(3) when spi_cs(3) = '0' 
+     else '0';
+  
+  SCK  <= spi_clk(0) when spi_cs(0) = '0' 
+     else spi_clk(1) when spi_cs(1) = '0' 
+     else spi_clk(2) when spi_cs(2) = '0' 
+     else spi_clk(3) when spi_cs(3) = '0' 
+     else '1';
+
+
+  monitor_inputs_i <= INP(MONITOR_INPUT_NUM-1 downto 0);
+  trigger_inputs_i <= INP(TRIG_GEN_INPUT_NUM-1 downto 0);
+  hit_in_i         <= INP(NUM_TDC_CHANNELS-2 downto 0);
 
   assert     DOUBLE_EDGE_TYPE /= 2 report "double edge in separate channels: connections missing" severity error;
 
   HDR_IO(15 downto 10) <= (others => '0');
   TEST(13 downto 1)    <= (others => '0');
-  TEST(14) <= FLASH_NCS;
+  TEST(14) <= flash_ncs_i;
+  FLASH_NCS <= flash_ncs_i;
   
 ---------------------------------------------------------------------------
 -- LED
@@ -367,7 +390,7 @@ THE_CAL_PLL : entity work.pll_in125_out33
   LED_SFP_RED    <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11)) or led_off;
   LED_SFP_YELLOW <= not med2int(0).stat_op(8) or led_off;
   LED            <= x"F0";
-  LED_RJ_GREEN   <= FLASH_NCS & FLASH_NCS;
+  LED_RJ_GREEN   <= "00";
   LED_RJ_RED     <= "11";
   LED_EXT_CLOCK  <= IN_SELECT_EXT_CLOCK or led_off;