use Term::ANSIColor qw(:constants);
use Cwd;
+###################################################################################
+#Settings for this project
+my $FAMILYNAME="LatticeECP3";
+my $DEVICENAME="LFE3-150EA";
+my $PACKAGE="FPBGA1156";
+my $SPEEDGRADE="8";
+
+my %config = do "config_compile.pl";
+
+my $TOPNAME = $config{TOPNAME};
+my $lattice_path = $config{lattice_path};
+my $synplify_path = $config{synplify_path};
+my $lm_license_file_for_synplify = $config{lm_license_file_for_synplify};
+my $lm_license_file_for_par = $config{lm_license_file_for_par};
+my $synplify_command = $config{synplify_command};
+
+#my $synplify_locale_workaround = "en_US\@UTF-8";
+my $synplify_locale_workaround = "C";
+my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed
+
+my $include_TDC = $config{include_TDC} || 0;
+my $include_GBE = $config{include_GBE} || 0;
+my $include_CTS = $config{include_CTS} || 0;
+my $include_HUB = $config{include_HUB} || 0;
+my $twr_number_of_errors = $config{twr_number_of_errors} || 10;
+my $pinout_file = $config{pinout_file} || $TOPNAME;
+my $nodelist_file = $config{nodelist_file} || 'nodelist.txt';
+my $par_options = $config{par_options};
+
+$FAMILYNAME = $config{Familyname} if $config{Familyname};
+$DEVICENAME = $config{Devicename} if $config{Devicename};
+$PACKAGE = $config{Package} if $config{Package};
+$SPEEDGRADE = $config{Speedgrade} if $config{Speedgrade};
+###################################################################################
+
###################################################################################
#Options for the script
my $help = "";
my $con = 0;
my $guidefile = 0;
my $compile_all = 0;
-my $design = "";
my $result = GetOptions (
"h|help" => \$help,
"m|mpar=i" => \$nrNodes,
"t|timing" => \$timing,
"b|bitgen" => \$bitgen,
"g|guide" => \$guidefile,
- "d|design=s" => \$design,
);
if ($help) {
print "-m --mpar\tSwitch for multi par. \"-m <number_of_nodes>\" (Default = off).\n";
print "\t\tThe node list file name has to be edited in the script. (Default = nodes_lxhadeb07.txt).\n";
print "-g --guide\tDefine guide file for the guided placement & routing.\n";
- print "-d --design\tSelect the design to compile. Overrides the TOPNAME option in config_compile.pl.\n";
- print "\t\t-d <DESIGN_TOPNAME>\n";
- print "\t\tDESIGN_TOPNAME: 32PinAddOn, ADA_Addon, gpin, wasa, hadesstart, hub, cts, cbmtof\n";
print "\n";
exit;
}
}
###################################################################################
-###################################################################################
-#Settings for this project
-my %config = do "config_compile.pl";
-
-
-my $TOPNAME = $design || $config{TOPNAME};
-my $project_path = $config{project_path};
-my $lattice_path = $config{lattice_path};
-my $synplify_path = $config{synplify_path};
-my $lm_license_file_for_synplify = $config{lm_license_file_for_synplify};
-my $lm_license_file_for_par = $config{lm_license_file_for_par};
-my $synplify_command = $config{synplify_command};
-
-#my $synplify_locale_workaround = "en_US\@UTF-8";
-my $synplify_locale_workaround = "C";
-my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed
-
-my $include_TDC = $config{include_TDC} || 0;
-my $include_GBE = $config{include_GBE} || 0;
-my $include_CTS = $config{include_CTS} || 0;
-my $include_HUB = $config{include_HUB} || 0;
-my $twr_number_of_errors = $config{twr_number_of_errors} || 10;
-#my $pinout_file = $config{pinout_file} || $TOPNAME;
-my $nodelist_file = $config{nodelist_file};
-my $par_options = $config{par_options};
-###################################################################################
-
-
# source the standard lattice environment
$ENV{bindir}="$lattice_bin_path";
-#open my $SOURCE, "bash -c '. $lattice_bin_path/diamond_env >& /dev/null; env'|" or
-# die "Can't fork: $!";
-#while (<$SOURCE>) {
-# if (/^(.*)=(.*)/) {
-# $ENV{$1} = ${2} ;
-# }
-#}
-#close $SOURCE;
-
-
-my %FPGA=(
- trb3_periph_32PinAddOn =>{family=>"LatticeECP3", device=>"LFE3-150EA", speed=>"8", package=>"FPBGA672", path=>"32PinAddOn"},
- trb3_periph_ADA =>{family=>"LatticeECP3", device=>"LFE3-150EA", speed=>"8", package=>"FPBGA672", path=>"ADA_Addon"},
- trb3_periph_gpin =>{family=>"LatticeECP3", device=>"LFE3-150EA", speed=>"8", package=>"FPBGA672", path=>"gpin"},
- trb3_periph_padiwa =>{family=>"LatticeECP3", device=>"LFE3-150EA", speed=>"8", package=>"FPBGA672", path=>"wasa"},
- trb3_periph_hadesstart =>{family=>"LatticeECP3", device=>"LFE3-150EA", speed=>"8", package=>"FPBGA672", path=>"hadesstart"},
- trb3_periph_hub =>{family=>"LatticeECP3", device=>"LFE3-150EA", speed=>"8", package=>"FPBGA672", path=>"hub"},
- trb3_central_cts =>{family=>"LatticeECP3", device=>"LFE3-150EA", speed=>"8", package=>"FPBGA1156", path=>"cts"},
- cbmtof =>{family=>"LatticeECP3", device=>"LFE3-150EA", speed=>"8", package=>"FPBGA672", path=>"cbmtof"},
-# trb3sc =>{family=>"LatticeECP3", device=>"LFE3-150EA", speed=>"8", package=>"FPBGA1156", path=>"../trb3sc/tdctemplate"},
-# dirich =>{family=>"ECP5UM", device=>"LFE5UM-85F", speed=>"8", package=>"BG381C", path=>"../dirich/dirich"},
- );
compile();
sub compile {
- unless (defined $FPGA{$TOPNAME}) {
- print RED, "Project $TOPNAME is not defined. Please edit the FPGA details in the compile script.\n", RESET;
- exit 129;
- }
- if ($design) {
- $project_path = $FPGA{$TOPNAME}{path};
- }
$ENV{'PAR_DESIGN_NAME'}=$TOPNAME;
$ENV{'SYNPLIFY'}=$synplify_path;
$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
$ENV{'SYNPLIFY_BINARY'}=$config{synplify_binary};
- my $FAMILYNAME= $FPGA{$TOPNAME}{family};
- my $DEVICENAME= $FPGA{$TOPNAME}{device};
- my $SPEEDGRADE= $FPGA{$TOPNAME}{speed};
- my $PACKAGE= $FPGA{$TOPNAME}{package};
-
- unless(-d "../$project_path") {
- print "Project path does not exit.\n";
- exit 129;
- }
- chdir "../$project_path";
my $cwd = getcwd();
my $WORKDIR = "workdir";
unless(-d $WORKDIR) {
mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!";
- system("cd $WORKDIR; ../../base/linkdesignfiles.sh; cd ..");
+ system("cd $WORKDIR; ../../../trb3/base/linkdesignfiles.sh; cd ..");
}
system("ln -sfT $lattice_path $WORKDIR/lattice-diamond");
#create full lpf file
my $pinout_file = $config{pinout_file} || $TOPNAME;
print GREEN, "Generating constraints file...\n\n", RESET;
- system("cp ../base/$pinout_file.lpf $WORKDIR/$TOPNAME.lpf");
+ if ($TOPNAME =~ /trb3/) {
+ system("cp ../base/$pinout_file.lpf $WORKDIR/$TOPNAME.lpf");
+ }
+ else {
+ system("cp ../pinout/$pinout_file.lpf $WORKDIR/$TOPNAME.lpf");
+ }
if ($include_TDC && $include_CTS==0) {
system("cat tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
system("cat tdc_release/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
system("cat unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf");
+ #copy delay line to project folder
+ system("rm $WORKDIR/Adder_304.ngo");
+ system("ln -s ../../../tdc/base/cores/ecp3/TDC/Adder_304.ngo $WORKDIR/Adder_304.ngo");
+
#change the Ring buffer name in the constraints file according to the config.vhd
my $fh = new FileHandle("<config.vhd");
my @a = <$fh>;
my $config_vhd = 'config_mainz_a2.vhd';
system("ln -f -s $config_vhd config.vhd") unless (-e "config.vhd");
system("./compile_constraints.pl");
- system("cp ../base/mulipar_nodelist_example.txt $WORKDIR/nodelist.txt") unless (-e "$WORKDIR/nodelist.txt");
+ system("cp ../../trb3/base/mulipar_nodelist_example.txt $WORKDIR/nodelist.txt") unless (-e "$WORKDIR/nodelist.txt");
symlink($CbmNetPath, '../cbmnet/cbmnet') unless (-e '../cbmnet/cbmnet');
}
- if ($include_TDC) {
- #copy delay line to project folder
- system("rm $WORKDIR/Adder_304.ngo");
- system("ln -s ../../../tdc/base/cores/ecp3/TDC/Adder_304.ngo $WORKDIR/Adder_304.ngo");
- }
-
if ($guidefile && -f "$TOPNAME.ncd") {
system("cp $TOPNAME.ncd guidefile.ncd");
$guidefile = " -g guidefile.ncd "
chdir $WORKDIR;
if ($syn==1 || $all==1) {
+ if ($include_TDC) { ## edit prj file for different designs
+ my %configSettings = ();
+ open(CONFIG, '../config.vhd');
+ my $config = "#!!! This file was compiled using compile_contraints.pl.\n#!!! DO NOT EDIT AS ALL CHANGES WILL BE OVERRIDEN\n\n";
+ print "The following module configuration was derived from config.vhd:\n";
+
+ while(my $line = <CONFIG>) {
+ if ($line =~ /(TDC_DATA_FORMAT).*:=\s*(\d+).*;/i) {
+ my $mod = uc $1;
+ my $type = $2;
+ $configSettings{$mod} = $type;
+ my $conf = "set $mod $type\n";
+ print ' ' . $conf;
+ $config .= $conf;
+ }
+ }
+ close(CONFIG);
+ open TCLCONF, '>', $TOPNAME . '_prjconfig.tcl';
+ print TCLCONF $config;
+ close TCLCONF;
+ }
+
print GREEN, "Starting synthesis process...\n\n", RESET;
$c="$synplify_path/bin/synplify_premier_dp -batch ../$TOPNAME.prj";
$r=execute($c, "do_not_exit" );
jspc29 / trb3.git / commitdiff