add simple (stretchable) multiplicity trigger for input channels for DiRICH

diff --git a/dirich/code/stretched_OR_trigger_multi.vhd b/dirich/code/input_multiplicity_trigger.vhd
similarity index 94%
rename from dirich/code/stretched_OR_trigger_multi.vhd
rename to dirich/code/input_multiplicity_trigger.vhd
index 63a52a3e8e1de4663805e069bf33763d4536d077..6577f1f1e0e441a4bbaf4448675a7f60014e75d6 100644 (file)
--- a/dirich/code/stretched_OR_trigger_multi.vhd
+++ b/dirich/code/input_multiplicity_trigger.vhd
@@ -5,7 +5,7 @@ library ieee;
 library work;
   use work.trb_net_std.all;
   
-entity stretched_OR_trigger_multi is
+entity input_multiplicity_trigger is
 port(
   CLK             : in  std_logic;
   RESET           : in  std_logic;
@@ -19,7 +19,7 @@ port(
 );
 end entity;
 
-architecture behaviour of stretched_OR_trigger_multi is
+architecture behaviour of input_multiplicity_trigger is
 
   signal stretched_input     : std_logic_vector (31 downto 0) := x"00000000";
   signal multiplicity        : std_logic_vector ( 4 downto 0) := "00000";
@@ -33,7 +33,7 @@ begin
 
 
   GEN_STRETCH : for i in 0 to 31 generate
-      THE_TRIGGER_Stretch : entity work.stretched_OR_trigger 
+      THE_TRIGGER_Stretch : entity work.input_signal_stretcher 
         port map (
           CLK     => CLK,
           RESET   => RESET,
@@ -66,7 +66,7 @@ begin
                     '0';
             
 
-  THE_TRIGGER_SIGNAL_Stretch : entity work.stretched_OR_trigger 
+  THE_TRIGGER_SIGNAL_Stretch : entity work.input_signal_stretcher 
   port map (
     CLK     => CLK,
     RESET   => RESET,

diff --git a/dirich/code/stretched_OR_trigger.vhd b/dirich/code/input_signal_stretcher.vhd
similarity index 93%
rename from dirich/code/stretched_OR_trigger.vhd
rename to dirich/code/input_signal_stretcher.vhd
index 897ff4600e12635c080910055367cdcba8a3a058..f5f0c27d923f2ce05b598ebf75bf3e3db3331870 100644 (file)
--- a/dirich/code/stretched_OR_trigger.vhd
+++ b/dirich/code/input_signal_stretcher.vhd
@@ -4,7 +4,7 @@ library ieee;
 library work;
   use work.trb_net_std.all;
   
-entity stretched_OR_trigger is
+entity input_signal_stretcher is
 port(
   CLK     : in  std_logic;
   RESET   : in  std_logic;
@@ -16,7 +16,7 @@ port(
 );
 end entity;
 
-architecture behaviour of stretched_OR_trigger is
+architecture behaviour of input_signal_stretcher is
   signal or_long  : std_logic := '0';
   signal active   : std_logic := '1';
   signal cnt      : unsigned (3 downto 0) := x"0";

diff --git a/dirich/config.vhd b/dirich/config.vhd
index 37e188721ead5eaaf88960ab7d0310860cf3b048..65d65875d516b3076627fdf624531a020c43427e 100644 (file)
--- a/dirich/config.vhd
+++ b/dirich/config.vhd
@@ -51,11 +51,12 @@ package config is
     constant INCLUDE_DEBUG_INTERFACE: integer  := c_NO; --300 slices
 
 --input monitor and trigger generation logic
-    constant INCLUDE_TRIGGER_LOGIC  : integer  := c_NO; --400 slices @32->2
-    constant INCLUDE_STATISTICS     : integer  := c_NO; --1300 slices, 1 RAM @32
-    constant TRIG_GEN_INPUT_NUM     : integer  := 1;
-    constant TRIG_GEN_OUTPUT_NUM    : integer  := 1;
-    constant MONITOR_INPUT_NUM      : integer  := 32;
+    constant INCLUDE_TRIGGER_LOGIC    : integer  := c_NO; --400 slices @32->2
+    constant INCLUDE_STATISTICS       : integer  := c_NO; --1300 slices, 1 RAM @32
+    constant USE_MULTIPLICITY_TRIGGER : integer := c_YES;
+    constant TRIG_GEN_INPUT_NUM       : integer  := 1;
+    constant TRIG_GEN_OUTPUT_NUM      : integer  := 1;
+    constant MONITOR_INPUT_NUM        : integer  := 32;
   
 --Retransmission
     constant USE_RETRANSMISSION     : integer  := c_NO;--c_YES;

diff --git a/dirich/dirich.prj b/dirich/dirich.prj
index b1a2af7791b5d541e75804987090efdcb625dcc9..aadc8ee7f0e4913816a573a68ea123136601ca73 100644 (file)
--- a/dirich/dirich.prj
+++ b/dirich/dirich.prj
@@ -216,9 +216,9 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_
 #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd"
 
-## trigger Input signal_sync
-add_file -vhdl -lib work "./code/stretched_OR_trigger.vhd"
-add_file -vhdl -lib work "./code/stretched_OR_trigger_multi.vhd"
+## multiplicity trigger Input signal
+add_file -vhdl -lib work "./code/input_signal_stretcher.vhd"
+add_file -vhdl -lib work "./code/input_multiplicity_trigger.vhd"
 
 add_file -vhdl -lib work "./dirich.vhd"
 #add_file -fpga_constraint "./synplify.fdc"

diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd
index 2f67518d65b1502ba03530eaa4d1a9572c5bb8f5..7ee72213f6c4e86655cb57da6f0f48c45b596937 100644 (file)
--- a/dirich/dirich.vhd
+++ b/dirich/dirich.vhd
@@ -374,17 +374,28 @@ end generate;
 ---------------------------------------------------------------------------
 -- Trigger
 ---------------------------------------------------------------------------
-THE_INPUT_TRIGGER : entity work.stretched_OR_trigger_multi
-port map (
-  CLK             => clk_sys,
-  RESET           => reset_i,
-  INPUT           => INPUT(32 downto 1),
-  OUTPUT          => signal_trigger_out,
-  OUTPUT_UNSTRCHD => signal_trigger_unstretched,
+gen_MULT_TRIG : if USE_MULTIPLICITY_TRIGGER = c_YES generate
+  THE_MULT_TRIG : entity work.input_multiplicity_trigger
+  port map (
+    CLK             => clk_sys,
+    RESET           => reset_i,
+    INPUT           => INPUT(32 downto 1),
+    OUTPUT          => signal_trigger_out,
+    OUTPUT_UNSTRCHD => signal_trigger_unstretched,
   
-  BUS_RX          => bus_sigTrigger_rx,
-  BUS_TX          => bus_sigTrigger_tx
-);
+    BUS_RX          => bus_sigTrigger_rx,
+    BUS_TX          => bus_sigTrigger_tx
+  );
+end generate;
+
+gen_MULT_TRIG : if USE_MULTIPLICITY_TRIGGER = c_NO generate
+  signal_trigger_out <= '0';
+  signal_trigger_unstretched <= '0';
+
+  bus_sigTrigger_tx.ack     <= '0';
+  bus_sigTrigger_tx.nack    <= '0';
+  bus_sigTrigger_tx.unknown <= '1';
+end generate;
 
 SIG(3) <= signal_trigger_out;
 SIG(4) <= signal_trigger_unstretched;

diff --git a/dirich/nodelist_giessen.txt b/dirich/nodelist_giessen.txt
index 371f726cb5a6d40bf4bfc8cf11c0ebe20a494981..d0b2e027329e45613efae61dadec960efcc35562 100644 (file)
--- a/dirich/nodelist_giessen.txt
+++ b/dirich/nodelist_giessen.txt
@@ -4,4 +4,4 @@
 [fb07pc-u102325]
 SYSTEM = linux
 CORENUM = 12
-WORKDIR = /home/adrian/trbvhdl/dirich/dirich_trigger/workdir
+WORKDIR = /home/adrian/trbvhdl/dirich/dirich/workdir

diff --git a/dirich/par.p2t b/dirich/par.p2t
index 424d026a544131206c3fc633855bbfc0c7eb56a2..8116754f9e9e6764042ff445b0bb20fcfbbe0dfe 100644 (file)
--- a/dirich/par.p2t
+++ b/dirich/par.p2t
@@ -4,7 +4,7 @@
 #-m nodelist.txt       # Controlled by the compile.pl script.
 #-n 2                          # Controlled by the compile.pl script.
 -s 10
--t 1  #12  #36
+-t 48  #12  #36
 #-t 85
 -c 2
 -e 2