testbench for coincidence scalers

diff --git a/code/tb/tb_scalers_xy.vhd b/code/tb/tb_scalers_xy.vhd
new file mode 100644 (file)
index 0000000..5e0c9a0
--- /dev/null
+++ b/code/tb/tb_scalers_xy.vhd
@@ -0,0 +1,68 @@
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.trb_net_std.all;
+
+entity tb is
+end entity;
+
+
+
+
+architecture arch of tb is
+
+signal clk_sys : std_logic := '1';
+signal reset_i : std_logic := '1';
+
+signal signals : std_logic_vector(31 downto 0) := (others => '0');
+signal BUS_RX : CTRLBUS_RX;
+
+
+begin
+
+clk_sys  <= not clk_sys after 5 ns;
+reset_i <= '0' after 100 ns;
+
+
+THE_DUT : entity work.scaler_xy
+  port map(
+    CLK   => clk_sys,
+    RESET => reset_i,
+    
+    SIGNAL_IN => signals,
+    
+    BUS_RX    => BUS_RX,
+    BUS_TX    => open
+    );
+
+    
+process begin
+  signals  <= x"0000_0000";
+  wait for 300 ns;
+  signals  <= x"0000_0000";
+  wait for 11 ns;  
+  signals  <= x"0000_0001";
+  wait for 7 ns;  
+  signals  <= x"0100_0001";
+  wait for 11 ns;  
+  signals  <= x"0100_0000";
+  wait for 1 ns;  
+  signals  <= x"0000_0000";
+  wait for 43 ns;
+  wait for 11 ns;  
+  signals  <= x"0000_0001";
+  wait for 7 ns;  
+  signals  <= x"0110_0001";
+  wait for 11 ns;  
+  signals  <= x"0111_0001";
+  wait for 11 ns;  
+  signals  <= x"0001_0000";
+  wait for 5 ns;
+  
+end process;
+
+
+
+
+end architecture;