\subsubsection{Time Measurement}
Time measurement is accomplished by a tapped delay line in the FPGA: The input signal travels along a line of about 300 delay elements realized by routing the signal through basic logic blocks (Look Up Tables - LUT) of the FPGA. If a hit is detected, the delay chain is read out, decoded and the position is stored in an internal buffer for read-out.
-The intrinsic dead-time of each TDC channel is 15~ns. Hence, to be able to measure both edges of the input signals with a width of a few nanoseconds, an internal stretcher in the FPGA is realized. The input signal is sent through in-FPGA routing and delayed by 20 to 30~ns. The original leading edge is then combined with the delayed trailing edge to a single pulse and fed to the TDC. This gives the TDC time to measure, decode and store the leading edge, before the delayed trailing edge arrives and is measured in the same TDC channel as well. The TDC implementation is described in further detail in \cite{tdc}.
+The intrinsic dead-time of each TDC channel is 15~ns. Hence, to be able to measure both edges of the input signals with a width of a few nanoseconds, an internal stretcher in the FPGA is realized. The input signal is sent through in-FPGA routing and delayed by 20 to 30~ns. The original leading edge is then combined with the delayed trailing edge to a single, stretched pulse and fed to the TDC. This gives the TDC time to measure, decode and store the leading edge, before the delayed trailing edge arrives and is measured in the same TDC channel as well. The TDC implementation is described in further detail in \cite{tdc}.
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