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-- SED Detection
---------------------------------------------------------------------------
+gen_sed : if FPGA_TYPE = 3 generate
THE_SED : entity work.sedcheck
port map(
CLK => CLK,
BUS_TX => bussed_tx,
DEBUG => open
);
+else generate
+ bussed_tx.unknown <= bussed_rx.write or bussed_rx.read;
+ bussed_tx.ack <= '0'; bussed_tx.nack <= '0';
+ bussed_tx.data <= (others => '0');
+ SED_ERROR_OUT <= '0';
+end generate;
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