+++ /dev/null
-#!/usr/bin/perl
-use Data::Dumper;
-use warnings;
-use strict;
-
-
-
-
-###################################################################################
-#Settings for this project
-my $TOPNAME = "trb3_periph"; #Name of top-level entity
-my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105';
-my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';
-my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
-my $lm_license_file_for_par = "1702\@hadeb05.gsi.de";
-###################################################################################
-
-
-
-
-
-
-
-
-use FileHandle;
-
-$ENV{'SYNPLIFY'}=$synplify_path;
-$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
-
-
-
-
-my $FAMILYNAME="LatticeECP3";
-my $DEVICENAME="LFE3-150EA";
-my $PACKAGE="FPBGA672";
-my $SPEEDGRADE="8";
-
-
-#create full lpf file
-system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf");
-system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf");
-
-
-#set -e
-#set -o errexit
-
-#generate timestamp
-my $t=time;
-my $fh = new FileHandle(">version.vhd");
-die "could not open file" if (! defined $fh);
-print $fh <<EOF;
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
- constant VERSION_NUMBER_TIME : integer := $t;
-
-end package version;
-EOF
-$fh->close;
-
-system("env| grep LM_");
-my $r = "";
-
-my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
-$r=execute($c, "do_not_exit" );
-
-
-chdir "workdir";
-$fh = new FileHandle("<$TOPNAME".".srr");
-my @a = <$fh>;
-$fh -> close;
-
-
-
-foreach (@a)
-{
- if(/\@E:/)
- {
- print "\n";
- $c="cat $TOPNAME.srr | grep \"\@E\"";
- system($c);
- print "\n\n";
- exit 129;
- }
-}
-
-
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
-
-
-$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
-execute($c);
-
-my $tpmap = $TOPNAME . "_map" ;
-
-$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-execute($c);
-
-system("rm $TOPNAME.ncd");
-
-
-$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
-execute($c);
-
-# IOR IO Timing Report
-# $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-# execute($c);
-
-# TWR Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
-# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-chdir "..";
-
-exit;
-
-sub execute {
- my ($c, $op) = @_;
- #print "option: $op \n";
- $op = "" if(!$op);
- print "\n\ncommand to execute: $c \n";
- $r=system($c);
- if($r) {
- print "$!";
- if($op ne "do_not_exit") {
- exit;
- }
- }
-
- return $r;
-
-}
--- /dev/null
+#!/bin/sh
+
+. /usr/local/opt/lattice_diamond/diamond/new/bin/lin/diamond_env
+
+exec ./compile_munich2.pl
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+entity adc_spi_master is\r
+ generic (\r
+ SPI_SPEED : unsigned(7 downto 0) := x"32"\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ -- SPI connections\r
+ SCLK_OUT : out std_logic;\r
+ SDIO_INOUT : inout std_logic;\r
+ CSB_OUT : out std_logic;\r
+ \r
+ -- Slave bus \r
+ SLV_READ_IN : in std_logic;\r
+ SLV_WRITE_IN : in std_logic;\r
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);\r
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);\r
+ SLV_ACK_OUT : out std_logic;\r
+ SLV_NO_MORE_DATA_OUT : out std_logic;\r
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;\r
+ \r
+ -- Debug Line\r
+ DEBUG_OUT : out std_logic_vector(15 downto 0)\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of adc_spi_master is\r
+\r
+ signal sdio_i : std_logic;\r
+ signal sdio_x : std_logic;\r
+ signal sdio : std_logic;\r
+\r
+ signal sclk_o : std_logic;\r
+\r
+ -- SPI Master\r
+ signal csb_o : std_logic;\r
+ signal spi_start : std_logic;\r
+\r
+ signal spi_busy : std_logic;\r
+ signal takeover_sdio : std_logic;\r
+ signal wait_timer_init : unsigned(7 downto 0);\r
+ signal sendbyte_seq_start : std_logic;\r
+ signal readbyte_seq_start : std_logic;\r
+ signal sendbyte_byte : std_logic_vector(7 downto 0);\r
+ signal read_seq_ctr : std_logic;\r
+ signal reg_data : std_logic_vector(31 downto 0);\r
+\r
+ signal spi_busy_x : std_logic;\r
+ signal wait_timer_init_x : unsigned(7 downto 0);\r
+ signal sendbyte_seq_start_x : std_logic;\r
+ signal sendbyte_byte_x : std_logic_vector(7 downto 0);\r
+ signal readbyte_seq_start_x : std_logic;\r
+ signal read_seq_ctr_x : std_logic;\r
+ signal reg_data_x : std_logic_vector(31 downto 0);\r
+ \r
+ signal sdio_sendbyte : std_logic;\r
+ signal sclk_sendbyte : std_logic;\r
+ signal sendbyte_done : std_logic;\r
+ \r
+ signal sclk_readbyte : std_logic;\r
+ signal readbyte_byte : std_logic_vector(7 downto 0);\r
+ signal readbyte_done : std_logic;\r
+ \r
+ type STATES is (S_RESET,\r
+ S_IDLE,\r
+ S_START,\r
+ S_START_WAIT,\r
+ \r
+ S_SEND_CMD_A,\r
+ S_SEND_CMD_A_WAIT,\r
+ S_SEND_CMD_B,\r
+ S_SEND_CMD_B_WAIT,\r
+\r
+ S_SEND_DATA,\r
+ S_SEND_DATA_WAIT,\r
+ S_GET_DATA,\r
+ S_GET_DATA_WAIT,\r
+\r
+ S_STOP,\r
+ S_STOP_WAIT\r
+ );\r
+ signal STATE, NEXT_STATE : STATES;\r
+ \r
+ -- SPI Timer\r
+ signal wait_timer_done : std_logic;\r
+ \r
+ -- TRBNet Slave Bus \r
+ signal slv_data_out_o : std_logic_vector(31 downto 0);\r
+ signal slv_no_more_data_o : std_logic;\r
+ signal slv_unknown_addr_o : std_logic;\r
+ signal slv_ack_o : std_logic;\r
+ signal spi_chipid : std_logic_vector(6 downto 0);\r
+ signal spi_rw_bit : std_logic;\r
+ signal spi_registerid : std_logic_vector(12 downto 0);\r
+ signal spi_register_data : std_logic_vector(7 downto 0);\r
+ signal spi_register_value_read : std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+ -- Timer\r
+ nx_timer_1: nx_timer\r
+ generic map (\r
+ CTR_WIDTH => 8\r
+ )\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ TIMER_START_IN => wait_timer_init,\r
+ TIMER_DONE_OUT => wait_timer_done\r
+ );\r
+\r
+ adc_spi_sendbyte_1: adc_spi_sendbyte\r
+ generic map (\r
+ SPI_SPEED => SPI_SPEED\r
+ )\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ START_IN => sendbyte_seq_start,\r
+ BYTE_IN => sendbyte_byte,\r
+ SEQUENCE_DONE_OUT => sendbyte_done,\r
+ SDIO_OUT => sdio_sendbyte,\r
+ SCLK_OUT => sclk_sendbyte\r
+ );\r
+\r
+ adc_spi_readbyte_1: adc_spi_readbyte\r
+ generic map (\r
+ SPI_SPEED => SPI_SPEED\r
+ )\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ START_IN => readbyte_seq_start,\r
+ BYTE_OUT => readbyte_byte,\r
+ SEQUENCE_DONE_OUT => readbyte_done,\r
+ SDIO_IN => sdio,\r
+ SCLK_OUT => sclk_readbyte\r
+ );\r
+ \r
+ -- Debug Line\r
+\r
+ DEBUG_OUT(0) <= CLK_IN;\r
+ DEBUG_OUT(1) <= SCLK_OUT;\r
+ DEBUG_OUT(2) <= SDIO_INOUT;\r
+ DEBUG_OUT(3) <= CSB_OUT;\r
+ DEBUG_OUT(4) <= spi_busy;\r
+ DEBUG_OUT(5) <= wait_timer_done;\r
+ DEBUG_OUT(6) <= sendbyte_seq_start;\r
+ DEBUG_OUT(7) <= sendbyte_done;\r
+ DEBUG_OUT(8) <= sclk_sendbyte;\r
+ DEBUG_OUT(9) <= sdio_sendbyte;\r
+ DEBUG_OUT(10) <= sclk_readbyte;\r
+ DEBUG_OUT(11) <= takeover_sdio;\r
+\r
+ -- Sync SPI SDIO Line\r
+ sdio_i <= SDIO_INOUT;\r
+\r
+ PROC_I2C_LINES_SYNC: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ sdio_x <= '1';\r
+ sdio <= '1';\r
+ else\r
+ sdio_x <= sdio_i;\r
+ sdio <= sdio_x;\r
+ end if;\r
+ end if;\r
+ end process PROC_I2C_LINES_SYNC;\r
+\r
+ PROC_I2C_MASTER_TRANSFER: process(CLK_IN)\r
+ begin \r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ spi_busy <= '1';\r
+ sendbyte_seq_start <= '0';\r
+ readbyte_seq_start <= '0';\r
+ sendbyte_byte <= (others => '0');\r
+ wait_timer_init <= (others => '0');\r
+ reg_data <= (others => '0');\r
+ read_seq_ctr <= '0';\r
+ STATE <= S_RESET;\r
+ else\r
+ spi_busy <= spi_busy_x;\r
+ sendbyte_seq_start <= sendbyte_seq_start_x;\r
+ readbyte_seq_start <= readbyte_seq_start_x;\r
+ sendbyte_byte <= sendbyte_byte_x;\r
+ wait_timer_init <= wait_timer_init_x;\r
+ reg_data <= reg_data_x;\r
+ read_seq_ctr <= read_seq_ctr_x;\r
+ STATE <= NEXT_STATE;\r
+ end if;\r
+ end if;\r
+ end process PROC_I2C_MASTER_TRANSFER;\r
+ \r
+ \r
+ PROC_I2C_MASTER: process(STATE)\r
+\r
+ begin\r
+ -- Defaults\r
+ takeover_sdio <= '0';\r
+ sclk_o <= '0';\r
+ csb_o <= '0';\r
+ spi_busy_x <= '1';\r
+ sendbyte_seq_start_x <= '0';\r
+ sendbyte_byte_x <= (others => '0');\r
+ readbyte_seq_start_x <= '0';\r
+ wait_timer_init_x <= (others => '0');\r
+ reg_data_x <= reg_data;\r
+ read_seq_ctr_x <= read_seq_ctr;\r
+ \r
+ case STATE is\r
+\r
+ when S_RESET =>\r
+ reg_data_x <= (others => '0');\r
+ NEXT_STATE <= S_IDLE;\r
+ \r
+ when S_IDLE =>\r
+ csb_o <= '1';\r
+ if (spi_start = '1') then\r
+ reg_data_x <= x"8000_0000"; -- Set Running , clear all other bits \r
+ NEXT_STATE <= S_START;\r
+ else\r
+ spi_busy_x <= '0';\r
+ reg_data_x <= reg_data and x"7fff_ffff"; -- clear running bit;\r
+ read_seq_ctr_x <= '0';\r
+ NEXT_STATE <= S_IDLE;\r
+ end if;\r
+ \r
+ -- SPI START Sequence \r
+ when S_START =>\r
+ wait_timer_init_x <= SPI_SPEED srl 2;\r
+ NEXT_STATE <= S_START_WAIT;\r
+ \r
+ when S_START_WAIT =>\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_START_WAIT;\r
+ else\r
+ takeover_sdio <= '1';\r
+ NEXT_STATE <= S_SEND_CMD_A;\r
+ end if;\r
+ \r
+ -- I2C SEND CMD Part1\r
+ when S_SEND_CMD_A =>\r
+ takeover_sdio <= '1';\r
+ sendbyte_byte_x(7) <= spi_rw_bit;\r
+ sendbyte_byte_x(6 downto 5) <= "00";\r
+ sendbyte_byte_x(4 downto 0) <= spi_registerid(12 downto 8);\r
+ sendbyte_seq_start_x <= '1';\r
+ NEXT_STATE <= S_SEND_CMD_A_WAIT;\r
+ \r
+ when S_SEND_CMD_A_WAIT =>\r
+ takeover_sdio <= '1';\r
+ if (sendbyte_done = '0') then\r
+ NEXT_STATE <= S_SEND_CMD_A_WAIT;\r
+ else\r
+ NEXT_STATE <= S_SEND_CMD_B;\r
+ end if;\r
+ \r
+ -- I2C SEND CMD Part1\r
+ when S_SEND_CMD_B =>\r
+ takeover_sdio <= '1';\r
+ sendbyte_byte_x(7 downto 0) <= spi_registerid(7 downto 0);\r
+ sendbyte_seq_start_x <= '1';\r
+ NEXT_STATE <= S_SEND_CMD_B_WAIT;\r
+ \r
+ when S_SEND_CMD_B_WAIT =>\r
+ takeover_sdio <= '1';\r
+ if (sendbyte_done = '0') then\r
+ NEXT_STATE <= S_SEND_CMD_B_WAIT;\r
+ else\r
+ if (spi_rw_bit = '1') then\r
+ NEXT_STATE <= S_GET_DATA;\r
+ else\r
+ NEXT_STATE <= S_SEND_DATA;\r
+ end if;\r
+ end if;\r
+\r
+ -- I2C SEND DataWord\r
+ when S_SEND_DATA =>\r
+ takeover_sdio <= '1';\r
+ sendbyte_byte_x <= spi_register_data;\r
+ sendbyte_seq_start_x <= '1';\r
+ NEXT_STATE <= S_SEND_DATA_WAIT;\r
+ \r
+ when S_SEND_DATA_WAIT =>\r
+ takeover_sdio <= '1';\r
+ if (sendbyte_done = '0') then\r
+ NEXT_STATE <= S_SEND_DATA_WAIT;\r
+ else\r
+ NEXT_STATE <= S_STOP;\r
+ end if;\r
+\r
+ -- I2C GET DataWord\r
+ when S_GET_DATA =>\r
+ readbyte_seq_start_x <= '1';\r
+ NEXT_STATE <= S_GET_DATA_WAIT;\r
+ \r
+ when S_GET_DATA_WAIT =>\r
+ if (readbyte_done = '0') then\r
+ NEXT_STATE <= S_GET_DATA_WAIT;\r
+ else\r
+ reg_data_x(7 downto 0) <= readbyte_byte; \r
+ NEXT_STATE <= S_STOP;\r
+ end if;\r
+ \r
+ -- SPI STOP Sequence \r
+ when S_STOP =>\r
+ wait_timer_init_x <= SPI_SPEED srl 2;\r
+ NEXT_STATE <= S_STOP_WAIT;\r
+ \r
+ when S_STOP_WAIT =>\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_STOP_WAIT;\r
+ else\r
+ reg_data_x <= reg_data or x"4000_0000"; -- Set DONE Bit\r
+ NEXT_STATE <= S_IDLE;\r
+ end if;\r
+ \r
+ end case;\r
+ end process PROC_I2C_MASTER;\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- TRBNet Slave Bus\r
+ -----------------------------------------------------------------------------\r
+ --\r
+ -- Write bit definition\r
+ -- ====================\r
+ -- \r
+ -- D[31] SPI_GO 0 => don't do anything on SPI,\r
+ -- 1 => start SPI access\r
+ -- D[30] SPI_ACTION 0 => write byte, 1 => read byte\r
+ -- D[20:8] SPI_CMD SPI Register Id\r
+ -- D[7:0] SPI_DATA data to be written\r
+ -- \r
+ -- Read bit definition\r
+ -- ===================\r
+ -- \r
+ -- D[31] RUNNING whatever\r
+ -- D[30] SPI_DONE whatever\r
+ -- D[29:21] reserved reserved\r
+ -- D[20:16] debug subject to change, don't use\r
+ -- D[15:8] reserved reserved\r
+ -- D[7:0] SPI_DATA result of SPI read operation\r
+ --\r
+ \r
+ PROC_SLAVE_BUS: process(CLK_IN)\r
+ begin\r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ slv_data_out_o <= (others => '0');\r
+ slv_no_more_data_o <= '0';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_ack_o <= '0';\r
+ spi_start <= '0';\r
+\r
+ spi_chipid <= (others => '0'); \r
+ spi_rw_bit <= '0'; \r
+ spi_registerid <= (others => '0'); \r
+ spi_register_data <= (others => '0'); \r
+ spi_register_value_read <= (others => '0');\r
+ \r
+ else\r
+ slv_ack_o <= '1';\r
+ slv_unknown_addr_o <= '0';\r
+ slv_no_more_data_o <= '0';\r
+ slv_data_out_o <= (others => '0');\r
+ spi_start <= '0';\r
+ \r
+ if (SLV_WRITE_IN = '1') then\r
+ if (spi_busy = '0' and SLV_DATA_IN(31) = '1') then\r
+ spi_rw_bit <= SLV_DATA_IN(30);\r
+ spi_registerid <= SLV_DATA_IN(20 downto 8);\r
+ spi_register_data <= SLV_DATA_IN(7 downto 0); \r
+ spi_start <= '1';\r
+ end if;\r
+\r
+ elsif (SLV_READ_IN = '1') then\r
+ if (spi_busy = '1') then\r
+ slv_data_out_o <= (others => '0');\r
+ slv_no_more_data_o <= '1';\r
+ slv_ack_o <= '0';\r
+ else\r
+ slv_data_out_o <= reg_data;\r
+ end if;\r
+\r
+ else\r
+ slv_ack_o <= '0';\r
+ end if;\r
+ end if;\r
+ end if; \r
+ end process PROC_SLAVE_BUS;\r
+\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- Output Signals\r
+ -----------------------------------------------------------------------------\r
+ \r
+ -- SPI Outputs\r
+ SDIO_INOUT <= sdio_sendbyte when (takeover_sdio = '1')\r
+ else 'Z';\r
+ \r
+ SCLK_OUT <= sclk_o or\r
+ sclk_sendbyte or\r
+ sclk_readbyte;\r
+\r
+ CSB_OUT <= csb_o;\r
+\r
+ -- Slave Bus\r
+ SLV_DATA_OUT <= slv_data_out_o; \r
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; \r
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;\r
+ SLV_ACK_OUT <= slv_ack_o; \r
+\r
+end Behavioral;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+\r
+entity adc_spi_readbyte is\r
+ generic (\r
+ SPI_SPEED : unsigned(7 downto 0) := x"32"\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ START_IN : in std_logic;\r
+ BYTE_OUT : out std_logic_vector(7 downto 0);\r
+ SEQUENCE_DONE_OUT : out std_logic;\r
+\r
+ -- SPI connections\r
+ SDIO_IN : in std_logic;\r
+ SCLK_OUT : out std_logic\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of adc_spi_readbyte is\r
+\r
+ -- Send Byte \r
+ signal sclk_o : std_logic;\r
+ signal spi_start : std_logic;\r
+\r
+ signal sequence_done_o : std_logic;\r
+ signal spi_byte : unsigned(7 downto 0);\r
+ signal bit_ctr : unsigned(3 downto 0);\r
+ signal spi_ack_o : std_logic;\r
+ signal wait_timer_init : unsigned(7 downto 0);\r
+\r
+ signal sequence_done_o_x : std_logic;\r
+ signal spi_byte_x : unsigned(7 downto 0);\r
+ signal bit_ctr_x : unsigned(3 downto 0);\r
+ signal spi_ack_o_x : std_logic;\r
+ signal wait_timer_init_x : unsigned(7 downto 0);\r
+ \r
+ type STATES is (S_IDLE,\r
+ S_UNSET_SCKL,\r
+ S_UNSET_SCKL_HOLD,\r
+ S_GET_BIT,\r
+ S_SET_SCKL,\r
+ S_NEXT_BIT,\r
+ S_DONE\r
+ );\r
+ signal STATE, NEXT_STATE : STATES;\r
+ \r
+ -- Wait Timer\r
+ signal wait_timer_done : std_logic;\r
+\r
+begin\r
+\r
+ -- Timer\r
+ nx_timer_1: nx_timer\r
+ generic map(\r
+ CTR_WIDTH => 8\r
+ )\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ TIMER_START_IN => wait_timer_init,\r
+ TIMER_DONE_OUT => wait_timer_done\r
+ );\r
+\r
+\r
+ PROC_READ_BYTE_TRANSFER: process(CLK_IN)\r
+ begin \r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ sequence_done_o <= '0';\r
+ bit_ctr <= (others => '0');\r
+ spi_ack_o <= '0';\r
+ wait_timer_init <= (others => '0');\r
+ STATE <= S_IDLE;\r
+ else\r
+ sequence_done_o <= sequence_done_o_x;\r
+ spi_byte <= spi_byte_x;\r
+ bit_ctr <= bit_ctr_x;\r
+ spi_ack_o <= spi_ack_o_x;\r
+ wait_timer_init <= wait_timer_init_x;\r
+ STATE <= NEXT_STATE;\r
+ end if;\r
+ end if;\r
+ end process PROC_READ_BYTE_TRANSFER; \r
+ \r
+ PROC_READ_BYTE: process(STATE)\r
+ begin \r
+ sclk_o <= '0';\r
+ sequence_done_o_x <= '0';\r
+ spi_byte_x <= spi_byte;\r
+ bit_ctr_x <= bit_ctr; \r
+ spi_ack_o_x <= spi_ack_o;\r
+ wait_timer_init_x <= (others => '0');\r
+ \r
+ case STATE is\r
+ when S_IDLE =>\r
+ if (START_IN = '1') then\r
+ spi_byte_x <= (others => '0');\r
+ bit_ctr_x <= x"7";\r
+ wait_timer_init_x <= SPI_SPEED srl 1;\r
+ NEXT_STATE <= S_UNSET_SCKL;\r
+ else\r
+ NEXT_STATE <= S_IDLE;\r
+ end if;\r
+\r
+ -- SPI Read byte\r
+ when S_UNSET_SCKL =>\r
+ wait_timer_init_x <= SPI_SPEED srl 1;\r
+ NEXT_STATE <= S_UNSET_SCKL_HOLD;\r
+\r
+ when S_UNSET_SCKL_HOLD =>\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_UNSET_SCKL_HOLD;\r
+ else\r
+ NEXT_STATE <= S_GET_BIT;\r
+ end if;\r
+ \r
+ when S_GET_BIT =>\r
+ spi_byte_x(0) <= SDIO_IN;\r
+ wait_timer_init_x <= SPI_SPEED srl 1;\r
+ NEXT_STATE <= S_SET_SCKL;\r
+\r
+ when S_SET_SCKL =>\r
+ sclk_o <= '1';\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_SET_SCKL;\r
+ else\r
+ wait_timer_init_x <= SPI_SPEED srl 1;\r
+ NEXT_STATE <= S_NEXT_BIT;\r
+ end if;\r
+ \r
+ when S_NEXT_BIT =>\r
+ sclk_o <= '1';\r
+ if (bit_ctr > 0) then\r
+ bit_ctr_x <= bit_ctr - 1;\r
+ spi_byte_x <= spi_byte sll 1;\r
+ wait_timer_init_x <= SPI_SPEED srl 1;\r
+ NEXT_STATE <= S_UNSET_SCKL;\r
+ else\r
+ NEXT_STATE <= S_DONE;\r
+ end if;\r
+\r
+ when S_DONE =>\r
+ sclk_o <= '1';\r
+ sequence_done_o_x <= '1';\r
+ NEXT_STATE <= S_IDLE;\r
+\r
+ end case;\r
+ end process PROC_READ_BYTE;\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- Output Signals\r
+ -----------------------------------------------------------------------------\r
+\r
+ SEQUENCE_DONE_OUT <= sequence_done_o;\r
+ BYTE_OUT <= spi_byte;\r
+ \r
+ -- I2c Outputs\r
+ SCLK_OUT <= sclk_o;\r
+ \r
+end Behavioral;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.nxyter_components.all;\r
+\r
+\r
+entity adc_spi_sendbyte is\r
+ generic (\r
+ SPI_SPEED : unsigned(7 downto 0) := x"32"\r
+ );\r
+ port(\r
+ CLK_IN : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ START_IN : in std_logic;\r
+ BYTE_IN : in std_logic_vector(7 downto 0);\r
+ SEQUENCE_DONE_OUT : out std_logic;\r
+\r
+ -- SPI connections\r
+ SCLK_OUT : out std_logic;\r
+ SDIO_OUT : out std_logic\r
+ );\r
+end entity;\r
+\r
+architecture Behavioral of adc_spi_sendbyte is\r
+\r
+ -- Send Byte \r
+ signal sclk_o : std_logic;\r
+ signal sdio_o : std_logic;\r
+ signal spi_start : std_logic;\r
+\r
+ signal sequence_done_o : std_logic;\r
+ signal spi_byte : unsigned(7 downto 0);\r
+ signal bit_ctr : unsigned(3 downto 0);\r
+ signal wait_timer_init : unsigned(7 downto 0);\r
+\r
+ signal sequence_done_o_x : std_logic;\r
+ signal spi_byte_x : unsigned(7 downto 0);\r
+ signal bit_ctr_x : unsigned(3 downto 0);\r
+ signal wait_timer_init_x : unsigned(7 downto 0);\r
+ \r
+ type STATES is (S_IDLE,\r
+ S_SET_SDIO,\r
+ S_SET_SCLK,\r
+ S_NEXT_BIT,\r
+ S_DONE\r
+ );\r
+ signal STATE, NEXT_STATE : STATES;\r
+ \r
+ -- Wait Timer\r
+ signal wait_timer_done : std_logic;\r
+\r
+begin\r
+\r
+ -- Timer\r
+ nx_timer_1: nx_timer\r
+ generic map (\r
+ CTR_WIDTH => 8\r
+ )\r
+ port map (\r
+ CLK_IN => CLK_IN,\r
+ RESET_IN => RESET_IN,\r
+ TIMER_START_IN => wait_timer_init,\r
+ TIMER_DONE_OUT => wait_timer_done\r
+ );\r
+\r
+\r
+ PROC_SEND_BYTE_TRANSFER: process(CLK_IN)\r
+ begin \r
+ if( rising_edge(CLK_IN) ) then\r
+ if( RESET_IN = '1' ) then\r
+ sequence_done_o <= '0';\r
+ bit_ctr <= (others => '0');\r
+ wait_timer_init <= (others => '0');\r
+ STATE <= S_IDLE;\r
+ else\r
+ sequence_done_o <= sequence_done_o_x;\r
+ spi_byte <= spi_byte_x;\r
+ bit_ctr <= bit_ctr_x;\r
+ wait_timer_init <= wait_timer_init_x;\r
+ STATE <= NEXT_STATE;\r
+ end if;\r
+ end if;\r
+ end process PROC_SEND_BYTE_TRANSFER; \r
+ \r
+ PROC_SEND_BYTE: process(STATE)\r
+ begin \r
+ sdio_o <= '0';\r
+ sclk_o <= '0';\r
+ sequence_done_o_x <= '0';\r
+ spi_byte_x <= spi_byte;\r
+ bit_ctr_x <= bit_ctr; \r
+ wait_timer_init_x <= (others => '0');\r
+ \r
+ case STATE is\r
+ when S_IDLE =>\r
+ if (START_IN = '1') then\r
+ spi_byte_x <= BYTE_IN;\r
+ bit_ctr_x <= x"7";\r
+ wait_timer_init_x <= SPI_SPEED srl 1;\r
+ NEXT_STATE <= S_SET_SDIO;\r
+ else\r
+ NEXT_STATE <= S_IDLE;\r
+ end if;\r
+\r
+ when S_SET_SDIO =>\r
+ sdio_o <= spi_byte(7);\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_SET_SDIO;\r
+ else\r
+ wait_timer_init_x <= SPI_SPEED srl 1;\r
+ NEXT_STATE <= S_SET_SCLK;\r
+ end if;\r
+ \r
+ when S_SET_SCLK =>\r
+ sdio_o <= spi_byte(7);\r
+ sclk_o <= '1';\r
+ if (wait_timer_done = '0') then\r
+ NEXT_STATE <= S_SET_SCLK;\r
+ else\r
+ NEXT_STATE <= S_NEXT_BIT;\r
+ end if;\r
+ \r
+ when S_NEXT_BIT =>\r
+ sdio_o <= spi_byte(7);\r
+ sclk_o <= '1';\r
+ if (bit_ctr > 0) then\r
+ bit_ctr_x <= bit_ctr - 1;\r
+ spi_byte_x <= spi_byte sll 1;\r
+ wait_timer_init_x <= SPI_SPEED srl 1;\r
+ NEXT_STATE <= S_SET_SDIO;\r
+ else\r
+ NEXT_STATE <= S_DONE;\r
+ end if;\r
+\r
+ when S_DONE =>\r
+ sdio_o <= spi_byte(7);\r
+ sclk_o <= '1';\r
+ sequence_done_o_x <= '1';\r
+ NEXT_STATE <= S_IDLE;\r
+ \r
+ end case;\r
+ end process PROC_SEND_BYTE;\r
+\r
+ -----------------------------------------------------------------------------\r
+ -- Output Signals\r
+ -----------------------------------------------------------------------------\r
+\r
+ SEQUENCE_DONE_OUT <= sequence_done_o;\r
+ \r
+ -- SPI Outputs\r
+ SDIO_OUT <= sdio_o;\r
+ SCLK_OUT <= sclk_o;\r
+ \r
+end Behavioral;\r
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+library work;
+use work.nxyter_components.all;
+
+entity nx_data_buffer is
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+
+ -- Data Buffer FIFO
+ FIFO_DATA_IN : std_logic_vector(31 downto 0);
+ FIFO_WRITE_ENABLE_IN : std_logic;
+ FIFO_READ_ENABLE_IN : std_logic;
+
+ -- Slave bus
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic
+ );
+
+end nx_data_buffer;
+
+architecture Behavioral of nx_data_buffer is
+
+-- FIFO Handler
+ signal fifo_o : std_logic_vector(31 downto 0);
+ signal fifo_empty : std_logic;
+ signal fifo_full : std_logic;
+ signal fifo_read_enable : std_logic;
+ signal fifo_write_enable : std_logic;
+
+-- Slave Bus
+ signal slv_data_out_o : std_logic_vector(31 downto 0);
+ signal slv_no_more_data_o : std_logic;
+ signal slv_unknown_addr_o : std_logic;
+ signal slv_ack_o : std_logic;
+
+ signal register_fifo_status : std_logic_vector(31 downto 0);
+ signal register_write_enable : std_logic;
+
+begin
+
+-------------------------------------------------------------------------------
+-- FIFO Handler
+-------------------------------------------------------------------------------
+ fifo_32_data_1: fifo_32_data
+ port map (
+ Data => FIFO_DATA_IN,
+ Clock => CLK_IN,
+ WrEn => fifo_write_enable,
+ RdEn => fifo_read_enable,
+ Reset => RESET_IN,
+ Q => fifo_o,
+ Empty => fifo_empty,
+ Full => fifo_full
+ );
+
+ PROC_FIFO_HANDLER: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ fifo_write_enable <= '0';
+ fifo_read_enable <= '0';
+ else
+ fifo_write_enable <= '1';
+ fifo_read_enable <= '1';
+
+ if (fifo_full = '1'
+ or FIFO_WRITE_ENABLE_IN = '0'
+ or register_write_enable <= '0') then
+ fifo_write_enable <= '0';
+ end if;
+
+ if (fifo_empty = '1' or FIFO_READ_ENABLE_IN = '0') then
+ fifo_read_enable <= '0';
+ end if;
+
+ end if;
+ end if;
+ end process PROC_FIFO_HANDLER;
+
+-------------------------------------------------------------------------------
+-- Slave Bus Slow Control
+-------------------------------------------------------------------------------
+
+ register_fifo_status(0) <= fifo_write_enable;
+ register_fifo_status(1) <= fifo_full;
+ register_fifo_status(3 downto 2) <= (others => '0');
+ register_fifo_status(4) <= fifo_read_enable;
+ register_fifo_status(5) <= fifo_empty;
+ register_fifo_status(7 downto 6) <= (others => '0');
+ register_fifo_status(31 downto 8) <= (others => '0');
+
+
+ PROC_SLAVE_BUS: process(CLK_IN)
+ begin
+ if( rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ slv_data_out_o <= (others => '0');
+ slv_ack_o <= '0';
+ slv_unknown_addr_o <= '0';
+ slv_no_more_data_o <= '0';
+ register_write_enable <= '0';
+ else
+ slv_data_out_o <= (others => '0');
+ slv_ack_o <= '1';
+ slv_unknown_addr_o <= '0';
+ slv_no_more_data_o <= '0';
+
+ if (SLV_READ_IN = '1') then
+ case SLV_ADDR_IN is
+ when x"0000" => if (fifo_empty = '1') then
+ slv_no_more_data_o <= '1';
+ else
+ slv_data_out_o <= fifo_o;
+ slv_ack_o <= '1';
+ end if;
+ when x"0001" => slv_data_out_o <= register_fifo_status;
+ when others => slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
+ end case;
+ elsif (SLV_WRITE_IN = '1') then
+ case SLV_ADDR_IN is
+ when x"0001" => register_write_enable <= SLV_DATA_IN(0);
+ slv_ack_o <= '1';
+ when others => slv_unknown_addr_o <= '1';
+ slv_ack_o <= '0';
+ end case;
+ else
+ slv_ack_o <= '0';
+ end if;
+ end if;
+ end if;
+ end process PROC_SLAVE_BUS;
+
+-- Output Signals
+ SLV_DATA_OUT <= slv_data_out_o;
+ SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
+ SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
+ SLV_ACK_OUT <= slv_ack_o;
+
+end Behavioral;
\r
entity nx_i2c_master is\r
generic (\r
- i2c_speed : unsigned(11 downto 0) := x"3e8"\r
+ I2C_SPEED : unsigned(11 downto 0) := x"3e8"\r
);\r
port(\r
CLK_IN : in std_logic;\r
signal i2c_busy_x : std_logic;\r
signal startstop_select_x : std_logic;\r
signal startstop_seq_start_x : std_logic;\r
- signal wait_timer_init_x : std_logic_vector(11 downto 0);\r
signal sendbyte_seq_start_x : std_logic;\r
signal sendbyte_byte_x : std_logic_vector(7 downto 0);\r
signal readbyte_seq_start_x : std_logic;\r
);\r
signal STATE, NEXT_STATE : STATES;\r
\r
- \r
- -- I2C Timer\r
- signal wait_timer_init : unsigned(11 downto 0);\r
- signal wait_timer_done : std_logic;\r
- \r
-- TRBNet Slave Bus \r
signal slv_data_out_o : std_logic_vector(31 downto 0);\r
signal slv_no_more_data_o : std_logic;\r
\r
begin\r
\r
- -- Timer\r
- nx_timer_1: nx_timer\r
- generic map (\r
- CTR_WIDTH => 12\r
- )\r
- port map (\r
- CLK_IN => CLK_IN,\r
- RESET_IN => RESET_IN,\r
- TIMER_START_IN => wait_timer_init,\r
- TIMER_DONE_OUT => wait_timer_done\r
- );\r
-\r
-- Start / Stop Sequence\r
nx_i2c_startstop_1: nx_i2c_startstop\r
generic map (\r
- i2c_speed => i2c_speed\r
+ I2C_SPEED => I2C_SPEED\r
)\r
port map (\r
CLK_IN => CLK_IN,\r
\r
nx_i2c_sendbyte_1: nx_i2c_sendbyte\r
generic map (\r
- i2c_speed => i2c_speed\r
+ I2C_SPEED => I2C_SPEED\r
)\r
port map (\r
CLK_IN => CLK_IN,\r
\r
nx_i2c_readbyte_1: nx_i2c_readbyte\r
generic map (\r
- i2c_speed => i2c_speed\r
+ I2C_SPEED => I2C_SPEED\r
)\r
port map (\r
CLK_IN => CLK_IN,\r
sendbyte_seq_start <= '0';\r
readbyte_seq_start <= '0';\r
sendbyte_byte <= (others => '0');\r
- wait_timer_init <= (others => '0');\r
reg_data <= (others => '0');\r
read_seq_ctr <= '0';\r
STATE <= S_RESET;\r
sendbyte_seq_start <= sendbyte_seq_start_x;\r
readbyte_seq_start <= readbyte_seq_start_x;\r
sendbyte_byte <= sendbyte_byte_x;\r
- wait_timer_init <= wait_timer_init_x;\r
reg_data <= reg_data_x;\r
read_seq_ctr <= read_seq_ctr_x;\r
STATE <= NEXT_STATE;\r
sendbyte_seq_start_x <= '0';\r
sendbyte_byte_x <= (others => '0');\r
readbyte_seq_start_x <= '0';\r
- wait_timer_init_x <= (others => '0');\r
reg_data_x <= reg_data;\r
read_seq_ctr_x <= read_seq_ctr;\r
\r
-- D[23:16] I2C_ADDRESS address of I2C chip\r
-- D[15:8] I2C_CMD command byte for access\r
-- D[7:0] I2C_DATA data to be written\r
- -- \r
-- \r
-- Read bit definition\r
-- ===================\r
-- \r
- -- D[31:24] status status information\r
-- D[31] RUNNING whatever\r
-- D[30] I2C_DONE whatever\r
-- D[29] ERROR_RADDACK no acknowledge for repeated address byte\r
\r
entity nx_i2c_readbyte is\r
generic (\r
- i2c_speed : unsigned(11 downto 0) := x"3e8"\r
+ I2C_SPEED : unsigned(11 downto 0) := x"3e8"\r
);\r
port(\r
CLK_IN : in std_logic;\r
signal i2c_byte : unsigned(7 downto 0);\r
signal bit_ctr : unsigned(3 downto 0);\r
signal i2c_ack_o : std_logic;\r
- signal wait_timer_init : unsigned(11 downto 0);\r
+ signal wait_timer_init : unsigned(11 downto 0);\r
\r
signal sequence_done_o_x : std_logic;\r
signal i2c_byte_x : unsigned(7 downto 0);\r
when S_INIT =>\r
sda_o <= '0';\r
scl_o <= '0';\r
- wait_timer_init_x <= i2c_speed srl 1;\r
+ wait_timer_init_x <= I2C_SPEED srl 1;\r
NEXT_STATE <= S_INIT_WAIT;\r
\r
when S_INIT_WAIT =>\r
when S_READ_BYTE =>\r
scl_o <= '0';\r
bit_ctr_x <= x"7";\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_UNSET_SCL1;\r
\r
when S_UNSET_SCL1 =>\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_UNSET_SCL1;\r
else\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_SET_SCL1;\r
end if;\r
\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_SET_SCL1;\r
else\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_GET_BIT;\r
end if;\r
\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_SET_SCL2;\r
else\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_UNSET_SCL2;\r
end if;\r
\r
if (bit_ctr > 0) then\r
bit_ctr_x <= bit_ctr - 1;\r
i2c_byte_x <= i2c_byte sll 1;\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_UNSET_SCL1;\r
else\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_SET_ACK;\r
end if;\r
\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_SET_ACK;\r
else\r
- wait_timer_init_x <= i2c_speed srl 1;\r
+ wait_timer_init_x <= I2C_SPEED srl 1;\r
NEXT_STATE <= S_ACK_SET_SCL;\r
end if;\r
\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_ACK_SET_SCL;\r
else\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_ACK_UNSET_SCL;\r
end if; \r
\r
\r
entity nx_i2c_sendbyte is\r
generic (\r
- i2c_speed : unsigned(11 downto 0) := x"3e8"\r
+ I2C_SPEED : unsigned(11 downto 0) := x"3e8"\r
);\r
port(\r
CLK_IN : in std_logic;\r
signal i2c_byte : unsigned(7 downto 0);\r
signal bit_ctr : unsigned(3 downto 0);\r
signal i2c_ack_o : std_logic;\r
- signal wait_timer_init : unsigned(11 downto 0);\r
+ signal wait_timer_init : unsigned(11 downto 0);\r
\r
signal sequence_done_o_x : std_logic;\r
signal i2c_byte_x : unsigned(7 downto 0);\r
when S_INIT =>\r
sda_o <= '0';\r
scl_o <= '0';\r
- wait_timer_init_x <= i2c_speed srl 1;\r
+ wait_timer_init_x <= I2C_SPEED srl 1;\r
NEXT_STATE <= S_INIT_WAIT;\r
\r
when S_INIT_WAIT =>\r
sda_o <= '0';\r
scl_o <= '0';\r
bit_ctr_x <= x"7";\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_SET_SDA;\r
\r
when S_SET_SDA =>\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_SET_SDA;\r
else\r
- wait_timer_init_x <= i2c_speed srl 1;\r
+ wait_timer_init_x <= I2C_SPEED srl 1;\r
NEXT_STATE <= S_SET_SCL;\r
end if;\r
\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_SET_SCL;\r
else\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_UNSET_SCL;\r
end if;\r
\r
if (bit_ctr > 0) then\r
bit_ctr_x <= bit_ctr - 1;\r
i2c_byte_x <= i2c_byte sll 1;\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_SET_SDA;\r
else\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_GET_ACK;\r
end if;\r
\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_GET_ACK;\r
else\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_ACK_SET_SCL;\r
end if;\r
\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_ACK_SET_SCL;\r
else\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_STORE_ACK;\r
end if; \r
\r
NEXT_STATE <= S_STORE_ACK;\r
else\r
i2c_ack_o_x <= not SDA_IN;\r
- wait_timer_init_x <= i2c_speed srl 2;\r
+ wait_timer_init_x <= I2C_SPEED srl 2;\r
NEXT_STATE <= S_ACK_UNSET_SCL;\r
end if;\r
\r
\r
entity nx_i2c_startstop is\r
generic (\r
- i2c_speed : unsigned(11 downto 0) := x"3e8"\r
+ I2C_SPEED : unsigned(11 downto 0) := x"3e8"\r
);\r
port(\r
CLK_IN : in std_logic;\r
\r
-- I2C START Sequence \r
when S_START =>\r
- wait_timer_init_x <= i2c_speed srl 1;\r
+ wait_timer_init_x <= I2C_SPEED srl 1;\r
NEXT_STATE <= S_WAIT_START_1;\r
\r
when S_WAIT_START_1 =>\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_WAIT_START_1;\r
else\r
- wait_timer_init_x <= i2c_speed srl 1;\r
+ wait_timer_init_x <= I2C_SPEED srl 1;\r
NEXT_STATE <= S_WAIT_START_2;\r
end if;\r
\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_WAIT_START_2;\r
else\r
- wait_timer_init_x <= i2c_speed srl 1;\r
+ wait_timer_init_x <= I2C_SPEED srl 1;\r
NEXT_STATE <= S_WAIT_START_3;\r
end if;\r
\r
when S_STOP =>\r
sda_o <= '0';\r
scl_o <= '0';\r
- wait_timer_init_x <= i2c_speed srl 1;\r
+ wait_timer_init_x <= I2C_SPEED srl 1;\r
NEXT_STATE <= S_WAIT_STOP_1;\r
\r
when S_WAIT_STOP_1 =>\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_WAIT_STOP_1;\r
else\r
- wait_timer_init_x <= i2c_speed srl 1;\r
+ wait_timer_init_x <= I2C_SPEED srl 1;\r
NEXT_STATE <= S_WAIT_STOP_2;\r
end if;\r
\r
if (wait_timer_done = '0') then\r
NEXT_STATE <= S_WAIT_STOP_2;\r
else\r
- wait_timer_init_x <= i2c_speed srl 1;\r
+ wait_timer_init_x <= I2C_SPEED srl 1;\r
NEXT_STATE <= S_WAIT_STOP_3;\r
end if;\r
\r
if( RESET_IN = '1' ) then\r
frame_clock_ctr <= (others => '0');\r
nx_frame_clock_o <= '0';\r
- frame_tag_o <= '1';\r
+ frame_tag_o <= '0';\r
else\r
case frame_clock_ctr is\r
\r
signal slv_unknown_addr : std_logic_vector(8-1 downto 0);
-- I2C Master
--- ADCM signal i2c_sda_o : std_logic;
--- ADCM signal i2c_sda_i : std_logic;
--- ADCM signal i2c_scl_o : std_logic;
--- ADCM signal i2c_scl_i : std_logic;
signal i2c_sm_reset_o : std_logic;
signal i2c_reg_reset_o : std_logic;
-------------------------------------------------------------------------------
-- DEBUG
-------------------------------------------------------------------------------
- DEBUG_LINE_OUT(0) <= CLK_IN;
- DEBUG_LINE_OUT(1) <= NX_CLK128_IN;
- DEBUG_LINE_OUT(2) <= ADC_SC_CLK32_OUT;
- DEBUG_LINE_OUT(3) <= ADC_FCLK_IN;
- DEBUG_LINE_OUT(4) <= ADC_DCLK_IN;
- DEBUG_LINE_OUT(5) <= ADC_NX_IN;
- DEBUG_LINE_OUT(6) <= ADC_A_IN;
- DEBUG_LINE_OUT(7) <= ADC_B_IN;
- DEBUG_LINE_OUT(8) <= ADC_D_IN;
-
- DEBUG_LINE_OUT(15 downto 9) <= (others => '0');
+-- DEBUG_LINE_OUT(0) <= CLK_IN;
+-- DEBUG_LINE_OUT(1) <= NX_CLK128_IN;
+-- DEBUG_LINE_OUT(2) <= ADC_SC_CLK32_OUT;
+-- DEBUG_LINE_OUT(3) <= ADC_FCLK_IN;
+-- DEBUG_LINE_OUT(4) <= ADC_DCLK_IN;
+-- DEBUG_LINE_OUT(5) <= ADC_NX_IN;
+-- DEBUG_LINE_OUT(6) <= ADC_A_IN;
+-- DEBUG_LINE_OUT(7) <= ADC_B_IN;
+-- DEBUG_LINE_OUT(8) <= ADC_D_IN;
+--
+-- DEBUG_LINE_OUT(15 downto 9) <= (others => '0');
--
-- DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN;
-- DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN;
-- Port Maps
-------------------------------------------------------------------------------
-
-
pll_nx_clk256_1: pll_nx_clk256
port map (
CLK => CLK_IN,
THE_BUS_HANDLER: trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 4,
+ PORT_NUMBER => 5,
PORT_ADDRESSES => ( 0 => x"0000", -- Control Register Handler
1 => x"0040", -- I2C master
2 => x"0100", -- Timestamp Fifo
3 => x"0200", -- Data Buffer
- -- 3 => x"d100", -- SPI data memory
+ 4 => x"0060", -- SPI Master
others => x"0000"),
PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler
1 => 0, -- I2C master
2 => 1, -- Timestamp Fifo
3 => 1, -- Data Buffer
- -- 3 => 6, -- SPI data memory
+ 4 => 0, -- Master
others => 0)
)
port map(
BUS_WRITE_ACK_IN(3) => slv_ack(3),
BUS_NO_MORE_DATA_IN(3) => slv_no_more_data(3),
BUS_UNKNOWN_ADDR_IN(3) => slv_unknown_addr(3),
-
+
+ -- SPI master
+ BUS_READ_ENABLE_OUT(4) => slv_read(4),
+ BUS_WRITE_ENABLE_OUT(4) => slv_write(4),
+ BUS_DATA_OUT(4*32+31 downto 4*32) => slv_data_wr(4*32+31 downto 4*32),
+ BUS_DATA_IN(4*32+31 downto 4*32) => slv_data_rd(4*32+31 downto 4*32),
+ BUS_ADDR_OUT(4*16+15 downto 4*16) => open,
+ BUS_TIMEOUT_OUT(4) => open,
+ BUS_DATAREADY_IN(4) => slv_ack(4),
+ BUS_WRITE_ACK_IN(4) => slv_ack(4),
+ BUS_NO_MORE_DATA_IN(4) => slv_no_more_data(4),
+ BUS_UNKNOWN_ADDR_IN(4) => slv_unknown_addr(4),
+
---- SPI control registers
--BUS_READ_ENABLE_OUT(4) => slv_read(4),
--BUS_WRITE_ENABLE_OUT(4) => slv_write(4),
nx_i2c_master_1: nx_i2c_master
generic map (
- i2c_speed => x"3e8"
+ I2C_SPEED => x"3e8"
)
port map (
CLK_IN => CLK_IN,
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1),
DEBUG_OUT => open
);
+
+-------------------------------------------------------------------------------
+-- SPI master block to access the ADC
+-------------------------------------------------------------------------------
+ adc_spi_master_1: adc_spi_master
+ generic map (
+ SPI_SPEED => x"32"
+ )
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ SCLK_OUT => SPI_SCLK_OUT,
+ SDIO_INOUT => SPI_SDIO_INOUT,
+ CSB_OUT => SPI_CSB_OUT,
+ SLV_READ_IN => slv_read(4),
+ SLV_WRITE_IN => slv_write(4),
+ SLV_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),
+ SLV_DATA_IN => slv_data_wr(4*32+31 downto 4*32),
+ SLV_ACK_OUT => slv_ack(4),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(4),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4),
+ DEBUG_OUT => DEBUG_LINE_OUT
+ -- DEBUG_OUT => open
+ );
+
-------------------------------------------------------------------------------
-- nXyter TimeStamp Read
-------------------------------------------------------------------------------
component nx_i2c_master
generic (
- i2c_speed : unsigned(11 downto 0)
+ I2C_SPEED : unsigned(11 downto 0)
);
port (
CLK_IN : in std_logic;
);
end component;
-component nx_timer
- generic (
- CTR_WIDTH : integer
- );
- port (
- CLK_IN : in std_logic;
- RESET_IN : in std_logic;
- TIMER_START_IN : in unsigned(11 downto 0);
- TIMER_DONE_OUT : out std_logic
- );
-end component;
-
component nx_i2c_startstop
generic (
- i2c_speed : unsigned(11 downto 0));
+ I2C_SPEED : unsigned(11 downto 0)
+ );
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
component nx_i2c_sendbyte
generic (
- i2c_speed : unsigned(11 downto 0)
+ I2C_SPEED : unsigned(11 downto 0)
);
port (
CLK_IN : in std_logic;
component nx_i2c_readbyte
generic (
- i2c_speed : unsigned(11 downto 0)
+ I2C_SPEED : unsigned(11 downto 0)
);
port (
CLK_IN : in std_logic;
);
end component;
+-------------------------------------------------------------------------------
+-- ADC SPI Interface
+-------------------------------------------------------------------------------
+
+component adc_spi_master
+ generic (
+ SPI_SPEED : unsigned(7 downto 0)
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ SCLK_OUT : out std_logic;
+ SDIO_INOUT : inout std_logic;
+ CSB_OUT : out std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_OUT : out std_logic_vector(15 downto 0)
+ );
+end component;
+
+component adc_spi_sendbyte
+ generic (
+ SPI_SPEED : unsigned(7 downto 0)
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ START_IN : in std_logic;
+ BYTE_IN : in std_logic_vector(7 downto 0);
+ SEQUENCE_DONE_OUT : out std_logic;
+ SCLK_OUT : out std_logic;
+ SDIO_OUT : out std_logic
+ );
+end component;
+
+component adc_spi_readbyte
+ generic (
+ SPI_SPEED : unsigned(7 downto 0)
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ START_IN : in std_logic;
+ BYTE_OUT : out std_logic_vector(7 downto 0);
+ SEQUENCE_DONE_OUT : out std_logic;
+ SDIO_IN : in std_logic;
+ SCLK_OUT : out std_logic
+ );
+end component;
+
-------------------------------------------------------------------------------
-- TRBNet Registers
-------------------------------------------------------------------------------
component Gray_Decoder
generic (
- WIDTH : integer);
+ WIDTH : integer
+ );
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
component Gray_Encoder
generic (
- WIDTH : integer);
+ WIDTH : integer
+ );
port (
CLK_IN : in std_logic;
RESET_IN : in std_logic;
LOCK : out std_logic);
end component;
+-------------------------------------------------------------------------------
+-- Misc Tools
+-------------------------------------------------------------------------------
+
+component nx_timer
+ generic (
+ CTR_WIDTH : integer
+ );
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ TIMER_START_IN : in unsigned(CTR_WIDTH - 1 downto 0);
+ TIMER_DONE_OUT : out std_logic
+ );
+end component;
+
-------------------------------------------------------------------------------
-- Simulations
-------------------------------------------------------------------------------
);
end component;
-
end package;
add_file -vhdl -lib "work" "./source/nxyter_components.vhd"
add_file -vhdl -lib "work" "./source/nxyter.vhd"
-add_file -vhdl -lib "work" "./source/slave_bus.vhd"
-#add_file -vhdl -lib "work" "./source/slv_ped_thr_mem.vhd"
-add_file -vhdl -lib "work" "./source/slv_register.vhd"
-#add_file -vhdl -lib "work" "./source/gray_decoder.vhd"
-
-add_file -vhdl -lib "work" "./source/i2c_gstart.vhd"
-add_file -vhdl -lib "work" "./source/i2c_master.vhd"
-add_file -vhdl -lib "work" "./source/i2c_sendb.vhd"
-add_file -vhdl -lib "work" "./source/i2c_slim.vhd"
-
+add_file -vhdl -lib "work" "./source/pll_nx_clk256.vhd"
+add_file -vhdl -lib "work" "./source/nxyter_registers.vhd"
+add_file -vhdl -lib "work" "./source/nx_timestamp_fifo_read.vhd"
+add_file -vhdl -lib "work" "./source/fifo_dc_9to36.vhd"
+add_file -vhdl -lib "work" "./source/level_to_pulse.vhd"
+add_file -vhdl -lib "work" "./source/gray_decoder.vhd"
+add_file -vhdl -lib "work" "./source/gray_encoder.vhd"
+add_file -vhdl -lib "work" "./source/nx_data_buffer.vhd"
+add_file -vhdl -lib "work" "./source/fifo_32_data.vhd"
+add_file -vhdl -lib "work" "./source/nx_timer.vhd"
+
+add_file -vhdl -lib "work" "./source/nx_i2c_master.vhd"
+add_file -vhdl -lib "work" "./source/nx_i2c_startstop.vhd"
+add_file -vhdl -lib "work" "./source/nx_i2c_sendbyte.vhd"
+add_file -vhdl -lib "work" "./source/nx_i2c_readbyte.vhd"
+
+add_file -vhdl -lib "work" "./source/adc_spi_master.vhd"
+add_file -vhdl -lib "work" "./source/adc_spi_sendbyte.vhd"
+add_file -vhdl -lib "work" "./source/adc_spi_readbyte.vhd"
+
+add_file -vhdl -lib "work" "./source/nx_timestamp_sim.vhd"
NX1_RESET_OUT : out std_logic;
NX1_I2C_SDA_INOUT : inout std_logic;
- NX1_I2C_SCL_OUT : out std_logic;
+ NX1_I2C_SCL_INOUT : inout std_logic;
NX1_I2C_SM_RESET_OUT : out std_logic;
NX1_I2C_REG_RESET_OUT : out std_logic;
NX1_SPI_SCLK_OUT : out std_logic;
- NX1_SPI_SDIO_INOUT : in std_logic;
+ NX1_SPI_SDIO_INOUT : inout std_logic;
NX1_SPI_CSB_OUT : out std_logic;
NX1_CLK128_IN : in std_logic;
NX1_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
NX2_RESET_OUT : out std_logic;
NX2_I2C_SDA_INOUT : inout std_logic;
- NX2_I2C_SCL_OUT : out std_logic;
+ NX2_I2C_SCL_INOUT : inout std_logic;
NX2_I2C_SM_RESET_OUT : out std_logic;
NX2_I2C_REG_RESET_OUT : out std_logic;
NX2_SPI_SCLK_OUT : out std_logic;
- NX2_SPI_SDIO_INOUT : in std_logic;
+ NX2_SPI_SDIO_INOUT : inout std_logic;
NX2_SPI_CSB_OUT : out std_logic;
NX2_CLK128_IN : in std_logic;
- NX2_IN : in std_logic_vector (7 downto 0);
+ NX2_TIMESTAMP_IN : in std_logic_vector (7 downto 0);
NX2_CLK256A_OUT : out std_logic;
NX2_TESTPULSE_OUT : out std_logic;
NX2_ADC_FCLK_IN : in std_logic;
signal nx1_regio_no_more_data_out : std_logic;
signal nx1_regio_unknown_addr_out : std_logic;
+ signal nx1_timestamp_sim_o : std_logic_vector(7 downto 0);
+ signal nx1_clk128_sim_o : std_logic;
+
-- nXyter 1 Regio Bus
signal nx2_regio_addr_in : std_logic_vector (15 downto 0);
signal nx2_regio_data_in : std_logic_vector (31 downto 0);
---------------------------------------------------------------------------
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
- PORT_NUMBER => 4,
+ PORT_NUMBER => 3,
PORT_ADDRESSES => (0 => x"d000",
1 => x"d100",
2 => x"8000",
- 3 => x"9000",
+ -- 3 => x"9000",
others => x"0000"),
PORT_ADDR_MASK => (0 => 1,
1 => 6,
- 2 => 15,
- 3 => 15,
+ 2 => 12,
+ -- 3 => 12,
others => 0)
)
port map(
DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
--Bus Handler (SPI CTRL)
- BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
- BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
- BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
- BUS_ADDR_OUT(0*16) => spictrl_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
- BUS_DATAREADY_IN(0) => spictrl_ack,
- BUS_WRITE_ACK_IN(0) => spictrl_ack,
- BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
- BUS_UNKNOWN_ADDR_IN(0) => '0',
-
- --Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(1) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
- BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
- BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
- BUS_DATAREADY_IN(1) => spimem_ack,
- BUS_WRITE_ACK_IN(1) => spimem_ack,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => '0',
+ BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
+ BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
+ BUS_ADDR_OUT(0*16) => spictrl_addr,
+ BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+ BUS_TIMEOUT_OUT(0) => open,
+ BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
+ BUS_DATAREADY_IN(0) => spictrl_ack,
+ BUS_WRITE_ACK_IN(0) => spictrl_ack,
+ BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
+ BUS_UNKNOWN_ADDR_IN(0) => '0',
+
+ --Bus Handler (SPI Memory)
+ BUS_READ_ENABLE_OUT(1) => spimem_read_en,
+ BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
+ BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
+ BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
+ BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+ BUS_TIMEOUT_OUT(1) => open,
+ BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
+ BUS_DATAREADY_IN(1) => spimem_ack,
+ BUS_WRITE_ACK_IN(1) => spimem_ack,
+ BUS_NO_MORE_DATA_IN(1) => '0',
+ BUS_UNKNOWN_ADDR_IN(1) => '0',
--Bus Handler (nXyter1 trb_net16_regio_bus_handler)
- BUS_READ_ENABLE_OUT(2) => nx1_regio_read_enable_in,
- BUS_WRITE_ENABLE_OUT(2) => nx1_regio_write_enable_in,
- BUS_DATA_OUT(2*32+31 downto 2*32) => nx1_regio_data_in,
- BUS_ADDR_OUT(2*16+15 downto 2*16) => nx1_regio_addr_in,
- BUS_TIMEOUT_OUT(2) => nx1_regio_timeout_in,
- BUS_DATA_IN(2*32+31 downto 2*32) => nx1_regio_data_out,
- BUS_DATAREADY_IN(2) => nx1_regio_dataready_out,
- BUS_WRITE_ACK_IN(2) => nx1_regio_write_ack_out,
- BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out,
- BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out,
-
- --Bus Handler (nXyter2 trb_net16_regio_bus_handler)
- BUS_READ_ENABLE_OUT(3) => nx2_regio_read_enable_in,
- BUS_WRITE_ENABLE_OUT(3) => nx2_regio_write_enable_in,
- BUS_DATA_OUT(3*32+31 downto 3*32) => nx2_regio_data_in,
- BUS_ADDR_OUT(3*16+15 downto 3*16) => nx2_regio_addr_in,
- BUS_TIMEOUT_OUT(3) => nx2_regio_timeout_in,
- BUS_DATA_IN(3*32+31 downto 3*32) => nx2_regio_data_out,
- BUS_DATAREADY_IN(3) => nx2_regio_dataready_out,
- BUS_WRITE_ACK_IN(3) => nx2_regio_write_ack_out,
- BUS_NO_MORE_DATA_IN(3) => nx2_regio_no_more_data_out,
- BUS_UNKNOWN_ADDR_IN(3) => nx2_regio_unknown_addr_out,
+ BUS_READ_ENABLE_OUT(2) => nx1_regio_read_enable_in,
+ BUS_WRITE_ENABLE_OUT(2) => nx1_regio_write_enable_in,
+ BUS_DATA_OUT(2*32+31 downto 2*32) => nx1_regio_data_in,
+ BUS_ADDR_OUT(2*16+11 downto 2*16) => nx1_regio_addr_in(11 downto 0),
+ BUS_ADDR_OUT(2*16+15 downto 2*16+12) => open,
+ BUS_TIMEOUT_OUT(2) => open, --nx1_regio_timeout_in,
+ BUS_DATA_IN(2*32+31 downto 2*32) => nx1_regio_data_out,
+ BUS_DATAREADY_IN(2) => nx1_regio_dataready_out,
+ BUS_WRITE_ACK_IN(2) => nx1_regio_write_ack_out,
+ BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out,
+ BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out,
+
+ -- --Bus Handler (nXyter2 trb_net16_regio_bus_handler)
+ -- BUS_READ_ENABLE_OUT(3) => nx2_regio_read_enable_in,
+ -- BUS_WRITE_ENABLE_OUT(3) => nx2_regio_write_enable_in,
+ -- BUS_DATA_OUT(3*32+31 downto 3*32) => nx2_regio_data_in,
+ -- BUS_ADDR_OUT(3*16+15 downto 3*16) => nx2_regio_addr_in,
+ -- BUS_TIMEOUT_OUT(3) => nx2_regio_timeout_in,
+ -- BUS_DATA_IN(3*32+31 downto 3*32) => nx2_regio_data_out,
+ -- BUS_DATAREADY_IN(3) => nx2_regio_dataready_out,
+ -- BUS_WRITE_ACK_IN(3) => nx2_regio_write_ack_out,
+ -- BUS_NO_MORE_DATA_IN(3) => nx2_regio_no_more_data_out,
+ -- BUS_UNKNOWN_ADDR_IN(3) => nx2_regio_unknown_addr_out,
STAT_DEBUG => open
);
RESET_IN => reset_i,
I2C_SDA_INOUT => NX1_I2C_SDA_INOUT,
- I2C_SCL_OUT => NX1_I2C_SCL_OUT,
+ I2C_SCL_INOUT => NX1_I2C_SCL_INOUT,
I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT,
I2C_REG_RESET_OUT => NX1_I2C_REG_RESET_OUT,
NX_CLK128_IN => NX1_CLK128_IN,
NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN,
+-- NX_CLK128_IN => nx1_clk128_sim_o,
+-- NX_TIMESTAMP_IN => nx1_timestamp_sim_o,
+
NX_RESET_OUT => NX1_RESET_OUT,
NX_CLK256A_OUT => NX1_CLK256A_OUT,
NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT,
REGIO_DATAREADY_OUT => nx1_regio_dataready_out,
REGIO_WRITE_ACK_OUT => nx1_regio_write_ack_out,
REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out,
- REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out
+ REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out,
+
+ CLK_128_IN => CLK_GPLL_LEFT,
+ DEBUG_LINE_OUT => TEST_LINE
+ -- DEBUG_LINE_OUT => open
);
+
+ -- TEST_LINE(0) <= clk_100_i;
+ -- TEST_LINE(1) <= clk_200_i;
+ -- TEST_LINE(2) <= NX1_CLK128_IN;
+ -- TEST_LINE(3) <= NX2_CLK128_IN;
+ -- TEST_LINE(7 downto 4) <= (others => '0');
+ -- TEST_LINE(11 downto 8) <= NX1_TIMESTAMP_IN(3 downto 0);
+ -- TEST_LINE(15 downto 12) <= NX2_TIMESTAMP_IN(3 downto 0);
+
+
+
+-------------------------------------------------------------------------------
+-- Timestamp Simulator
+-------------------------------------------------------------------------------
+-- nxyter_timestamp_sim_1: nxyter_timestamp_sim
+-- port map (
+-- CLK_IN => CLK_GPLL_LEFT,
+-- RESET_IN => reset_i,
+-- TIMESTAMP_OUT => nx1_timestamp_sim_o,
+-- CLK128_OUT => nx1_clk128_sim_o
+-- );
+
---------------------------------------------------------------------------
-- Test Connector - Logic Analyser
---------------------------------------------------------------------------
- TEST_LINE(15 downto 0) <= (others => '0');
-
+ -- TEST_LINE(15 downto 0) <= (others => '0');
+
end architecture;
jspc29 / trb3.git / commitdiff