added hld data file format to trb3docu

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index e24d3d889d74858fa7a40a551cb80544cd26a5df..7afb333db38ca6c0f0c594d2d362ed9ecdbf1a77 100644 (file)
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -89,7 +89,7 @@ The lower 16 Bit are used to identify the contents of the design and the AddOn b
   \item[5XXX]  use with General Purpose AddOn - with NIM connectors
   \item[6XXX]  use with Nxyter
   \item[7XXX]  use with 32PinAddOn
-  \item[8XXX]  uses RX clock as main internal clock
+  \item[9XXX]  use with ADC AddOn
   \item[X0nX]  contains $2^n$ TDC channels, single edge, n<8
   \item[X1nX]  contains $2^n$ TDC channels, double edge, n<8
   \item[X2XX]  contains a network hub
@@ -97,6 +97,7 @@ The lower 16 Bit are used to identify the contents of the design and the AddOn b
   \item[X8XX]  Double edge TDC realized with two single edge channels
   \item[XX8X]  Non-TDC (because of bad choice of encoding)
   \item[XX9X]  for MVD converter board 2013
+  \item[XXX1]  uses RX clock as main internal clock
 \end{description*}
 \end{description*}
 
@@ -126,6 +127,7 @@ All boards of a given type are accessible by a broadcast address at the same tim
  \item 0x44 for a design for FPGA 4 only
  \item 0x48 TDC design for peripheral FPGA
  \item 0x49 peripheral FPGA with Nxyter AddOn
+ \item 0x4b peripheral FPGA with ADC AddOn
  \item 0x4d peripheral FPGA for MAPS read-out
  \item 0x50 CBM-Rich
 \end{itemize*}

diff --git a/trb3/figures/hldfile.png b/trb3/figures/hldfile.png
new file mode 100644 (file)
index 0000000..fe716c6
Binary files /dev/null and b/trb3/figures/hldfile.png differ

diff --git a/trb3/figures/hldformat.png b/trb3/figures/hldformat.png
new file mode 100644 (file)
index 0000000..5637fab
Binary files /dev/null and b/trb3/figures/hldformat.png differ

diff --git a/trb3/hldfileformat.tex b/trb3/hldfileformat.tex
new file mode 100644 (file)
index 0000000..b251d8b
--- /dev/null
+++ b/trb3/hldfileformat.tex
@@ -0,0 +1,18 @@
+\section{Data File Format}
+The data in the hld file is binary data, organized in 32 Bit words. For historic reasons, some parts are big endian, some are little endian - check the existing data reading code for their detection method.
+Each event has an event header, followed by an arbitrary number of subevents. The subevents contain a header and a data block, consisting of subsubevents, which are data blocks from individual FPGAs. The structure is shown in figures \ref{fig:hldfile} and \ref{fig:hldheaders}.
+
+
+\begin{figure}[!ht]
+ \centering
+ \includegraphics[width=1.0\textwidth]{figures/hldfile.png}
+ \caption{The structure of the hld file.}
+ \label{fig:hldfile}
+\end{figure}
+
+\begin{figure}[!ht]
+ \centering
+ \includegraphics[width=1.0\textwidth]{figures/hldformat.png}
+ \caption{The structure of the event header and sub-event inside the hld file.}
+ \label{fig:hldheaders}
+\end{figure}
\ No newline at end of file

diff --git a/trb3/main.tex b/trb3/main.tex
index f0fe5a493700b93a9f3e3984a9ed1fd7cf9f7e59..6757662521afa04eb41f57ea40c155f350ac5a24 100644 (file)
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -230,7 +230,7 @@
 
 \cleardoublepage
 \input{trb3qs_part}
-
+\input{hldfileformat}
 
 \cleardoublepage
 \part{Synchronous TrbNet}

diff --git a/trb3/trb3qs_webinterface.tex b/trb3/trb3qs_webinterface.tex
index a243a2373bf0c84b013807c54e19d419073078b1..35202a7395d428e1feb623721b0a2256cc467a76 100644 (file)
--- a/trb3/trb3qs_webinterface.tex
+++ b/trb3/trb3qs_webinterface.tex
@@ -24,22 +24,4 @@ frequency 1~MHz is used as a trigger source.}
 \end{figure}
 
 
-\begin{figure}[!ht]
- \centering
- \includegraphics[width=1.0\textwidth]{trb3qs_img/TDCregs}
- \caption{TDC settings panel}
-\end{figure}
-
-\begin{figure}[!ht]
- \centering
- \includegraphics[width=1.0\textwidth]{trb3qs_img/GbEregs}
- \caption{Gigabit Ethernet settings panel}
-\end{figure}
-
-\begin{figure}[!ht]
- \centering
- \includegraphics[width=1.0\textwidth]{trb3qs_img/Threshreg}
- \caption{Threshold settings panel}
-\end{figure}
-