signal fifo_read_done : std_logic;
signal fifo_data : std_logic_vector(31 downto 0);
- signal fifo_read_enable_x : std_logic;
- signal fifo_read_busy_x : std_logic;
- signal fifo_no_data_x : std_logic;
- signal fifo_read_done_x : std_logic;
- signal fifo_data_x : std_logic_vector(31 downto 0);
-
type STATES is (S_IDLE,
S_NOP1,
S_NOP2,
S_READ_WORD
);
- signal STATE, NEXT_STATE: STATES;
+ signal STATE : STATES;
-- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
-- FIFO Output Handler
-----------------------------------------------------------------------------
- PROC_FIFO_READ_TRANSFER: process(CLK_IN)
+ PROC_FIFO_READ_WORD: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
- fifo_read_enable <= '0';
- fifo_read_busy <= '0';
- fifo_data <= (others => '0');
- fifo_read_done <= '0';
- fifo_no_data <= '1';
- STATE <= S_IDLE;
- else
- fifo_read_enable <= fifo_read_enable_x;
- fifo_read_busy <= fifo_read_busy_x;
- fifo_data <= fifo_data_x;
- fifo_read_done <= fifo_read_done_x;
- fifo_no_data <= fifo_no_data_x;
- STATE <= NEXT_STATE;
- end if;
- end if;
- end process PROC_FIFO_READ_TRANSFER;
-
- PROC_FIFO_READ_WORD: process(STATE,
- fifo_read_start,
- fifo_empty
- )
- begin
- fifo_read_busy_x <= '0';
- fifo_no_data_x <= '0';
- fifo_read_done_x <= '0';
- fifo_data_x <= (others => '0');
- fifo_read_enable_x <= '0';
-
- case STATE is
- when S_IDLE =>
- if (fifo_read_start = '1') then
- if (fifo_empty = '0') then
- fifo_read_enable_x <= '1';
- fifo_read_busy_x <= '1';
- NEXT_STATE <= S_NOP1;
- else
- fifo_no_data_x <= '1';
- fifo_read_done_x <= '1';
- NEXT_STATE <= S_IDLE;
- end if;
- else
- NEXT_STATE <= S_IDLE;
- end if;
+ fifo_read_enable <= '0';
+ fifo_read_busy <= '0';
+ fifo_data <= (others => '0');
+ fifo_read_done <= '0';
+ fifo_no_data <= '1';
+ STATE <= S_IDLE;
+ else
+ fifo_read_busy <= '0';
+ fifo_no_data <= '0';
+ fifo_read_done <= '0';
+ fifo_data <= (others => '0');
+ fifo_read_enable <= '0';
+
+ case STATE is
+ when S_IDLE =>
+ if (fifo_read_start = '1') then
+ if (fifo_empty = '0') then
+ fifo_read_enable <= '1';
+ fifo_read_busy <= '1';
+ STATE <= S_NOP1;
+ else
+ fifo_no_data <= '1';
+ fifo_read_done <= '1';
+ STATE <= S_IDLE;
+ end if;
+ else
+ STATE <= S_IDLE;
+ end if;
- when S_NOP1 =>
- fifo_read_busy_x <= '1';
- NEXT_STATE <= S_NOP2;
+ when S_NOP1 =>
+ fifo_read_busy <= '1';
+ STATE <= S_NOP2;
- when S_NOP2 =>
- fifo_read_busy_x <= '1';
- NEXT_STATE <= S_READ_WORD;
-
- when S_READ_WORD =>
- fifo_read_busy_x <= '0';
- fifo_data_x <= fifo_o;
- fifo_read_done_x <= '1';
- NEXT_STATE <= S_IDLE;
-
- end case;
+ when S_NOP2 =>
+ fifo_read_busy <= '1';
+ STATE <= S_READ_WORD;
+
+ when S_READ_WORD =>
+ fifo_read_busy <= '0';
+ fifo_data <= fifo_o;
+ fifo_read_done <= '1';
+ STATE <= S_IDLE;
+
+ end case;
+ end if;
+ end if;
end process PROC_FIFO_READ_WORD;
signal timer_ctr : unsigned(CTR_WIDTH - 1 downto 0);\r
signal timer_done_o : std_logic;\r
\r
- signal timer_ctr_x : unsigned(CTR_WIDTH - 1 downto 0);\r
- signal timer_done_o_x : std_logic;\r
-\r
type STATES is (S_IDLE,\r
S_COUNT,\r
S_DONE\r
);\r
- signal STATE, NEXT_STATE : STATES;\r
+ signal STATE : STATES;\r
\r
begin\r
-\r
- PROC_TIMER_TRANSFER: process(CLK_IN)\r
- begin\r
+ \r
+ PROC_TIMER: process(CLK_IN)\r
+ begin \r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
timer_ctr <= (others => '0');\r
timer_done_o <= '0';\r
STATE <= S_IDLE;\r
else\r
- timer_ctr <= timer_ctr_x;\r
- timer_done_o <= timer_done_o_x;\r
- STATE <= NEXT_STATE;\r
- end if;\r
- end if;\r
- end process PROC_TIMER_TRANSFER;\r
- \r
- PROC_TIMER: process(STATE,\r
- TIMER_START_IN,\r
- timer_ctr\r
- )\r
- begin \r
-\r
- timer_done_o_x <= '0';\r
-\r
- if (TIMER_START_IN > 0) then\r
- timer_ctr_x <= TIMER_START_IN;\r
- NEXT_STATE <= S_COUNT;\r
- else\r
- case STATE is\r
- when S_IDLE =>\r
- if (TIMER_START_IN = 0) then\r
- NEXT_STATE <= S_IDLE;\r
- else\r
- timer_ctr_x <= TIMER_START_IN;\r
- NEXT_STATE <= S_COUNT;\r
- end if;\r
+ timer_done_o <= '0';\r
+ \r
+ if (TIMER_START_IN > 0) then\r
+ timer_ctr <= TIMER_START_IN;\r
+ STATE <= S_COUNT;\r
+ else\r
+ case STATE is\r
+ when S_IDLE =>\r
+ if (TIMER_START_IN = 0) then\r
+ STATE <= S_IDLE;\r
+ else\r
+ timer_ctr <= TIMER_START_IN;\r
+ STATE <= S_COUNT;\r
+ end if;\r
\r
- when S_COUNT =>\r
- if (timer_ctr > 0) then\r
- timer_ctr_x <= timer_ctr - 1;\r
- NEXT_STATE <= S_COUNT;\r
- else\r
- NEXT_STATE <= S_DONE;\r
- end if;\r
+ when S_COUNT =>\r
+ if (timer_ctr > 0) then\r
+ timer_ctr <= timer_ctr - 1;\r
+ STATE <= S_COUNT;\r
+ else\r
+ STATE <= S_DONE;\r
+ end if;\r
\r
- when S_DONE =>\r
- timer_done_o_x <= '1';\r
- NEXT_STATE <= S_IDLE;\r
+ when S_DONE =>\r
+ timer_done_o <= '1';\r
+ STATE <= S_IDLE;\r
\r
- end case;\r
+ end case;\r
+ end if;\r
+ end if;\r
end if;\r
end process PROC_TIMER;\r
\r
S_SYNC_WAIT\r
);\r
\r
- signal STATE_SYNC, NEXT_STATE_SYNC: STATES_SYNC;\r
+ signal STATE_SYNC : STATES_SYNC;\r
\r
signal rs_sync_set : std_logic;\r
signal rs_sync_reset : std_logic;\r
signal nx_frame_resync_ctr : unsigned(7 downto 0);\r
signal frame_sync_wait_done : std_logic;\r
\r
- signal rs_sync_set_x : std_logic;\r
- signal rs_sync_reset_x : std_logic;\r
- signal frame_clock_ctr_inc_s_x : std_logic;\r
- signal frame_sync_wait_ctr_x : unsigned(7 downto 0);\r
- signal nx_frame_resync_ctr_x : unsigned(7 downto 0);\r
-\r
-- Slave Bus \r
signal slv_data_out_o : std_logic_vector(31 downto 0);\r
signal slv_no_more_data_o : std_logic;\r
);\r
\r
-- Frame Sync process\r
- PROC_SYNC_TO_NX_FRAME_TRANSFER: process(CLK_IN)\r
+ PROC_SYNC_TO_NX_FRAME: process(CLK_IN)\r
+ \r
+ variable fifo_tag_given : std_logic_vector(3 downto 0);\r
+\r
begin\r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
frame_sync_wait_ctr <= (others => '0');\r
STATE_SYNC <= S_SYNC_CHECK;\r
else\r
- rs_sync_set <= rs_sync_set_x;\r
- rs_sync_reset <= rs_sync_reset_x;\r
- frame_clock_ctr_inc_s <= frame_clock_ctr_inc_s_x;\r
- nx_frame_resync_ctr <= nx_frame_resync_ctr_x;\r
- frame_sync_wait_ctr <= frame_sync_wait_ctr_x;\r
- STATE_SYNC <= NEXT_STATE_SYNC;\r
- end if;\r
- end if;\r
- end process PROC_SYNC_TO_NX_FRAME_TRANSFER;\r
-\r
- PROC_SYNC_TO_NX_FRAME: process(STATE_SYNC,\r
- fifo_out(35),\r
- fifo_out(26),\r
- fifo_out(17),\r
- fifo_out(8),\r
- fifo_new_frame,\r
- register_fifo_data,\r
- frame_sync_wait_done,\r
- reset_ctr\r
- )\r
-\r
- variable fifo_tag_given : std_logic_vector(3 downto 0);\r
-\r
- begin\r
- rs_sync_set_x <= '0';\r
- rs_sync_reset_x <= '0';\r
- frame_clock_ctr_inc_s_x <= '0';\r
- nx_frame_resync_ctr_x <= nx_frame_resync_ctr;\r
- frame_sync_wait_ctr_x <= (others => '0');\r
-\r
- fifo_tag_given := fifo_out(35) & fifo_out(26) &\r
- fifo_out(17) & fifo_out(8);\r
-\r
- case STATE_SYNC is\r
- when S_SYNC_CHECK =>\r
- if (fifo_new_frame = '1') then \r
- case register_fifo_data is\r
- when x"7f7f7f06" =>\r
- rs_sync_set_x <= '1';\r
- NEXT_STATE_SYNC <= S_SYNC_CHECK;\r
-\r
- when x"067f7f7f" =>\r
- NEXT_STATE_SYNC <= S_SYNC_RESYNC;\r
- \r
- when x"7f067f7f" =>\r
- NEXT_STATE_SYNC <= S_SYNC_RESYNC;\r
- \r
- when x"7f7f067f" =>\r
- NEXT_STATE_SYNC <= S_SYNC_RESYNC;\r
- \r
- when others =>\r
- NEXT_STATE_SYNC <= S_SYNC_CHECK;\r
- \r
- end case;\r
- else\r
- NEXT_STATE_SYNC <= S_SYNC_CHECK;\r
- end if;\r
-\r
- when S_SYNC_RESYNC =>\r
- rs_sync_reset_x <= '1';\r
- frame_clock_ctr_inc_s_x <= '1';\r
- if (reset_ctr = '0') then\r
- nx_frame_resync_ctr_x <= nx_frame_resync_ctr + 1; \r
- end if;\r
-\r
- frame_sync_wait_ctr_x <= x"14";\r
- NEXT_STATE_SYNC <= S_SYNC_WAIT;\r
+ rs_sync_set <= '0';\r
+ rs_sync_reset <= '0';\r
+ frame_clock_ctr_inc_s <= '0';\r
+ nx_frame_resync_ctr <= nx_frame_resync_ctr;\r
+ frame_sync_wait_ctr <= (others => '0');\r
\r
- when S_SYNC_WAIT =>\r
- if (frame_sync_wait_done = '0') then\r
- NEXT_STATE_SYNC <= S_SYNC_WAIT;\r
- else\r
- NEXT_STATE_SYNC <= S_SYNC_CHECK;\r
- end if;\r
+ fifo_tag_given := fifo_out(35) & fifo_out(26) &\r
+ fifo_out(17) & fifo_out(8);\r
+\r
+ case STATE_SYNC is\r
+ when S_SYNC_CHECK =>\r
+ if (fifo_new_frame = '1') then \r
+ case register_fifo_data is\r
+ when x"7f7f7f06" =>\r
+ rs_sync_set <= '1';\r
+ STATE_SYNC <= S_SYNC_CHECK;\r
+\r
+ when x"067f7f7f" =>\r
+ STATE_SYNC <= S_SYNC_RESYNC;\r
+ \r
+ when x"7f067f7f" =>\r
+ STATE_SYNC <= S_SYNC_RESYNC;\r
+ \r
+ when x"7f7f067f" =>\r
+ STATE_SYNC <= S_SYNC_RESYNC;\r
+ \r
+ when others =>\r
+ STATE_SYNC <= S_SYNC_CHECK;\r
+ \r
+ end case;\r
+ else\r
+ STATE_SYNC <= S_SYNC_CHECK;\r
+ end if;\r
+\r
+ when S_SYNC_RESYNC =>\r
+ rs_sync_reset <= '1';\r
+ frame_clock_ctr_inc_s <= '1';\r
+ if (reset_ctr = '0') then\r
+ nx_frame_resync_ctr <= nx_frame_resync_ctr + 1; \r
+ end if;\r
+\r
+ frame_sync_wait_ctr <= x"14";\r
+ STATE_SYNC <= S_SYNC_WAIT;\r
+\r
+ when S_SYNC_WAIT =>\r
+ if (frame_sync_wait_done = '0') then\r
+ STATE_SYNC <= S_SYNC_WAIT;\r
+ else\r
+ STATE_SYNC <= S_SYNC_CHECK;\r
+ end if;\r
\r
- end case;\r
-\r
- if (reset_ctr = '1') then\r
- nx_frame_resync_ctr_x <= (others => '0'); \r
+ end case;\r
+ \r
+ if (reset_ctr = '1') then\r
+ nx_frame_resync_ctr <= (others => '0'); \r
+ end if;\r
+ end if;\r
end if;\r
-\r
end process PROC_SYNC_TO_NX_FRAME;\r
\r
-----------------------------------------------------------------------------\r
-- Process Trigger Handler
signal store_to_fifo : std_logic;
- signal store_to_fifo_x : std_logic;
signal data_fifo_reset_o : std_logic;
- signal data_fifo_reset_o_x : std_logic;
signal process_busy_o : std_logic;
- signal process_busy_o_x : std_logic;
signal wait_timer_init : unsigned(11 downto 0);
- signal wait_timer_init_x : unsigned(11 downto 0);
signal token_return_ctr : unsigned(3 downto 0);
- signal token_return_ctr_x : unsigned(3 downto 0);
signal ch_status_cmd_tr : CS_CMDS;
- signal ch_status_cmd_tr_x : CS_CMDS;
type STATES is (S_IDLE,
S_TRIGGER,
S_WAIT_PROCESS_END,
S_WRITE_TRAILER
);
- signal STATE, NEXT_STATE : STATES;
+ signal STATE : STATES;
signal t_data_o : std_logic_vector(31 downto 0);
- signal t_data_o_x : std_logic_vector(31 downto 0);
signal t_data_clk_o : std_logic;
- signal t_data_clk_o_x : std_logic;
-
signal busy_time_ctr : unsigned(11 downto 0);
- signal busy_time_ctr_x : unsigned(11 downto 0);
-- Timer
signal wait_timer_done : std_logic;
-- Trigger Handler
-----------------------------------------------------------------------------
- PROC_TRIGGER_HANDLER_TRANSFER: process(CLK_IN)
- begin
-
+ PROC_TRIGGER_HANDLER: process(CLK_IN)
+ begin
if( rising_edge(CLK_IN) ) then
if (RESET_IN = '1') then
store_to_fifo <= '0';
ch_status_cmd_tr <= CS_RESET;
STATE <= S_IDLE;
else
- store_to_fifo <= store_to_fifo_x;
- data_fifo_reset_o <= data_fifo_reset_o_x;
- process_busy_o <= process_busy_o_x;
- wait_timer_init <= wait_timer_init_x;
- t_data_o <= t_data_o_x;
- t_data_clk_o <= t_data_clk_o_x;
- busy_time_ctr <= busy_time_ctr_x;
- token_return_ctr <= token_return_ctr_x;
- ch_status_cmd_tr <= ch_status_cmd_tr_x;
- STATE <= NEXT_STATE;
- end if;
- end if;
- end process PROC_TRIGGER_HANDLER_TRANSFER;
+ store_to_fifo <= '0';
+ data_fifo_reset_o <= '0';
+ wait_timer_init <= (others => '0');
+ process_busy_o <= '1';
+ t_data_o <= (others => '0');
+ t_data_clk_o <= '0';
+ token_return_ctr <= token_return_ctr;
+ ch_status_cmd_tr <= CS_NONE;
+ case STATE is
+
+ when S_IDLE =>
+ if (TRIGGER_IN = '1') then
+ busy_time_ctr <= (others => '0');
+ STATE <= S_TRIGGER;
+ else
+ process_busy_o <= '0';
+ STATE <= S_IDLE;
+ end if;
+
+ when S_TRIGGER =>
+ ch_status_cmd_tr <= CS_RESET;
+ data_fifo_reset_o <= '1';
+ wait_timer_init <= x"020"; -- wait 320ns for first event
+ STATE <= S_WAIT_DATA;
+
+ when S_WAIT_DATA =>
+ if (wait_timer_done = '0') then
+ STATE <= S_WAIT_DATA;
+ else
+ STATE <= S_PROCESS_START;
+ end if;
+
+ when S_PROCESS_START =>
+ token_return_ctr <= (others => '0');
+ wait_timer_init <= readout_time_max;
+ store_to_fifo <= '1';
+ STATE <= S_WAIT_PROCESS_END;
+
+ when S_WAIT_PROCESS_END =>
+ if (wait_timer_done = '1' or
+ channel_all_done = '1' or
+ NX_NOMORE_DATA_IN = '1') then
+ STATE <= S_WRITE_TRAILER;
+ else
+ store_to_fifo <= '1';
+ STATE <= S_WAIT_PROCESS_END;
+
+ -- Check Token_Return
+ if (readout_mode = x"0" and NX_TOKEN_RETURN_IN = '1') then
+ if (token_return_ctr > 0) then
+ ch_status_cmd_tr <= CS_TOKEN_UPDATE;
+ end if;
+ token_return_ctr <= token_return_ctr + 1;
+ end if;
+ end if;
- PROC_TRIGGER_HANDLER: process(TRIGGER_IN)
- begin
- store_to_fifo_x <= '0';
- data_fifo_reset_o_x <= '0';
- wait_timer_init_x <= (others => '0');
- process_busy_o_x <= '1';
- t_data_o_x <= (others => '0');
- t_data_clk_o_x <= '0';
- token_return_ctr_x <= token_return_ctr;
- ch_status_cmd_tr_x <= CS_NONE;
- case STATE is
-
- when S_IDLE =>
- if (TRIGGER_IN = '1') then
- busy_time_ctr_x <= (others => '0');
- NEXT_STATE <= S_TRIGGER;
- else
- process_busy_o_x <= '0';
- NEXT_STATE <= S_IDLE;
- end if;
-
- when S_TRIGGER =>
- ch_status_cmd_tr_x <= CS_RESET;
- data_fifo_reset_o_x <= '1';
- wait_timer_init_x <= x"020"; -- wait 320ns for first event
- NEXT_STATE <= S_WAIT_DATA;
-
- when S_WAIT_DATA =>
- if (wait_timer_done = '0') then
- NEXT_STATE <= S_WAIT_DATA;
- else
- NEXT_STATE <= S_PROCESS_START;
- end if;
-
- when S_PROCESS_START =>
- token_return_ctr_x <= (others => '0');
- wait_timer_init_x <= readout_time_max;
- store_to_fifo_x <= '1';
- NEXT_STATE <= S_WAIT_PROCESS_END;
-
- when S_WAIT_PROCESS_END =>
- if (wait_timer_done = '1' or
- channel_all_done = '1' or
- NX_NOMORE_DATA_IN = '1') then
- NEXT_STATE <= S_WRITE_TRAILER;
- else
- store_to_fifo_x <= '1';
- NEXT_STATE <= S_WAIT_PROCESS_END;
-
- -- Check Token_Return
- if (readout_mode = x"0" and NX_TOKEN_RETURN_IN = '1') then
- if (token_return_ctr > 0) then
- ch_status_cmd_tr_x <= CS_TOKEN_UPDATE;
- end if;
- token_return_ctr_x <= token_return_ctr + 1;
- end if;
- end if;
-
- when S_WRITE_TRAILER =>
- t_data_o_x <= x"deadaffe";
- t_data_clk_o_x <= '1';
- ch_status_cmd_tr_x <= CS_RESET;
- NEXT_STATE <= S_IDLE;
-
- end case;
-
- if (STATE /= S_IDLE) then
- busy_time_ctr_x <= busy_time_ctr + 1;
- end if;
-
+ when S_WRITE_TRAILER =>
+ t_data_o <= x"deadaffe";
+ t_data_clk_o <= '1';
+ ch_status_cmd_tr <= CS_RESET;
+ STATE <= S_IDLE;
+
+ end case;
+
+ if (STATE /= S_IDLE) then
+ busy_time_ctr <= busy_time_ctr + 1;
+ end if;
+
+ end if;
+ end if;
end process PROC_TRIGGER_HANDLER;
-----------------------------------------------------------------------------
\r
signal start_cycle : std_logic;\r
signal trigger_cycle_ctr : unsigned(7 downto 0);\r
- signal trigger_cycle_ctr_x : unsigned(7 downto 0);\r
signal wait_timer_init : unsigned(15 downto 0);\r
- signal wait_timer_init_x : unsigned(15 downto 0);\r
signal wait_timer_done : std_logic;\r
signal trigger_o : std_logic;\r
- signal trigger_o_x : std_logic;\r
signal ts_reset_o : std_logic;\r
- signal ts_reset_o_x : std_logic;\r
- signal testpulse_o_x : std_logic;\r
signal testpulse_o : std_logic;\r
\r
type STATES is (S_IDLE,\r
S_SET_TESTPULSE,\r
S_WAIT_TRIGGER_END\r
);\r
- signal STATE, NEXT_STATE : STATES;\r
+ signal STATE : STATES;\r
\r
-- TRBNet Slave Bus \r
signal slv_data_out_o : std_logic_vector(31 downto 0);\r
-----------------------------------------------------------------------------\r
-- Gernerate Trigger\r
-----------------------------------------------------------------------------\r
-\r
- PROC_TRIGGER_OUT_TRANSFER: process (CLK_IN)\r
- begin \r
+ \r
+ PROC_TRIGGER_OUT: process(CLK_IN)\r
+ begin\r
if( rising_edge(CLK_IN) ) then\r
if (RESET_IN = '1') then\r
trigger_o <= '0';\r
trigger_cycle_ctr <= (others => '0');\r
STATE <= S_IDLE;\r
else\r
- trigger_o <= trigger_o_x;\r
- testpulse_o <= testpulse_o_x;\r
- ts_reset_o <= ts_reset_o_x;\r
- wait_timer_init <= wait_timer_init_x;\r
- trigger_cycle_ctr <= trigger_cycle_ctr_x;\r
- STATE <= NEXT_STATE;\r
+ trigger_o <= '0';\r
+ testpulse_o <= '0';\r
+ ts_reset_o <= '0';\r
+ wait_timer_init <= (others => '0');\r
+ trigger_cycle_ctr <= trigger_cycle_ctr;\r
+ \r
+ case STATE is\r
+ when S_IDLE =>\r
+ if (start_cycle = '1') then\r
+ trigger_cycle_ctr <= reg_trigger_num_cycles;\r
+ if (reg_reset_on = '1') then\r
+ ts_reset_o <= '1';\r
+ wait_timer_init <= reg_trigger_period;\r
+ STATE <= S_WAIT_TRIGGER_END;\r
+ else\r
+ STATE <= S_NEXT_CYCLE;\r
+ end if;\r
+ else\r
+ STATE <= S_IDLE;\r
+ end if;\r
+\r
+ when S_NEXT_CYCLE =>\r
+ if (trigger_cycle_ctr > 0) then\r
+ trigger_o <= '1';\r
+ trigger_cycle_ctr <= trigger_cycle_ctr - 1;\r
+ if (reg_testpulse_length > 0) then\r
+ wait_timer_init <= reg_testpulse_length;\r
+ STATE <= S_SET_TESTPULSE;\r
+ else\r
+ wait_timer_init <= reg_trigger_period;\r
+ STATE <= S_WAIT_TRIGGER_END;\r
+ end if;\r
+ else\r
+ STATE <= S_IDLE;\r
+ end if;\r
+\r
+ when S_SET_TESTPULSE =>\r
+ testpulse_o <= '1';\r
+ if (wait_timer_done = '0') then\r
+ STATE <= S_SET_TESTPULSE;\r
+ else\r
+ wait_timer_init <= reg_trigger_period - reg_testpulse_length;\r
+ STATE <= S_WAIT_TRIGGER_END;\r
+ end if;\r
+ \r
+ when S_WAIT_TRIGGER_END =>\r
+ if (wait_timer_done = '0') then\r
+ STATE <= S_WAIT_TRIGGER_END;\r
+ else\r
+ STATE <= S_NEXT_CYCLE;\r
+ end if;\r
+\r
+ end case;\r
end if;\r
end if;\r
- end process PROC_TRIGGER_OUT_TRANSFER;\r
-\r
- PROC_TRIGGER_OUT: process(STATE,\r
- start_cycle,\r
- reg_trigger_num_cycles,\r
- reg_trigger_period,\r
- reg_reset_on,\r
- reg_testpulse_length,\r
- wait_timer_done\r
- )\r
- begin\r
- trigger_o_x <= '0';\r
- testpulse_o_x <= '0';\r
- ts_reset_o_x <= '0';\r
- wait_timer_init_x <= (others => '0');\r
- trigger_cycle_ctr_x <= trigger_cycle_ctr;\r
- \r
- case STATE is\r
- when S_IDLE =>\r
- if (start_cycle = '1') then\r
- trigger_cycle_ctr_x <= reg_trigger_num_cycles;\r
- if (reg_reset_on = '1') then\r
- ts_reset_o_x <= '1';\r
- wait_timer_init_x <= reg_trigger_period;\r
- NEXT_STATE <= S_WAIT_TRIGGER_END;\r
- else\r
- NEXT_STATE <= S_NEXT_CYCLE;\r
- end if;\r
- else\r
- NEXT_STATE <= S_IDLE;\r
- end if;\r
-\r
- when S_NEXT_CYCLE =>\r
- if (trigger_cycle_ctr > 0) then\r
- trigger_o_x <= '1';\r
- trigger_cycle_ctr_x <= trigger_cycle_ctr - 1;\r
- if (reg_testpulse_length > 0) then\r
- wait_timer_init_x <= reg_testpulse_length;\r
- NEXT_STATE <= S_SET_TESTPULSE;\r
- else\r
- wait_timer_init_x <= reg_trigger_period;\r
- NEXT_STATE <= S_WAIT_TRIGGER_END;\r
- end if;\r
- else\r
- NEXT_STATE <= S_IDLE;\r
- end if;\r
-\r
- when S_SET_TESTPULSE =>\r
- testpulse_o_x <= '1';\r
- if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_SET_TESTPULSE;\r
- else\r
- wait_timer_init_x <= reg_trigger_period - reg_testpulse_length;\r
- NEXT_STATE <= S_WAIT_TRIGGER_END;\r
- end if;\r
- \r
- when S_WAIT_TRIGGER_END =>\r
- if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_WAIT_TRIGGER_END;\r
- else\r
- NEXT_STATE <= S_NEXT_CYCLE;\r
- end if;\r
-\r
- end case;\r
end process PROC_TRIGGER_OUT;\r
\r
-----------------------------------------------------------------------------\r
\r
signal start_cycle : std_logic;\r
signal wait_timer_init : unsigned(7 downto 0);\r
- signal wait_timer_init_x : unsigned(7 downto 0);\r
signal wait_timer_done : std_logic;\r
signal trigger_o : std_logic;\r
- signal trigger_o_x : std_logic;\r
signal timestamp_hold_o : std_logic;\r
- signal timestamp_hold_o_x : std_logic;\r
signal trigger_busy_o : std_logic;\r
- signal trigger_busy_o_x : std_logic;\r
\r
type STATES is (S_IDLE,\r
S_START,\r
S_WAIT_TRIGGER_RELEASE\r
);\r
- signal STATE, NEXT_STATE : STATES;\r
+ signal STATE : STATES;\r
\r
-- TRBNet Slave Bus \r
signal slv_data_out_o : std_logic_vector(31 downto 0);\r
-- Trigger Handler\r
-----------------------------------------------------------------------------\r
\r
- PROC_TRIGGER_HANDLER_TRANSFER: process (CLK_IN)\r
- begin \r
+ PROC_TRIGGER_HANDLER: process(CLK_IN)\r
+ begin\r
if( rising_edge(CLK_IN) ) then\r
if (RESET_IN = '1') then\r
trigger_o <= '0';\r
wait_timer_init <= (others => '0');\r
STATE <= S_IDLE;\r
else\r
- trigger_o <= trigger_o_x;\r
- timestamp_hold_o <= timestamp_hold_o_x;\r
- trigger_busy_o <= trigger_busy_o_x;\r
- wait_timer_init <= wait_timer_init_x;\r
- STATE <= NEXT_STATE;\r
+ trigger_o <= '0';\r
+ timestamp_hold_o <= '0';\r
+ trigger_busy_o <= '1';\r
+ wait_timer_init <= (others => '0');\r
+ \r
+ case STATE is\r
+ when S_IDLE =>\r
+ if (TRIGGER_IN = '1') then\r
+ trigger_o <= '1';\r
+ timestamp_hold_o <= '1';\r
+ STATE <= S_START;\r
+ else\r
+ trigger_busy_o <= '0';\r
+ STATE <= S_IDLE;\r
+ end if;\r
+\r
+ when S_START =>\r
+ STATE <= S_WAIT_TRIGGER_RELEASE;\r
+ \r
+ when S_WAIT_TRIGGER_RELEASE =>\r
+ if (TRIGGER_RELEASE_IN = '0') then\r
+ STATE <= S_WAIT_TRIGGER_RELEASE;\r
+ else\r
+ STATE <= S_IDLE;\r
+ end if;\r
+ \r
+ end case;\r
end if;\r
end if;\r
- end process PROC_TRIGGER_HANDLER_TRANSFER;\r
-\r
- PROC_TRIGGER_HANDLER: process(STATE,\r
- TRIGGER_IN,\r
- TRIGGER_RELEASE_IN\r
- )\r
- begin\r
- trigger_o_x <= '0';\r
- timestamp_hold_o_x <= '0';\r
- trigger_busy_o_x <= '1';\r
- wait_timer_init_x <= (others => '0');\r
- \r
- case STATE is\r
- when S_IDLE =>\r
- if (TRIGGER_IN = '1') then\r
- trigger_o_x <= '1';\r
- timestamp_hold_o_x <= '1';\r
- NEXT_STATE <= S_START;\r
- else\r
- trigger_busy_o_x <= '0';\r
- NEXT_STATE <= S_IDLE;\r
- end if;\r
-\r
- when S_START =>\r
- NEXT_STATE <= S_WAIT_TRIGGER_RELEASE;\r
- \r
- when S_WAIT_TRIGGER_RELEASE =>\r
- if (TRIGGER_RELEASE_IN = '0') then\r
- NEXT_STATE <= S_WAIT_TRIGGER_RELEASE;\r
- else\r
- NEXT_STATE <= S_IDLE;\r
- end if;\r
- \r
- end case;\r
end process PROC_TRIGGER_HANDLER;\r
\r
-----------------------------------------------------------------------------\r
-------------------------------------------------------------------------------
-- FPGA Timestamp
-------------------------------------------------------------------------------
-
+
nx_fpga_timestamp_1: nx_fpga_timestamp
port map (
CLK_IN => clk_256_o,
-------------------------------------------------------------------------------
-- ADC 9228 Handler
-------------------------------------------------------------------------------
--- adc_ad9222_1: adc_ad9222
+
+-- adc_ad9222_1: entity work.adc_ad9222
-- generic map (
--- CHANNELS => 4,
--- DEVICES => 2,
+-- CHANNELS => 4,
+-- DEVICES => 1,
-- RESOLUTION => 12
-- )
-- port map (
-- CLK => CLK_IN,
--- CLK_ADCREF => adc_ref_clk,
--- CLK_ADCDAT => adc_dat_clk,
--- RESTART_IN => adc_restart,
--- ADCCLK_OUT => ADC_SC_CLK32_OUT,
--- ADC_DATA(0) => ADC_NX_IN,
--- ADC_DATA(7 downto 1) => open,
--- ADC_DCO(0) => ADC_DCLK_IN,
--- ADC_DCO(1) => ADC_DCLK_IN,
--- ADC_FCO(0) => ADC_FCLK_IN,
--- ADC_FCO(1) => open,
--- DATA_OUT(11 downto 0) => adc_data_word,
--- DATA_OUT(95 downto 12) => open,
--- FCO_OUT => open,
--- -- FCO_OUT(23 downto 1) => open,
--- DATA_VALID_OUT(0) => adc_data_valid,
--- DATA_VALID_OUT(1) => open,
+-- CLK_ADCREF => nx_frame_clock_o, -- adc_ref_clk,
+-- CLK_ADCDAT => nx_frame_clock_o, -- adc_dat_clk,
+-- RESTART_IN => '0', -- adc_restart,
+-- ADCCLK_OUT => ADC_SC_CLK32_OUT, -- adc_sc_clk32_o,
+-- ADC_DATA(0) => ADC_A_IN, -- adc_data_i,
+-- ADC_DATA(1) => ADC_B_IN, -- adc_data_i,
+-- ADC_DATA(2) => ADC_NX_IN, -- adc_data_i,
+-- ADC_DATA(3) => ADC_D_IN, -- adc_data_i,
+-- ADC_DCO(0) => ADC_DCLK_IN, -- adc_dat_clk_i,
+-- ADC_FCO(0) => ADC_FCLK_IN, -- adc_fco_clk_i,
+-- DATA_OUT(0) => DEBUG_LINE_OUT(0), -- adc_data_word,
+-- FCO_OUT(0) => DEBUG_LINE_OUT(1), -- adc_fco,
+-- DATA_VALID_OUT(0) => DEBUG_LINE_OUT(2), -- adc_data_valid,
-- DEBUG => open
-- );
--- nx_frame_clock_o
-
- adc_ad9222_1: entity work.adc_ad9222
- generic map (
- CHANNELS => 4,
- DEVICES => 1,
- RESOLUTION => 12
- )
- port map (
- CLK => CLK_IN,
- CLK_ADCREF => nx_frame_clock_o, -- adc_ref_clk,
- CLK_ADCDAT => nx_frame_clock_o, -- adc_dat_clk,
- RESTART_IN => '0', -- adc_restart,
- ADCCLK_OUT => ADC_SC_CLK32_OUT, -- adc_sc_clk32_o,
- ADC_DATA(0) => ADC_A_IN, -- adc_data_i,
- ADC_DATA(1) => ADC_B_IN, -- adc_data_i,
- ADC_DATA(2) => ADC_NX_IN, -- adc_data_i,
- ADC_DATA(3) => ADC_D_IN, -- adc_data_i,
- ADC_DCO(0) => ADC_DCLK_IN, -- adc_dat_clk_i,
- ADC_FCO(0) => ADC_FCLK_IN, -- adc_fco_clk_i,
- DATA_OUT(0) => DEBUG_LINE_OUT(0), -- adc_data_word,
- FCO_OUT(0) => DEBUG_LINE_OUT(1), -- adc_fco,
- DATA_VALID_OUT(0) => DEBUG_LINE_OUT(2), -- adc_data_valid,
- DEBUG => open
- );
-
-
--- adc_ref_clk <= adc_10MHz_clock;
--- adc_dat_clk <= '0';
--- adc_restart <= RESET_IN;
--- adc_data_i(0) <= adc_nx_i;
--- adc_data_i(7 downto 1) <= (others => '0');
-
-
-------------------------------------------------------------------------------
-- nXyter Signals
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- ADC Signals
-------------------------------------------------------------------------------
- --ADC_SC_CLK32_OUT <= adc_sc_clk32_o;
- --ADC_SC_CLK32_OUT <= nx_frame_clock_o;
--- adc_fclk_i <= ADC_FCLK_IN;
--- adc_dclk_i <= ADC_DCLK_IN;
--- adc_a_i <= ADC_A_IN;
--- adc_b_i <= ADC_B_IN;
--- adc_nx_i <= ADC_NX_IN;
--- adc_d_i <= ADC_D_IN;
---
+
+
-------------------------------------------------------------------------------
-- I2C Signals
-------------------------------------------------------------------------------
I2C_SM_RESET_OUT <= not i2c_sm_reset_o;
I2C_REG_RESET_OUT <= not i2c_reg_reset_o;
-
-
-
-------------------------------------------------------------------------------
-- END
-- LV2 Data Out Handler
signal fee_trg_release_o : std_logic;
- signal fee_trg_release_o_x : std_logic;
signal fee_trg_statusbits_o : std_logic_vector(31 downto 0);
- signal fee_trg_statusbits_o_x : std_logic_vector(31 downto 0);
signal fee_data_o : std_logic_vector(31 downto 0);
- signal fee_data_o_x : std_logic_vector(31 downto 0);
signal fee_data_write_o : std_logic;
- signal fee_data_write_o_x : std_logic;
signal fee_data_finished_o : std_logic;
- signal fee_data_finished_o_x : std_logic;
-
type STATES is (S_IDLE,
S_SEND_DATA,
S_END
);
- signal STATE, NEXT_STATE : STATES;
+ signal STATE : STATES;
begin
DEBUG_LINE_OUT(8) <= FEE_DATA_ALMOST_FULL_IN;
DEBUG_LINE_OUT(15 downto 9) <= LVL1_TRG_NUMBER_IN(6 downto 0);
- PROC_DATA_HANDLER_TRANSFER: process(CLK_IN)
+ PROC_DATA_HANDLER: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
fee_data_finished_o <= '0';
STATE <= S_IDLE;
else
- fee_trg_release_o <= fee_trg_release_o_x;
- fee_data_o <= fee_data_o_x;
- fee_data_write_o <= fee_data_write_o_x;
- fee_data_finished_o <= fee_data_finished_o_x;
- STATE <= NEXT_STATE;
+ fee_trg_release_o <= '0';
+ fee_data_o <= (others => '0');
+ fee_data_write_o <= '0';
+ fee_data_finished_o <= '0';
+
+ case STATE is
+ when S_IDLE =>
+ if (LVL1_TRG_DATA_VALID_IN = '1') then
+ STATE <= S_SEND_DATA;
+ end if;
+
+ when S_SEND_DATA =>
+ fee_data_o <= x"deadbeef";
+ fee_data_write_o <= '1';
+ STATE <= S_END;
+
+ when S_END =>
+ fee_trg_release_o <= '1';
+ fee_data_finished_o <= '1';
+ STATE <= S_IDLE;
+
+ end case;
end if;
end if;
- end process PROC_DATA_HANDLER_TRANSFER;
-
- PROC_DATA_HANDLER: process(STATE)
- begin
- fee_trg_release_o_x <= '0';
- fee_data_o_x <= (others => '0');
- fee_data_write_o_x <= '0';
- fee_data_finished_o_x <= '0';
-
- case STATE is
- when S_IDLE =>
- if (LVL1_TRG_DATA_VALID_IN = '1') then
- NEXT_STATE <= S_SEND_DATA;
- end if;
-
- when S_SEND_DATA =>
- fee_data_o_x <= x"deadbeef";
- fee_data_write_o_x <= '1';
- NEXT_STATE <= S_END;
-
- when S_END =>
- fee_trg_release_o_x <= '1';
- fee_data_finished_o_x <= '1';
- NEXT_STATE <= S_IDLE;
-
- end case;
end process PROC_DATA_HANDLER;
signal i2c_sm_reset_o : std_logic;\r
signal i2c_reg_reset_o : std_logic;\r
signal nx_ts_reset_o : std_logic;\r
- signal wait_timer_init_x : unsigned(7 downto 0);\r
\r
type STATES is (S_IDLE,\r
S_I2C_SM_RESET,\r
S_NX_TS_RESET\r
);\r
\r
- signal STATE, NEXT_STATE : STATES;\r
+ signal STATE : STATES;\r
\r
-- Wait Timer\r
signal wait_timer_init : unsigned(7 downto 0);\r
-- I2C SM Reset\r
-----------------------------------------------------------------------------\r
\r
- PROC_I2C_SM_RESET_TRANSFER: process(CLK_IN)\r
- begin \r
+ PROC_I2C_SM_RESET: process(CLK_IN)\r
+ begin\r
if( rising_edge(CLK_IN) ) then\r
if( RESET_IN = '1' ) then\r
- wait_timer_init <= (others => '0');\r
- STATE <= S_IDLE;\r
+ wait_timer_init <= (others => '0');\r
+ i2c_sm_reset_o <= '0';\r
+ i2c_reg_reset_o <= '0';\r
+ nx_ts_reset_o <= '0';\r
+ STATE <= S_IDLE;\r
else\r
- wait_timer_init <= wait_timer_init_x;\r
- STATE <= NEXT_STATE;\r
+ i2c_sm_reset_o <= '0';\r
+ i2c_reg_reset_o <= '0';\r
+ nx_ts_reset_o <= '0';\r
+ wait_timer_init <= (others => '0');\r
+ \r
+ case STATE is\r
+ when S_IDLE =>\r
+ if (i2c_sm_reset_start = '1') then\r
+ STATE <= S_I2C_SM_RESET;\r
+ elsif (i2c_reg_reset_start = '1') then\r
+ STATE <= S_I2C_REG_RESET;\r
+ elsif (nx_ts_reset_start = '1') then\r
+ STATE <= S_NX_TS_RESET;\r
+ else\r
+ STATE <= S_IDLE;\r
+ end if;\r
+ \r
+ when S_I2C_SM_RESET =>\r
+ i2c_sm_reset_o <= '1';\r
+ wait_timer_init <= x"8f";\r
+ STATE <= S_I2C_SM_RESET_WAIT;\r
+\r
+ when S_I2C_SM_RESET_WAIT =>\r
+ i2c_sm_reset_o <= '1';\r
+ if (wait_timer_done = '0') then\r
+ STATE <= S_I2C_SM_RESET_WAIT;\r
+ else\r
+ STATE <= S_IDLE;\r
+ end if;\r
+\r
+ when S_I2C_REG_RESET =>\r
+ i2c_reg_reset_o <= '1';\r
+ wait_timer_init <= x"8f";\r
+ STATE <= S_I2C_REG_RESET_WAIT;\r
+\r
+ when S_I2C_REG_RESET_WAIT =>\r
+ i2c_reg_reset_o <= '1';\r
+ if (wait_timer_done = '0') then\r
+ STATE <= S_I2C_REG_RESET_WAIT;\r
+ else\r
+ STATE <= S_IDLE;\r
+ end if;\r
+\r
+ when S_NX_TS_RESET =>\r
+ nx_ts_reset_o <= '1';\r
+ STATE <= S_IDLE;\r
+\r
+ end case;\r
end if;\r
end if;\r
- end process PROC_I2C_SM_RESET_TRANSFER;\r
-\r
- PROC_I2C_SM_RESET: process(STATE,\r
- i2c_sm_reset_start,\r
- i2c_reg_reset_start,\r
- nx_ts_reset_start,\r
- wait_timer_done\r
- )\r
- begin\r
- i2c_sm_reset_o <= '0';\r
- i2c_reg_reset_o <= '0';\r
- nx_ts_reset_o <= '0';\r
- wait_timer_init_x <= (others => '0');\r
\r
- case STATE is\r
- when S_IDLE =>\r
- if (i2c_sm_reset_start = '1') then\r
- NEXT_STATE <= S_I2C_SM_RESET;\r
- elsif (i2c_reg_reset_start = '1') then\r
- NEXT_STATE <= S_I2C_REG_RESET;\r
- elsif (nx_ts_reset_start = '1') then\r
- NEXT_STATE <= S_NX_TS_RESET;\r
- else\r
- NEXT_STATE <= S_IDLE;\r
- end if;\r
- \r
- when S_I2C_SM_RESET =>\r
- i2c_sm_reset_o <= '1';\r
- wait_timer_init_x <= x"8f";\r
- NEXT_STATE <= S_I2C_SM_RESET_WAIT;\r
-\r
- when S_I2C_SM_RESET_WAIT =>\r
- i2c_sm_reset_o <= '1';\r
- if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_I2C_SM_RESET_WAIT;\r
- else\r
- NEXT_STATE <= S_IDLE;\r
- end if;\r
-\r
- when S_I2C_REG_RESET =>\r
- i2c_reg_reset_o <= '1';\r
- wait_timer_init_x <= x"8f";\r
- NEXT_STATE <= S_I2C_REG_RESET_WAIT;\r
-\r
- when S_I2C_REG_RESET_WAIT =>\r
- i2c_reg_reset_o <= '1';\r
- if (wait_timer_done = '0') then\r
- NEXT_STATE <= S_I2C_REG_RESET_WAIT;\r
- else\r
- NEXT_STATE <= S_IDLE;\r
- end if;\r
-\r
- when S_NX_TS_RESET =>\r
- nx_ts_reset_o <= '1';\r
- NEXT_STATE <= S_IDLE;\r
-\r
- end case;\r
end process PROC_I2C_SM_RESET;\r
\r
-----------------------------------------------------------------------------\r
jspc29 / trb3.git / commitdiff