start signal for fast pixel configuration. FIFO has to be filled before issuing this...

diff --git a/mupix/Mupix8/sources/SlowControl/PixelControl.vhd b/mupix/Mupix8/sources/SlowControl/PixelControl.vhd
index 76c4b5afbdec24dba26d41578312f11fed57aa8b..ea92d9a402a695d369617f5d2fa526214c786332 100644 (file)
--- a/mupix/Mupix8/sources/SlowControl/PixelControl.vhd
+++ b/mupix/Mupix8/sources/SlowControl/PixelControl.vhd
@@ -134,6 +134,7 @@ architecture Behavioral of PixelControl is
   signal mupix_ctrl_i, mupix_ctrl_ext, mupix_ctrl_sel, mupix_ctrl_reg : MupixSlowControl := c_mupix_slctrl_init;
 
   signal reset_fastcontrol_i             : std_logic                    := '0';
+  signal start_fastcontrol_i             : std_logic                    := '0';
   signal configure_state, sendbits_state : std_logic_vector(3 downto 0) := (others => '0');
 
 begin  -- Behavioral
@@ -346,7 +347,7 @@ begin  -- Behavioral
           when idle =>
             config_busy     <= '0';
             configure_state <= x"1";
-            if Empty = '0' then
+            if Empty = '0' and start_fastcontrol_i = '1' then
               config_fsm <= readfifo;
             else
               config_fsm <= idle;
@@ -396,6 +397,7 @@ begin  -- Behavioral
   --                 bit 6: reset incoming CRC sum
   --                 bit 7: readback
   --                 bit 8: reset fast slow control
+  --                 bit 9: start fast slow control
   --                 bit 31-16: number of total bits for configuration
   --x0084: reset readback process
   --x0085: set readback address/data from readback memory
@@ -415,6 +417,7 @@ begin  -- Behavioral
       reset_crc_from_mupix_ext <= '0';
       reset_readback_i         <= '0';
       reset_fastcontrol_i      <= '0';
+      start_fastcontrol_i      <= '0';
       slv_data_out             <= (others => '0');
       if SLV_WRITE_IN = '1' then
         case SLV_ADDR_IN is
@@ -432,6 +435,7 @@ begin  -- Behavioral
             reset_crc_from_mupix_ext <= SLV_DATA_IN(6);
             mupix_ctrl_ext.rb        <= SLV_DATA_IN(7);
             reset_fastcontrol_i      <= SLV_DATA_IN(8);
+            start_fastcontrol_i      <= SLV_DATA_IN(9);
             bitstosend               <= unsigned(SLV_DATA_IN(31 downto 16));
             SLV_ACK_OUT              <= '1';
           when x"0084" =>