attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true";
signal stat_med : std_logic_vector(31 downto 0);
+signal timer : unsigned(31 downto 0);
begin
stat_med(7) <= rx_ready;
stat_med(8) <= tx_ready;
stat_med(9) <= lsm_status;
-stat_med(31 downto 10) <= (others => '0');
+stat_med(15 downto 10) <= (others => '0');
+stat_med(31 downto 16) <= timer(26 downto 11);
+
+
+ PROC_TIMER : process begin
+ wait until rising_edge(SYSCLK);
+ if stat_fsm_reset_i(8) = '0' or stat_fsm_reset_i(9) = '0' then
+ timer <= (others => '0');
+ else
+ timer <= timer + 1;
+ end if;
+ end process;
end architecture;
signal stat_med : std_logic_vector(63 downto 0);
+type timer_t is array(0 to 1) of unsigned(31 downto 0);
+signal timer : timer_t;
+
begin
reset_n <= not RESET;
stat_med(i*32+7) <= rx_ready(i);
stat_med(i*32+8) <= tx_ready(i);
stat_med(i*32+9) <= lsm_status(i);
- stat_med(i*32+31 downto i*32+10) <= (others => '0');
+ stat_med(i*32+15 downto i*32+10) <= (others => '0');
+ stat_med(i*32+31 downto i*32+16) <= timer(i)(26 downto 11);
+
+
+ PROC_TIMER : process begin
+ wait until rising_edge(SYSCLK);
+ if stat_fsm_reset_i(i*32+8) = '1' or stat_fsm_reset_i(i*32+9) = '1' then
+ timer(i) <= (others => '0');
+ else
+ timer(i) <= timer(i) + 1;
+ end if;
+ end process;
+
end generate;