slv_no_more_data_o <= '0';
slv_unknown_addr_o <= '0';
slv_ack_o <= '0';
- port_select <= x"00";
+ port_select <= x"02";
else
slv_ack_o <= '1';
slv_unknown_addr_o <= '0';
--Inputs
RESET_CTR_IN : in std_logic;
LATCH_TRIGGER_IN : in std_logic; -- The raw Timing Trigger Signal
- LATCH_EXTERN_IN : in std_logic; -- The raw Latch Signal
-- Outputs
RESET_CTR_OUT : out std_logic;
LATCH_OUT : out std_logic;
- LATCH_VALID_OUT : out std_logic;
- LATCH_INVALID_OUT : out std_logic;
-- Slave bus
SLV_READ_IN : in std_logic;
signal reset_ctr_o : std_logic;
-- Latch Handler
- signal latch_select_ff : std_logic_vector(1 downto 0);
signal latch_ff : std_logic_vector(2 downto 0);
-
- signal latch_i : std_logic;
- signal latch : std_logic;
signal latch_o : std_logic;
- signal latch_valid_o : std_logic;
- signal latch_invalid_o : std_logic;
-
--- -- Latch Handler
--- type LH_STATES is (LH_IDLE,
--- LH_VALIDATE,
--- LH_WAIT
--- );
--- signal LH_STATE : LH_STATES;
---
--- signal lh_wait_timer_reset : std_logic;
--- signal lh_wait_timer_start : std_logic;
--- signal lh_wait_timer_done : std_logic;
---
--- signal latch_validate_ctr : unsigned(4 downto 0);
---
--- signal latch_o : std_logic;
--- signal latch_valid_o : std_logic;
--- signal latch_invalid_o : std_logic;
---
--- -- Rate Calculation
--- signal accepted_trigger_rate_t : unsigned(27 downto 0);
--- signal rate_timer : unsigned(27 downto 0);
-
+
-- TRBNet Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
-----------------------------------------------------------------------------
attribute syn_keep : boolean;
- attribute syn_keep of latch_select_ff : signal is true;
attribute syn_keep of latch_ff : signal is true;
attribute syn_keep of reset_ctr_ff : signal is true;
attribute syn_preserve : boolean;
- attribute syn_preserve of latch_select_ff : signal is true;
attribute syn_preserve of latch_ff : signal is true;
attribute syn_preserve of reset_ctr_ff : signal is true;
DEBUG_OUT(0) <= CLK_IN;
DEBUG_OUT(1) <= LATCH_TRIGGER_IN;
- DEBUG_OUT(2) <= latch_i;
+ DEBUG_OUT(2) <= '0';
DEBUG_OUT(3) <= latch_ff(2);
DEBUG_OUT(4) <= latch_ff(1);
DEBUG_OUT(5) <= latch_ff(0);
-- Latch Handler
-----------------------------------------------------------------------------
- latch_select_ff(1) <= latch_select_r when rising_edge(CLK_D1_IN);
- latch_select_ff(0) <= latch_select_ff(1) when rising_edge(CLK_D1_IN);
+ latch_ff(2) <= LATCH_TRIGGER_IN when rising_edge(CLK_D1_IN);
+ latch_ff(1) <= latch_ff(2) when rising_edge(CLK_D1_IN);
+ latch_ff(0) <= latch_ff(1) when rising_edge(CLK_D1_IN);
- PROC_LATCH_MULTIPLEXER: process(latch_select_ff(0),
- LATCH_TRIGGER_IN,
- LATCH_EXTERN_IN)
- begin
- if (latch_select_ff(0) = '0') then
- latch_i <= LATCH_TRIGGER_IN;
- else
- latch_i <= LATCH_EXTERN_IN;
- end if;
- end process PROC_LATCH_MULTIPLEXER;
-
- latch_ff(2) <= latch_i when rising_edge(CLK_D1_IN);
- latch_ff(1) <= latch_ff(2) when rising_edge(CLK_D1_IN);
- latch_ff(0) <= latch_ff(1) when rising_edge(CLK_D1_IN);
-
- latch <= '1' when latch_ff(1 downto 0) = "10" else '0';
-
- latch_o <= latch;
- latch_valid_o <= latch;
- latch_invalid_o <= '0';
-
--- -- Timer
--- lh_timer_static: timer_static
--- generic map (
--- CTR_WIDTH => 8,
--- CTR_END => 32 -- 128ns
--- )
--- port map (
--- CLK_IN => CLK_D1_IN,
--- RESET_IN => lh_wait_timer_reset,
--- TIMER_START_IN => lh_wait_timer_start,
--- TIMER_DONE_OUT => lh_wait_timer_done
--- );
---
--- PROC_LATCH_HANDLER: process(CLK_D1_IN)
--- begin
--- if( rising_edge(CLK_D1_IN) ) then
--- if (RESET_D1 = '1') then
--- latch_validate_ctr <= (others => '0');
--- latch_o <= '0';
--- latch_valid_o <= '0';
--- latch_invalid_o <= '0';
---
--- lh_wait_timer_start <= '0';
--- lh_wait_timer_reset <= '1';
---
--- LH_STATE <= LH_IDLE;
--- else
--- lh_wait_timer_start <= '0';
--- lh_wait_timer_reset <= '0';
---
--- latch_o <= '0';
--- latch_valid_o <= '0';
--- latch_invalid_o <= '0';
---
--- case LH_STATE is
--- when LH_IDLE =>
--- if (latch = '1') then
--- latch_validate_ctr <= (others => '0');
--- latch_o <= '1';
--- LH_STATE <= LH_VALIDATE;
--- end if;
--- LH_STATE <= LH_IDLE;
---
--- when LH_VALIDATE =>
--- if (latch_validate_ctr < x"a") then
--- if (latch = '1') then
--- latch_validate_ctr <= latch_validate_ctr + 1;
--- LH_STATE <= LH_VALIDATE;
--- else
--- latch_invalid_o <= '1';
--- lh_wait_timer_start <= '1';
--- LH_STATE <= LH_WAIT;
--- end if;
--- else
--- latch_valid_o <= '1';
--- lh_wait_timer_start <= '1';
--- LH_STATE <= LH_WAIT;
--- end if;
---
--- when LH_WAIT =>
--- if (lh_wait_timer_done = '1') then
--- LH_STATE <= LH_IDLE;
--- else
--- LH_STATE <= LH_WAIT;
--- end if;
--- end case;
---
--- end if;
--- end if;
--- end process PROC_LATCH_HANDLER;
+ latch_o <= '1' when latch_ff(1 downto 0) = "10" else '0';
---------------------------------------------------------------------------
-- TRBNet Slave Bus
slv_no_more_data_o <= '0';
slv_unknown_addr_o <= '0';
slv_ack_o <= '0';
- latch_select_r <= '0';
else
slv_unknown_addr_o <= '0';
slv_no_more_data_o <= '0';
if (SLV_WRITE_IN = '1') then
case SLV_ADDR_IN is
- when x"0000" =>
- latch_select_r <= SLV_DATA_IN(0);
- slv_ack_o <= '1';
-
+
when others =>
slv_unknown_addr_o <= '1';
elsif (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
- when x"0000" =>
- slv_data_out_o(0) <= latch_select_r;
- slv_data_out_o(31 downto 1) <= (others => '0');
-
- slv_ack_o <= '1';
when others =>
slv_unknown_addr_o <= '1';
RESET_CTR_OUT <= reset_ctr_o;
LATCH_OUT <= latch_o;
- LATCH_VALID_OUT <= latch_valid_o;
- LATCH_INVALID_OUT <= latch_invalid_o;
-- Slave Bus
SLV_DATA_OUT <= slv_data_out_o;
-- Debug Multiplexer
0x8200 : r/w Select Debug Entity
- 0: Scaler Channel 0
- 1: Trigger Handler
- 2: Latch Handler
+ 0: Trigger Handler
+ 1: Latch Handler
+ 2: Scaler Channel 0
+ 3: Scaler Channel 1
##############################################################################
# Clock Setup:
signal RESET_D1 : std_logic;
-- Bus Handler
- constant NUM_PORTS : integer := 4;
+ constant NUM_PORTS : integer := 5;
signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0);
signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0);
-- Latch Handler
signal reset_ctr : std_logic;
signal latch : std_logic;
- signal latch_valid : std_logic;
- signal latch_invalid : std_logic;
-- Trigger Validate
signal trigger_data : std_logic_vector(31 downto 0);
signal trigger_busy : std_logic;
signal fast_clear : std_logic;
signal fee_trg_release_o : std_logic;
-
+
+ -- Scaler Channels
+ signal channel_0_counter : std_logic_vector(47 downto 0);
+ signal channel_1_counter : std_logic_vector(47 downto 0);
+
-- FPGA Timestamp
signal timestamp_hold : unsigned(11 downto 0);
signal error_event_buffer : std_logic;
-- Debug Handler
- constant DEBUG_NUM_PORTS : integer := 3; -- 14
+ constant DEBUG_NUM_PORTS : integer := 4; -- 14
signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1);
----------------------------------------------------------------------
PORT_NUMBER => NUM_PORTS,
PORT_ADDRESSES => (0 => x"0200", -- Debug Multiplexer
- 1 => x"0000", -- Scaler Channel 0
+ 1 => x"0180", -- Latch Handler
2 => x"0160", -- Trigger Handler
- 3 => x"0180", -- Latch Handler
+
+ 3 => x"0000", -- Scaler Channel 0
+ 4 => x"0020", -- Scaler Channel 1
+
--2 => x"0040", -- Scaler Channel 2
--3 => x"0060", -- Scaler Channel 3
--4 => x"0080", -- Scaler Channel 4
),
PORT_ADDR_MASK => (0 => 0, -- Debug Multiplexer
- 1 => 2, -- Scaler Channel 0
+ 1 => 4, -- Latch Handler
2 => 4, -- Trigger Handler
- 3 => 4, -- Latch Handler
+
+ 3 => 2, -- Scaler Channel 0
+ 4 => 2, -- Scaler Channel 1
+
--2 => 2, -- Scaler Channel 2
--3 => 2, -- Scaler Channel 3
--4 => 2, -- Scaler Channel 4
CLK_D1_IN => CLK_D1_IN,
RESET_D1_IN => RESET_D1,
RESET_CTR_IN => CHANNELS_IN(7),
- LATCH_TRIGGER_IN => clk_pulse, -- TIMING_TRIGGER_IN, -- latch_i,
- LATCH_EXTERN_IN => TIMING_TRIGGER_IN,
+ LATCH_TRIGGER_IN => TIMING_TRIGGER_IN,
RESET_CTR_OUT => reset_ctr,
LATCH_OUT => latch,
- LATCH_VALID_OUT => latch_valid,
- LATCH_INVALID_OUT => latch_invalid,
+ SLV_READ_IN => slv_read(1),
+ SLV_WRITE_IN => slv_write(1),
+ SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),
+ SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),
+ SLV_ADDR_IN => slv_addr(1*16+15 downto 1*16),
+ SLV_ACK_OUT => slv_ack(1),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(1),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1),
+ DEBUG_OUT => debug_line(1)
+ );
+
+
+ scaler_channel_0: scaler_channel
+ port map (
+ CLK_IN => CLK_IN,
+ RESET_IN => RESET_IN,
+ CLK_D1_IN => CLK_D1_IN,
+ RESET_D1_IN => RESET_D1,
+
+ RESET_CTR_IN => reset_ctr,
+ LATCH_IN => latch,
+ PULSE_IN => CHANNELS_IN(0),
+ INHIBIT_IN => '0',
+
+ COUNTER_OUT => channel_0_counter,
+
SLV_READ_IN => slv_read(3),
SLV_WRITE_IN => slv_write(3),
SLV_DATA_OUT => slv_data_rd(3*32+31 downto 3*32),
SLV_ACK_OUT => slv_ack(3),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(3),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3),
+
DEBUG_OUT => debug_line(2)
);
-
- scaler_channel_0: scaler_channel
+ scaler_channel_1: scaler_channel
port map (
CLK_IN => CLK_IN,
RESET_IN => RESET_IN,
RESET_CTR_IN => reset_ctr,
LATCH_IN => latch,
- PULSE_IN => CHANNELS_IN(0),
+ PULSE_IN => CHANNELS_IN(1),
INHIBIT_IN => '0',
+
+ COUNTER_OUT => channel_1_counter,
- SLV_READ_IN => slv_read(1),
- SLV_WRITE_IN => slv_write(1),
- SLV_DATA_OUT => slv_data_rd(1*32+31 downto 1*32),
- SLV_DATA_IN => slv_data_wr(1*32+31 downto 1*32),
- SLV_ADDR_IN => slv_addr(1*16+15 downto 1*16),
- SLV_ACK_OUT => slv_ack(1),
- SLV_NO_MORE_DATA_OUT => slv_no_more_data(1),
- SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(1),
+ SLV_READ_IN => slv_read(4),
+ SLV_WRITE_IN => slv_write(4),
+ SLV_DATA_OUT => slv_data_rd(4*32+31 downto 4*32),
+ SLV_DATA_IN => slv_data_wr(4*32+31 downto 4*32),
+ SLV_ADDR_IN => slv_addr(4*16+15 downto 4*16),
+ SLV_ACK_OUT => slv_ack(4),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(4),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4),
- DEBUG_OUT => debug_line(0)
+ DEBUG_OUT => debug_line(3)
);
FEE_TRG_RELEASE_OUT => FEE_TRG_RELEASE_OUT,
FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT,
- FEE_DATA_0_IN => fee_data_o_0,
- FEE_DATA_WRITE_0_IN => fee_data_write_o_0,
- FEE_DATA_1_IN => fee_data_o_1,
- FEE_DATA_WRITE_1_IN => fee_data_write_o_1,
- INTERNAL_TRIGGER_IN => internal_trigger,
+ CHANNEL_DATA_0_IN => channel_0_counter,
+ CHANNEL_DATA_1_IN => channel_1_counter,
- TRIGGER_VALIDATE_BUSY_IN => trigger_validate_busy,
- TRIGGER_BUSY_0_IN => trigger_evt_busy_0,
- TRIGGER_BUSY_1_IN => trigger_evt_busy_1,
-
- VALID_TRIGGER_OUT => trigger,
- TIMESTAMP_TRIGGER_OUT => timestamp_trigger,
- TRIGGER_TIMING_OUT => trigger_timing,
- TRIGGER_STATUS_OUT => trigger_status,
- TRIGGER_CALIBRATION_OUT => trigger_calibration,
- FAST_CLEAR_OUT => fast_clear,
- TRIGGER_BUSY_OUT => trigger_busy,
-
- TESTPULSE_OUT => open,
-
SLV_READ_IN => slv_read(2),
SLV_WRITE_IN => slv_write(2),
SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(2),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2),
- DEBUG_OUT => debug_line(1)
+ DEBUG_OUT => debug_line(0)
);
LATCH_IN : in std_logic;
PULSE_IN : in std_logic;
INHIBIT_IN : in std_logic;
+
+ -- Trigger
+ COUNTER_OUT : out std_logic_vector(47 downto 0);
-- Slave bus
SLV_READ_IN : in std_logic;
-- Clock Domain Transfer in case of latch or overflow
-----------------------------------------------------------------------------
- --latch_d1 <= LATCH_IN when rising_edge(CLK_D1_IN);
- latch_d1 <= counter_low_ovfl_d1 when rising_edge(CLK_D1_IN);
+ latch_d1 <= LATCH_IN when rising_edge(CLK_D1_IN);
+ --latch_d1 <= counter_low_ovfl_d1 when rising_edge(CLK_D1_IN);
COUNTER_LOW_DOMAIN_TRANSFER_1: entity work.fifo_6to6_dc
port map (
-- Output Signals
----------------------------------------------------------------------
+ --COUNTER_OUT <= x"affedeadbeef";
+
+ COUNTER_OUT <= counter_latched;
+
SLV_DATA_OUT <= slv_data_out_o;
SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o;
SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o;
LATCH_IN : in std_logic;
PULSE_IN : in std_logic;
INHIBIT_IN : in std_logic;
+ COUNTER_OUT : out std_logic_vector(47 downto 0);
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
RESET_D1_IN : in std_logic;
RESET_CTR_IN : in std_logic;
LATCH_TRIGGER_IN : in std_logic;
- LATCH_EXTERN_IN : in std_logic;
RESET_CTR_OUT : out std_logic;
LATCH_OUT : out std_logic;
- LATCH_VALID_OUT : out std_logic;
- LATCH_INVALID_OUT : out std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
FEE_DATA_FINISHED_OUT : out std_logic;
FEE_TRG_RELEASE_OUT : out std_logic;
FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
- FEE_DATA_0_IN : in std_logic_vector(31 downto 0);
- FEE_DATA_WRITE_0_IN : in std_logic;
- FEE_DATA_1_IN : in std_logic_vector(31 downto 0);
- FEE_DATA_WRITE_1_IN : in std_logic;
- INTERNAL_TRIGGER_IN : in std_logic;
- TRIGGER_VALIDATE_BUSY_IN : in std_logic;
- TRIGGER_BUSY_0_IN : in std_logic;
- TRIGGER_BUSY_1_IN : in std_logic;
- VALID_TRIGGER_OUT : out std_logic;
- TIMESTAMP_TRIGGER_OUT : out std_logic;
- TRIGGER_TIMING_OUT : out std_logic;
- TRIGGER_STATUS_OUT : out std_logic;
- TRIGGER_CALIBRATION_OUT : out std_logic;
- FAST_CLEAR_OUT : out std_logic;
- TRIGGER_BUSY_OUT : out std_logic;
- TESTPULSE_OUT : out std_logic;
+ CHANNEL_DATA_0_IN : in std_logic_vector(47 downto 0);
+ CHANNEL_DATA_1_IN : in std_logic_vector(47 downto 0);
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_OUT : out std_logic_vector(31 downto 0);
FEE_TRG_RELEASE_OUT : out std_logic;
FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
- FEE_DATA_0_IN : in std_logic_vector(31 downto 0);
- FEE_DATA_WRITE_0_IN : in std_logic;
- FEE_DATA_1_IN : in std_logic_vector(31 downto 0);
- FEE_DATA_WRITE_1_IN : in std_logic;
-
- -- Internal FPGA Trigger
- INTERNAL_TRIGGER_IN : in std_logic;
-
- -- Trigger FeedBack
- TRIGGER_VALIDATE_BUSY_IN : in std_logic;
- TRIGGER_BUSY_0_IN : in std_logic;
- TRIGGER_BUSY_1_IN : in std_logic;
-
- -- OUT
- VALID_TRIGGER_OUT : out std_logic;
- TIMESTAMP_TRIGGER_OUT : out std_logic;
- TRIGGER_TIMING_OUT : out std_logic;
- TRIGGER_STATUS_OUT : out std_logic;
- TRIGGER_CALIBRATION_OUT : out std_logic;
- FAST_CLEAR_OUT : out std_logic;
- TRIGGER_BUSY_OUT : out std_logic;
-
- -- Pulser
- TESTPULSE_OUT : out std_logic;
+ CHANNEL_DATA_0_IN : in std_logic_vector(47 downto 0);
+ CHANNEL_DATA_1_IN : in std_logic_vector(47 downto 0);
-- Slave bus
SLV_READ_IN : in std_logic;
type STATES is (S_IDLE,
S_IGNORE_TRIGGER,
- S_STATUS_TRIGGER,
S_TIMING_TRIGGER,
- S_CALIBRATION_TRIGGER,
S_WAIT_TRG_DATA_VALID,
- S_WAIT_TIMING_TRIGGER_DONE,
+
+ S_SEND_CHANNEL_0_DATA,
+ S_SEND_CHANNEL_0_DATA_HIGH,
+
+ S_SEND_CHANNEL_1_DATA,
+ S_SEND_CHANNEL_1_DATA_HIGH,
+
+ S_SEND_FEE_DATA_DONE,
+
S_FEE_TRIGGER_RELEASE,
- S_WAIT_FEE_TRIGGER_RELEASE_ACK,
- S_INTERNAL_TRIGGER,
- S_WAIT_TRIGGER_VALIDATE_ACK,
- S_WAIT_TRIGGER_VALIDATE_DONE
+ S_WAIT_FEE_TRIGGER_RELEASE_ACK
);
signal STATE : STATES;
signal status_trigger_type : std_logic_vector(3 downto 0);
signal calibration_trigger_type : std_logic_vector(3 downto 0);
- attribute syn_keep : boolean;
-
- attribute syn_keep of trigger_busy_ff : signal is true;
- attribute syn_keep of trigger_busy_f : signal is true;
-
- attribute syn_keep of fast_clear_ff : signal is true;
- attribute syn_keep of fast_clear_f : signal is true;
-
- attribute syn_keep of internal_trigger_f : signal is true;
- attribute syn_keep of internal_trigger : signal is true;
-
- attribute syn_keep of timestamp_calib_trigger_f : signal is true;
- attribute syn_keep of timestamp_calib_trigger_o : signal is true;
-
- attribute syn_preserve : boolean;
-
- attribute syn_preserve of trigger_busy_ff : signal is true;
- attribute syn_preserve of trigger_busy_f : signal is true;
-
- attribute syn_preserve of fast_clear_ff : signal is true;
- attribute syn_preserve of fast_clear_f : signal is true;
-
- attribute syn_preserve of internal_trigger_f : signal is true;
- attribute syn_preserve of internal_trigger : signal is true;
-
- attribute syn_preserve of timestamp_calib_trigger_f : signal is true;
- attribute syn_preserve of timestamp_calib_trigger_o : signal is true;
-
begin
-- Debug Line
DEBUG_OUT(3) <= LVL1_VALID_TIMING_TRG_IN;
DEBUG_OUT(4) <= LVL1_TRG_DATA_VALID_IN;
DEBUG_OUT(5) <= fee_data_write_o;
- DEBUG_OUT(6) <= TRIGGER_VALIDATE_BUSY_IN;
- DEBUG_OUT(7) <= TRIGGER_BUSY_0_IN;
+ DEBUG_OUT(6) <= '0';
+ DEBUG_OUT(7) <= '0';
DEBUG_OUT(8) <= valid_trigger_o;
DEBUG_OUT(9) <= timing_trigger_o;
DEBUG_OUT(10) <= fee_data_finished_o;
-- Trigger Handler
-----------------------------------------------------------------------------
- PROC_TIMING_TRIGGER_HANDLER: process(CLK_D1_IN)
- constant pattern : std_logic_vector(NUM_FF - 1 downto 0)
- := (others => '1');
- begin
- if( rising_edge(CLK_D1_IN) ) then
- timing_trigger_ff_p(1) <= TIMING_TRIGGER_IN;
- if (RESET_D1_IN = '1') then
- timing_trigger_ff_p(0) <= '0';
- timing_trigger_ff(NUM_FF - 1 downto 0) <= (others => '0');
- timing_trigger_l <= '0';
- else
- timing_trigger_ff_p(0) <= timing_trigger_ff_p(1);
- timing_trigger_ff(NUM_FF - 1) <= timing_trigger_ff_p(0);
-
- for I in NUM_FF - 2 downto 0 loop
- timing_trigger_ff(I) <= timing_trigger_ff(I + 1);
- end loop;
-
- if (timing_trigger_ff = pattern) then
- timing_trigger_l <= '1';
- else
- timing_trigger_l <= '0';
- end if;
- end if;
- end if;
- end process PROC_TIMING_TRIGGER_HANDLER;
-
- level_to_pulse_1: level_to_pulse
- port map (
- CLK_IN => CLK_D1_IN,
- RESET_IN => RESET_D1_IN,
- LEVEL_IN => timing_trigger_l,
- PULSE_OUT => timing_trigger
- );
-
- -- Signal Domain Transfers to NX Clock
- trigger_busy_ff <= trigger_busy_o
- when rising_edge(CLK_D1_IN);
- trigger_busy_f <= trigger_busy_ff
- when rising_edge(CLK_D1_IN);
- trigger_busy <= trigger_busy_f
- when rising_edge(CLK_D1_IN);
-
- fast_clear_ff <= fast_clear_o
- when rising_edge(CLK_D1_IN);
- fast_clear_f <= fast_clear_ff
- when rising_edge(CLK_D1_IN);
- fast_clear <= fast_clear_f
- when rising_edge(CLK_D1_IN);
-
- PROC_TIMING_TRIGGER_HANDLER: process(CLK_D1_IN)
- begin
- if( rising_edge(CLK_D1_IN) ) then
- if (RESET_D1_IN = '1') then
- invalid_timing_trigger_n <= '1';
- ts_wait_timer_start <= '0';
- ts_wait_timer_reset <= '1';
- timestamp_trigger_o <= '0';
- TS_STATE <= TS_IDLE;
- else
- invalid_timing_trigger_n <= '0';
- ts_wait_timer_start <= '0';
- ts_wait_timer_reset <= '0';
- timestamp_trigger_o <= '0';
-
- if (fast_clear = '1') then
- ts_wait_timer_reset <= '1';
- TS_STATE <= TS_IDLE;
- else
- case TS_STATE is
- when TS_IDLE =>
- -- Wait for Timing Trigger synced to NX_MAIN_CLK_DOMAIN
- if (timing_trigger = '1') then
- if (trigger_busy = '1') then
- -- If busy is set --> Error
- TS_STATE <= TS_INVALID_TRIGGER;
- else
- timestamp_trigger_o <= '1';
- ts_wait_timer_start <= '1';
- TS_STATE <= TS_WAIT_VALID_TIMING_TRIGGER;
- end if;
- else
- TS_STATE <= TS_IDLE;
- end if;
-
- when TS_WAIT_VALID_TIMING_TRIGGER =>
- -- Wait and test if CLK_IN Trigger Handler does accepted Trigger
- if (trigger_busy = '1') then
- -- Trigger has been accepted, stop timer and wait trigger end
- ts_wait_timer_reset <= '1';
- TS_STATE <= TS_WAIT_TRIGGER_END;
- else
- if (ts_wait_timer_done = '1') then
- -- Timeout after 128ns --> Invalid Trigger Error
- TS_STATE <= TS_INVALID_TRIGGER;
- else
- TS_STATE <= TS_WAIT_VALID_TIMING_TRIGGER;
- end if;
- end if;
-
- when TS_INVALID_TRIGGER =>
- invalid_timing_trigger_n <= '1';
- TS_STATE <= TS_IDLE;
-
- when TS_WAIT_TRIGGER_END =>
- if (trigger_busy = '0') then
- TS_STATE <= TS_IDLE;
- else
- TS_STATE <= TS_WAIT_TRIGGER_END;
- end if;
-
- end case;
- end if;
- end if;
- end if;
- end process PROC_TIMING_TRIGGER_HANDLER;
-
- PROC_TIMING_TRIGGER_COUNTER: process(CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if (RESET_IN = '1') then
- invalid_timing_trigger_ctr <= (others => '0');
- else
- if (invalid_t_trigger_ctr_clear = '1') then
- invalid_timing_trigger_ctr <= (others => '0');
- elsif (invalid_timing_trigger = '1') then
- invalid_timing_trigger_ctr <= invalid_timing_trigger_ctr + 1;
- end if;
- end if;
- end if;
- end process PROC_TIMING_TRIGGER_COUNTER;
-
- -- Relax Timing
- invalid_timing_trigger_ff <= invalid_timing_trigger_n
- when rising_edge(CLK_D1_IN);
- invalid_timing_trigger_f <= invalid_timing_trigger_ff
- when rising_edge(CLK_D1_IN);
-
- pulse_dtrans_INVALID_TIMING_TRIGGER: pulse_dtrans
- generic map (
- CLK_RATIO => 4
- )
- port map (
- CLK_A_IN => CLK_D1_IN,
- RESET_A_IN => RESET_D1_IN,
- PULSE_A_IN => invalid_timing_trigger_f,
- CLK_B_IN => CLK_IN,
- RESET_B_IN => RESET_IN,
- PULSE_B_OUT => invalid_timing_trigger
- );
-
- -----------------------------------------------------------------------------
-
PROC_TRIGGER_HANDLER: process(CLK_IN)
begin
if( rising_edge(CLK_IN) ) then
timing_trigger_o <= '0';
status_trigger_o <= '0';
calibration_trigger_o <= '0';
+ fee_data_o <= (others => '0');
+ fee_data_write_o <= '0';
fee_data_finished_o <= '0';
fee_trg_release_o <= '0';
fee_trg_statusbits_o <= (others => '0');
timing_trigger_o <= '0';
status_trigger_o <= '0';
calibration_trigger_o <= '0';
+ fee_data_o <= (others => '0');
+ fee_data_write_o <= '0';
fee_data_finished_o <= '0';
fee_trg_release_o <= '0';
fee_trg_statusbits_o <= (others => '0');
when S_IDLE =>
if (LVL1_VALID_TIMING_TRG_IN = '1') then
- -- Timing Trigger IN
- if (OFFLINE_IN = '1' or
- bypass_all_trigger = '1') then
-
- -- Ignore Trigger for nxyter is or pretends to be offline
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
+ -- Check Trigger Type
+ if (LVL1_TRG_TYPE_IN = physics_trigger_type) then
+ -- Physiks Trigger
+ TRIGGER_TYPE <= T_TIMING;
+ STATE <= S_TIMING_TRIGGER;
else
- -- Check Trigger Type
- if (LVL1_TRG_TYPE_IN = physics_trigger_type) then
- -- Physiks Trigger
- if (bypass_physics_trigger = '1') then
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- else
- TRIGGER_TYPE <= T_TIMING;
- STATE <= S_TIMING_TRIGGER;
- end if;
- else
- -- Unknown Timing Trigger, ignore
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- end if;
+ -- Unknown Timing Trigger, ignore
+ TRIGGER_TYPE <= T_IGNORE;
+ STATE <= S_IGNORE_TRIGGER;
end if;
-
+
elsif (LVL1_VALID_NOTIMING_TRG_IN = '1') then
- -- No Timing Trigger IN
- if (OFFLINE_IN = '1' or
- bypass_all_trigger = '1') then
-
- -- Ignore Trigger for nxyter or pretend to be offline
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- else
- -- Check Trigger Type
- if (LVL1_TRG_TYPE_IN = calibration_trigger_type) then
- -- Calibration Trigger
- if (bypass_calibration_trigger = '1') then
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- else
- if (calib_downscale_ctr >= calibration_downscale) then
- timestamp_calib_trigger_c100 <= '1';
- calib_downscale_ctr <= x"0001";
- TRIGGER_TYPE <= T_CALIBRATION;
- STATE <= S_CALIBRATION_TRIGGER;
- else
- calib_downscale_ctr <= calib_downscale_ctr + 1;
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- end if;
- end if;
-
- elsif (LVL1_TRG_TYPE_IN = status_trigger_type) then
- -- Status Trigger
- if (bypass_status_trigger = '1') then
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- else
- -- Status Trigger
- status_trigger_o <= '1';
- TRIGGER_TYPE <= T_STATUS;
- STATE <= S_STATUS_TRIGGER;
- end if;
-
- else
- -- Some other Trigger, ignore it
- TRIGGER_TYPE <= T_IGNORE;
- STATE <= S_IGNORE_TRIGGER;
- end if;
-
- end if;
+ -- Ignore NOTIMING Triggers
+ TRIGGER_TYPE <= T_IGNORE;
+ STATE <= S_IGNORE_TRIGGER;
else
-- No Trigger IN, Nothing to do, Sleep Well
timing_trigger_o <= '1';
STATE <= S_WAIT_TRG_DATA_VALID;
- when S_CALIBRATION_TRIGGER =>
- calibration_trigger_o <= '1';
- valid_trigger_o <= '1';
- timing_trigger_o <= '1';
- STATE <= S_WAIT_TRG_DATA_VALID;
-
- when S_WAIT_TRG_DATA_VALID | S_STATUS_TRIGGER | S_IGNORE_TRIGGER =>
+ when S_WAIT_TRG_DATA_VALID | S_IGNORE_TRIGGER =>
if (LVL1_TRG_DATA_VALID_IN = '0') then
STATE <= S_WAIT_TRG_DATA_VALID;
else
- STATE <= S_WAIT_TIMING_TRIGGER_DONE;
+ if (TRIGGER_TYPE = T_IGNORE) then
+ STATE <= S_SEND_FEE_DATA_DONE;
+ else
+ STATE <= S_SEND_CHANNEL_0_DATA;
+ end if;
end if;
+
+ -- Send Channel Data
+ when S_SEND_CHANNEL_0_DATA =>
+ fee_data_o(31 downto 28) <= x"0";
+ fee_data_o(27 downto 16) <= x"aaa";
+ fee_data_o(15 downto 0) <= CHANNEL_DATA_0_IN(47 downto 32);
+ fee_data_write_o <= '1';
+ STATE <= S_SEND_CHANNEL_0_DATA_HIGH;
+
+ when S_SEND_CHANNEL_0_DATA_HIGH =>
+ fee_data_o <= CHANNEL_DATA_0_IN(31 downto 0);
+ fee_data_write_o <= '1';
+ STATE <= S_SEND_CHANNEL_1_DATA;
+
+
+ when S_SEND_CHANNEL_1_DATA =>
+ fee_data_o(31 downto 28) <= x"1";
+ fee_data_o(27 downto 16) <= x"bbb";
+ fee_data_o(15 downto 0) <= CHANNEL_DATA_1_IN(47 downto 32);
+ fee_data_write_o <= '1';
+ STATE <= S_SEND_CHANNEL_1_DATA_HIGH;
+
+ when S_SEND_CHANNEL_1_DATA_HIGH =>
+ fee_data_o <= CHANNEL_DATA_1_IN(31 downto 0);
+ fee_data_write_o <= '1';
+ STATE <= S_SEND_FEE_DATA_DONE;
- when S_WAIT_TIMING_TRIGGER_DONE =>
- if (((TRIGGER_TYPE = T_TIMING or
- TRIGGER_TYPE = T_CALIBRATION)
- and TRIGGER_BUSY_0_IN = '1')
- or
- (TRIGGER_TYPE = T_STATUS and
- TRIGGER_BUSY_1_IN = '1')
- ) then
- STATE <= S_WAIT_TIMING_TRIGGER_DONE;
- else
- fee_data_finished_o <= '1';
- STATE <= S_FEE_TRIGGER_RELEASE;
- end if;
+
+ when S_SEND_FEE_DATA_DONE =>
+ fee_data_finished_o <= '1';
+ STATE <= S_FEE_TRIGGER_RELEASE;
+ -- Hier noch warten auf CTS
when S_FEE_TRIGGER_RELEASE =>
fee_trg_release_o <= '1';
STATE <= S_WAIT_FEE_TRIGGER_RELEASE_ACK;
else
STATE <= S_IDLE;
end if;
-
- -- Internal Trigger Handler
- when S_INTERNAL_TRIGGER =>
- valid_trigger_o <= '1';
- STATE <= S_WAIT_TRIGGER_VALIDATE_ACK;
- when S_WAIT_TRIGGER_VALIDATE_ACK =>
- if (TRIGGER_VALIDATE_BUSY_IN = '0') then
- STATE <= S_WAIT_TRIGGER_VALIDATE_ACK;
- else
- STATE <= S_WAIT_TRIGGER_VALIDATE_DONE;
- end if;
-
- when S_WAIT_TRIGGER_VALIDATE_DONE =>
- if (TRIGGER_VALIDATE_BUSY_IN = '1') then
- STATE <= S_WAIT_TRIGGER_VALIDATE_DONE;
- else
- STATE <= S_IDLE;
- end if;
-
- end case;
+ end case;
end if;
end if;
end if;
end process PROC_TRIGGER_HANDLER;
- PROC_EVENT_DATA_MULTIPLEXER: process(TRIGGER_TYPE)
- begin
- case TRIGGER_TYPE is
- when T_UNDEF | T_IGNORE =>
- fee_data_o <= (others => '0');
- fee_data_write_o <= '0';
-
- when T_TIMING | T_CALIBRATION =>
- fee_data_o <= FEE_DATA_0_IN;
- fee_data_write_o <= FEE_DATA_WRITE_0_IN;
-
- when T_STATUS =>
- fee_data_o <= FEE_DATA_1_IN;
- fee_data_write_o <= FEE_DATA_WRITE_1_IN;
-
- end case;
- end process PROC_EVENT_DATA_MULTIPLEXER;
-
- internal_trigger_f <= INTERNAL_TRIGGER_IN or
- calibration_trigger_o when rising_edge(CLK_D1_IN);
- internal_trigger <= internal_trigger_f when rising_edge(CLK_D1_IN);
-
- PROC_CAL_RATES: process (CLK_IN)
- begin
- if( rising_edge(CLK_IN) ) then
- if (RESET_IN = '1') then
- accepted_trigger_rate_t <= (others => '0');
- accepted_trigger_rate <= (others => '0');
- rate_timer <= (others => '0');
- else
- if (rate_timer < x"5f5e100") then
- if (timing_trigger_o = '1') then
- accepted_trigger_rate_t <= accepted_trigger_rate_t + 1;
- end if;
-
- rate_timer <= rate_timer + 1;
- else
- rate_timer <= (others => '0');
- accepted_trigger_rate <= accepted_trigger_rate_t;
-
- accepted_trigger_rate_t <= (others => '0');
- end if;
- end if;
- end if;
- end process PROC_CAL_RATES;
-
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
-----------------------------------------------------------------------------
-- Output Signals
-----------------------------------------------------------------------------
- timestamp_calib_trigger_f <= timestamp_calib_trigger_c100
- when rising_edge(CLK_D1_IN);
-
- timestamp_calib_trigger_o <= timestamp_calib_trigger_f
- when rising_edge(CLK_D1_IN);
-
-- Trigger Output
- VALID_TRIGGER_OUT <= valid_trigger_o;
- TIMESTAMP_TRIGGER_OUT <= timestamp_trigger_o or timestamp_calib_trigger_o;
- TRIGGER_TIMING_OUT <= timing_trigger_o;
- TRIGGER_STATUS_OUT <= status_trigger_o;
- TRIGGER_CALIBRATION_OUT <= calibration_trigger_o;
- FAST_CLEAR_OUT <= fast_clear_o;
- TRIGGER_BUSY_OUT <= trigger_busy_o;
-
FEE_DATA_OUT <= fee_data_o;
FEE_DATA_WRITE_OUT <= fee_data_write_o;
FEE_DATA_FINISHED_OUT <= fee_data_finished_o;
#Trigger from fan-out
LOCATE COMP "TRIGGER_LEFT" SITE "V3";
-#LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
+LOCATE COMP "TRIGGER_RIGHT" SITE "N24";
IOBUF PORT "TRIGGER_LEFT" IO_TYPE=LVDS25 ;
-#IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
+IOBUF PORT "TRIGGER_RIGHT" IO_TYPE=LVDS25 ;
LATCH_IN => CHANNELS_ECL_IN(0),
CHANNELS_IN(0) => quad_channel_0,
- CHANNELS_IN(7 downto 1) => CHANNELS_NIM_IN(7 downto 1),
+ CHANNELS_IN(1) => CHANNELS_NIM_IN(0),
+ CHANNELS_IN(7 downto 2) => CHANNELS_NIM_IN(7 downto 2),
TIMING_TRIGGER_IN => TRIGGER_RIGHT,
LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
MULTICYCLE TO CELL "scaler_0/scaler_channel_0/pulse_ff*[2]*" 30 ns;
MULTICYCLE TO CELL "scaler_0/latch_handler_1/reset_ctr_ff*[2]*" 30 ns;
-MULTICYCLE FROM CELL "scaler_0/latch_handler_1/latch_select_r*" 100 ns;
MULTICYCLE TO CELL "scaler_0/latch_handler_1/latch_ff*[2]*" 30 ns;
MULTICYCLE TO GROUP "TEST_LINE_group" 500.000000 ns ;
jspc29 / trb3.git / commitdiff