use work.trb3_components.all;\r
use work.med_sync_define.all;\r
\r
+\r
entity trb5sc_mimosis is\r
port(\r
CLK_200 : in std_logic;\r
H3(3) <= clk_320;\r
\r
-- For IPHC Proxy\r
- -- RJ(0) <= clk_40;\r
+ RJ(0) <= clk_40;\r
-- For IKF Proxy\r
- H1(4) <= clk_40;\r
+ -- H1(4) <= clk_40;\r
\r
---------------------------------------------------------------------------\r
-- TrbNet Uplink\r
LED_ADDON_SFP_ORANGE(1) <= '0';\r
\r
\r
-\r
-----------------------------------------------------------------------------\r
---- GbE\r
-----------------------------------------------------------------------------\r
--end process;\r
\r
\r
----------------------------------------------------------------------------\r
--- Output stage\r
----------------------------------------------------------------------------\r
- -- THE_OUT : entity work.testout\r
- -- port map(\r
- -- clkout => open,\r
- -- refclk => clk_160,\r
- -- reset => reset_i,\r
- -- data => out_data,\r
- -- data_cflag => open,\r
- -- data_direction => (others => '0'),\r
- -- data_loadn => (others => '1'),\r
- -- data_move => (others => '0'),\r
- -- dout => out_i\r
- -- );\r
-\r
- -- PROC_OUT : process\r
- -- variable cnt : integer range 0 to 7;\r
- -- begin\r
- -- wait until rising_edge(clk_160);\r
- -- cnt := cnt + 1;\r
- -- case cnt is\r
- -- when 0 => out_data <= x"ffff";\r
- -- when 1 => out_data <= x"ffff";\r
- -- when 2 => out_data <= x"ffff";\r
- -- when 3 => out_data <= x"0000";\r
- -- when 4 => out_data <= x"5555";\r
- -- when 5 => out_data <= x"5555";\r
- -- when 6 => out_data <= x"5555";\r
- -- when 7 => out_data <= x"5555";\r
- -- end case;\r
- -- end process;\r
-\r
- -- H3(3 downto 0) <= out_i(3 downto 0);\r
- -- H4(3 downto 0) <= out_i(7 downto 4);\r
-\r
-\r
---------------------------------------------------------------------------\r
-- Input stage\r
---------------------------------------------------------------------------\r
LOCATE COMP "H7[3]" SITE "W30" ; #was "FE_DIFF[7]"
#LOCATE COMP "H5[4]" SITE "T32" ; #was "FE_DIFF[8]"
+# H5
# LOCATE COMP "MIMOSIS_SCL" SITE "U32" ; #was "FE_DIFF[8]"
# LOCATE COMP "MIMOSIS_SDA" SITE "T32" ; #was "FE_DIFF[8]"
+# H3
LOCATE COMP "MIMOSIS_SCL" SITE "C2" ; #was "FE_DIFF[8]"
LOCATE COMP "MIMOSIS_SDA" SITE "B1" ; #was "FE_DIFF[8]"
IOBUF PORT "MIMOSIS_SCL" IO_TYPE=LVCMOS25 ;
# LOCATE COMP "FE_DIFF[31]" SITE "K27" ; #was "FE_DIFF[31]"
LOCATE COMP "H3[3]" SITE "D4" ; #was "FE_DIFF[32]"
LOCATE COMP "H3[4]" SITE "B1" ; #was "FE_DIFF[34]"
-# LOCATE COMP "H3[2]" SITE "F3" ; #was "FE_DIFF[36]"
-LOCATE COMP "H3_2" SITE "F3" ; #was "FE_DIFF[36]"
+LOCATE COMP "H3[2]" SITE "F3" ; #was "FE_DIFF[36]"
+# LOCATE COMP "H3_2" SITE "F3" ; #was "FE_DIFF[36]"
LOCATE COMP "H3[1]" SITE "F2" ; #was "FE_DIFF[38]"
LOCATE COMP "H3[0]" SITE "H2" ; #was "FE_DIFF[40]"
# LOCATE COMP "FE_DIFF[41]" SITE "J3" ; #was "FE_DIFF[41]"
IOBUF GROUP "H2_group" IO_TYPE=LVDS DIFFRESISTOR=100 ;
DEFINE PORT GROUP "H3_group" "H3*" ;
IOBUF GROUP "H3_group" IO_TYPE=LVDS DIFFRESISTOR=100 ;
+
+# IOBUF PORT "H3_0" IO_TYPE=LVDS DIFFRESISTOR=100;
+# IOBUF PORT "H3_2" IO_TYPE=LVDS DIFFRESISTOR=100;
+# IOBUF PORT "H3_3" IO_TYPE=LVDS DIFFRESISTOR=100;
+
DEFINE PORT GROUP "H4_group" "H4*" ;
IOBUF GROUP "H4_group" IO_TYPE=LVDS DIFFRESISTOR=100 ;
DEFINE PORT GROUP "H5_group" "H5*" ;