constant INIT_ADDRESS : std_logic_vector := x"F30a";
constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"4b";
---ADC sampling frequency: 40 or 64 MHz supported
- constant ADC_SAMPLING_RATE : integer := 64;
+--ADC sampling frequency: 40 or 80 MHz supported
+ constant ADC_SAMPLING_RATE : integer := 80;
--These are currently used for the included features table only
constant ADC_PROCESSING_TYPE : integer := 0;
constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
-end package body;
\ No newline at end of file
+end package body;
type q_t is array(0 to NUM_DEVICES-1) of std_logic_vector(19 downto 0);
signal q,qq,qqq : q_t;
-signal clk_adcfast_i : std_logic; --200MHz/320MHz
-signal clk_data : std_logic; --100MHz/160MHz
+signal clk_adcfast_i : std_logic; --200MHz/400MHz
+signal clk_data : std_logic; --100MHz/200MHz
signal restart_i : std_logic;
type cnt_t is array(0 to NUM_DEVICES-1) of unsigned(27 downto 0);
);
end generate;
- gen_64MHz : if ADC_SAMPLING_RATE = 64 generate
- THE_ADC_REF : entity work.pll_in200_out64
+ gen_80MHz : if ADC_SAMPLING_RATE = 80 generate
+ THE_ADC_REF : entity work.pll_in200_out80
port map(
CLK => CLK_ADCRAW,
CLKOP => ADCCLK_OUT,
LOCK => open
);
- THE_ADC_PLL_0 : entity work.pll_adc10bit_64
+ THE_ADC_PLL_0 : entity work.pll_adc10bit_80
port map(
CLK => CLK_ADCRAW,
CLKOP => clk_adcfast_i,
add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
add_file -vhdl -lib "work" "../base/cores/pll_in200_out40.vhd"
-add_file -vhdl -lib "work" "../base/cores/pll_in200_out64.vhd"
+add_file -vhdl -lib "work" "../base/cores/pll_in200_out80.vhd"
add_file -vhdl -lib "work" "../base/cores/pll_adc10bit.vhd"
-add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_64.vhd"
+add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_80.vhd"
add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd"
add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"
add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200_50.vhd"
define_clock {CLK_PCLK_RIGHT} -name {CLK_PCLK_RIGHT} -freq 200 -clockgroup default_clkgroup_0
define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -freq 100 -clockgroup default_clkgroup_1
define_clock {TRIGGER_LEFT} -name {TRIGGER_LEFT} -freq 10 -clockgroup default_clkgroup_2
-define_clock {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -freq 160 -clockgroup default_clkgroup_3
-define_clock {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -freq 160 -clockgroup default_clkgroup_4
+define_clock {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -freq 200 -clockgroup default_clkgroup_3
+define_clock {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -freq 200 -clockgroup default_clkgroup_4
define_clock {n:THE_MAIN_PLL.CLKOP} -name {n:THE_MAIN_PLL.CLKOP} -freq 100 -clockgroup default_clkgroup_5
define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -freq 100 -clockgroup default_clkgroup_6
define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -freq 100 -clockgroup default_clkgroup_7
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_adc10bit_80" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 02 12 20:59:18.317" version="5.3" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="pll_adc10bit_80.lpc" type="lpc" modified="2015 02 12 20:59:15.000"/>
+ <File name="pll_adc10bit_80.vhd" type="top_level_vhdl" modified="2015 02 12 20:59:15.000"/>
+ <File name="pll_adc10bit_80_tmpl.vhd" type="template_vhdl" modified="2015 02 12 20:59:15.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8LFN672C
+SpeedGrade=8L
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.3
+ModuleName=pll_adc10bit_80
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=02/12/2015
+Time=20:59:15
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=1
+ClkOPBp=0
+Post=2
+U_OFrq=400
+OP_Tol=0.0
+OFrq=400.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=Internal
+Mult=2
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=2.970786
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module Version: 5.3
+--/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n pll_adc10bit_80 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 400 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -noclkok -norst -noclkok2 -bw -e
+
+-- Thu Feb 12 20:59:15 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_adc10bit_80 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_adc10bit_80 : entity is true;
+end pll_adc10bit_80;
+
+architecture Structure of pll_adc10bit_80 is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal CLKFB_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "400.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2, CLKI_DIV=> 1,
+ FIN=> "200.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>CLKFB_t);
+
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_adc10bit_80 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_in200_out80" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 02 12 21:02:06.981" version="5.3" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="pll_in200_out80.lpc" type="lpc" modified="2015 02 12 21:01:08.000"/>
+ <File name="pll_in200_out80.vhd" type="top_level_vhdl" modified="2015 02 12 21:01:09.000"/>
+ <File name="pll_in200_out80_tmpl.vhd" type="template_vhdl" modified="2015 02 12 21:01:09.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LFE3-150EA
+PartName=LFE3-150EA-8LFN672C
+SpeedGrade=8L
+Package=FPBGA672
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.3
+ModuleName=pll_in200_out80
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=02/12/2015
+Time=21:01:08
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=5
+ClkOPBp=0
+Post=8
+U_OFrq=80
+OP_Tol=0.0
+OFrq=80.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=CLKOP
+Mult=2
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=2.191564
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
+-- Module Version: 5.3
+--/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out80 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 80 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e
+
+-- Thu Feb 12 21:01:09 2015
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_in200_out80 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in200_out80 : entity is true;
+end pll_in200_out80;
+
+architecture Structure of pll_in200_out80 is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "80.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 2, CLKI_DIV=> 5,
+ FIN=> "200.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>open);
+
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_in200_out80 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
jspc29 / trb3.git / commitdiff