]> jspc29.x-matter.uni-frankfurt.de Git - dirich.git/commitdiff
switch threshold firmware between DiRICh versions by config and selection of pinout...
authorAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Tue, 1 Jun 2021 08:46:03 +0000 (10:46 +0200)
committerAdrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Tue, 1 Jun 2021 08:46:03 +0000 (10:46 +0200)
thresholds/config.vhd [new file with mode: 0644]
thresholds/config_compile_giessen.pl [new file with mode: 0644]
thresholds/thresholds.prj
thresholds/thresholds.vhd

diff --git a/thresholds/config.vhd b/thresholds/config.vhd
new file mode 100644 (file)
index 0000000..2bceacc
--- /dev/null
@@ -0,0 +1,10 @@
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+package config is
+
+
+  constant DIRICH_VERSION   : integer := 4; --DiRICH_vX.
+  -- in case of DIRICH_VERSION > 3, change pinout accordingly to dirich4
+end;
diff --git a/thresholds/config_compile_giessen.pl b/thresholds/config_compile_giessen.pl
new file mode 100644 (file)
index 0000000..12ba21c
--- /dev/null
@@ -0,0 +1,27 @@
+Familyname  => 'MachXO3LF',
+Devicename  => 'LCMXO3LF-4300E',
+Package     => 'WLCSP81',
+Speedgrade  => '5',
+
+TOPNAME                      => "thresholds",
+lm_license_file_for_synplify => "7788\@fb07pc-u102325",
+lm_license_file_for_par      => "7788\@fb07pc-u102325",
+lattice_path                 => '/usr/local/diamond/3.10_x64/',
+synplify_path                => '/usr/local/diamond/3.10_x64/synpbase',
+synplify_command             => "synpwrap -fg -options",
+#synplify_command             => "ssh  adrian\@jspc37.x-matter.uni-frankfurt.de \"cd /local/adrian/git/dirich/combiner_cts/; LM_LICENSE_FILE=27020\@jspc29 /d/jspc29/lattice/synplify/O-2018.09-SP1/bin/synplify_premier -batch combiner.prj\"",
+
+nodelist_file                => 'nodelist_frankfurt.txt',
+
+
+#Include only necessary lpf files
+pinout_file                  => 'thresholds_dirich4', #name of pin-out file, if not equal TOPNAME
+#change DIRICH VERSION in config.vhd accordingly
+include_TDC                  => 0,
+include_GBE                  => 0,
+
+#Report settings
+firefox_open                 => 0,
+twr_number_of_errors         => 20,
+no_ltxt2ptxt                 => 1,  #if there is no serdes being used
+make_jed                     => 1,
index 983193460972f50767e0dc00f21e1777f7d6ec50..32ec80757ccbea3dfea20603212357474f8646c7 100644 (file)
@@ -6,6 +6,7 @@
 
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "./config.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/sedcheck.vhd"
 add_file -vhdl -lib work "../../vhdlbasics/io/pwm.vhd"
index 8f882339a647f2673dc523606dd72c94ff10bf07..7d0d033c9f3bccd34cb9a688eb79b82bb4cb7f68 100644 (file)
@@ -8,6 +8,7 @@ use machxo3lf.all;
 library work;\r
 use work.trb_net_std.all;\r
 use work.version.all;\r
+use work.config.all;\r
 \r
 entity thresholds is\r
   port(\r
@@ -121,36 +122,74 @@ THE_SPI : entity work.spi_slave
     DEBUG     => open\r
   );\r
 \r
-THE_FLASH_CONTROLLER : entity generic_flash_ctrl\r
-  generic map (\r
-    CFG_FLASH_DISABLE_COUNTER_WIDTH => 30, --31sec timeout\r
-    USE_I2C_PROG => c_YES              -- DiRICH1,2,3: c_YES ; DiRICH4: c_NO\r
-  )\r
-  port map(\r
+  \r
+-- select Flash controller according to the Dirich version  \r
+THE_DIRICH_GEN : if DIRICH_VERSION < 4 generate \r
+  THE_FLASH_CONTROLLER : entity generic_flash_ctrl\r
+    generic map (\r
+      CFG_FLASH_DISABLE_COUNTER_WIDTH => 30, --31sec timeout\r
+      USE_I2C_PROG => c_NO             -- DiRICH1,2,3: c_NO ; DiRICH4: c_YES\r
+    )\r
+    port map(\r
+  \r
+      CLK_f => clk_33,\r
+      CLK_l => clk_33,\r
+      RESET => '0',\r
+      \r
+      SPI_DATA_IN   => spi_data_out,\r
+      SPI_DATA_OUT  => spi_data_in,\r
+      SPI_ADDR_IN   => spi_addr_out,\r
+      SPI_WRITE_IN  => spi_write_out,\r
+      SPI_READ_IN   => spi_read_out,\r
+      SPI_READY_OUT => spi_ready_in,\r
+      SPI_BUSY_IN   => spi_busy_out,\r
+      \r
+      LOC_DATA_OUT  => spi_rx_data,\r
+      LOC_DATA_IN   => spi_tx_data,\r
+      LOC_ADDR_OUT  => spi_addr,\r
+      LOC_WRITE_OUT => bus_write,\r
+      LOC_READ_OUT  => bus_read,\r
+      LOC_READY_IN  => bus_ready,\r
+      LOC_BUSY_OUT  => bus_busy,\r
+      \r
+      SCL           => SCL,\r
+      SDA           => SDA\r
+    );\r
+end generate;\r
+\r
+THE_DIRICH_GEN : if DIRICH_VERSION >= 4 generate \r
+  THE_FLASH_CONTROLLER : entity generic_flash_ctrl\r
+    generic map (\r
+      CFG_FLASH_DISABLE_COUNTER_WIDTH => 30, --31sec timeout\r
+      USE_I2C_PROG => c_YES            -- DiRICH1,2,3: c_NO ; DiRICH4: c_YES\r
+    )\r
+    port map(\r
+  \r
+      CLK_f => clk_33,\r
+      CLK_l => clk_33,\r
+      RESET => '0',\r
+      \r
+      SPI_DATA_IN   => spi_data_out,\r
+      SPI_DATA_OUT  => spi_data_in,\r
+      SPI_ADDR_IN   => spi_addr_out,\r
+      SPI_WRITE_IN  => spi_write_out,\r
+      SPI_READ_IN   => spi_read_out,\r
+      SPI_READY_OUT => spi_ready_in,\r
+      SPI_BUSY_IN   => spi_busy_out,\r
+      \r
+      LOC_DATA_OUT  => spi_rx_data,\r
+      LOC_DATA_IN   => spi_tx_data,\r
+      LOC_ADDR_OUT  => spi_addr,\r
+      LOC_WRITE_OUT => bus_write,\r
+      LOC_READ_OUT  => bus_read,\r
+      LOC_READY_IN  => bus_ready,\r
+      LOC_BUSY_OUT  => bus_busy,\r
+      \r
+      SCL           => SCL,\r
+      SDA           => SDA\r
+    );\r
+end generate;\r
 \r
-    CLK_f => clk_33,\r
-    CLK_l => clk_33,\r
-    RESET => '0',\r
-    \r
-    SPI_DATA_IN   => spi_data_out,\r
-    SPI_DATA_OUT  => spi_data_in,\r
-    SPI_ADDR_IN   => spi_addr_out,\r
-    SPI_WRITE_IN  => spi_write_out,\r
-    SPI_READ_IN   => spi_read_out,\r
-    SPI_READY_OUT => spi_ready_in,\r
-    SPI_BUSY_IN   => spi_busy_out,\r
-    \r
-    LOC_DATA_OUT  => spi_rx_data,\r
-    LOC_DATA_IN   => spi_tx_data,\r
-    LOC_ADDR_OUT  => spi_addr,\r
-    LOC_WRITE_OUT => bus_write,\r
-    LOC_READ_OUT  => bus_read,\r
-    LOC_READY_IN  => bus_ready,\r
-    LOC_BUSY_OUT  => bus_busy,\r
-    \r
-    SCL           => SCL,\r
-    SDA           => SDA\r
-  );  \r
 \r
 PROC_REGS : process begin\r
   wait until rising_edge(clk_33);\r
@@ -167,6 +206,7 @@ PROC_REGS : process begin
           when x"31" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));\r
           when x"ee" => spi_tx_data <= sed_debug(15 downto 0);\r
           when x"ef" => spi_tx_data <= sed_debug(31 downto 16);\r
+          when x"fe" => spi_tx_data <= std_logic_vector(to_unsigned(DIRICH_VERSION,16)); --DiRICH version (different pinout due to I2C)\r
           when x"ff" => spi_tx_data <= x"0100"; --version number\r
           when others => spi_tx_data <= x"0000";\r
         end case; \r