entity cbmnet_phy_ecp3 is\r
generic(\r
IS_SYNC_SLAVE : integer := c_YES; --select slave mode\r
- DETERMINISTIC_LATENCY : integer := c_NO; -- if selected proper alignment of barrel shifter and word alignment is enforced (link may come up slower)\r
+ DETERMINISTIC_LATENCY : integer := c_YES; -- if selected proper alignment of barrel shifter and word alignment is enforced (link may come up slower)\r
IS_SIMULATED : integer := c_NO;\r
INCL_DEBUG_AIDS : integer := c_YES\r
);\r
\r
-- Clocks and global resets \r
signal clk_125_local : std_logic; -- local 125 MHz reference clock driven by clock generators\r
- signal clk_125_i : std_logic; -- in FEE mode, driven by recovered clock, in Master mode, driven by local clock\r
signal rclk_250_i : std_logic; -- recovered word clock\r
signal rclk_125_i : std_logic; -- rclk_250_i divided by two. aligned s.t. the rising edge corresponds to the lower received word\r
signal clk_tx_full_i : std_logic; -- 250 MHz clock generated by the serdes's TX-PLL\r
\r
signal rst_i : std_logic; -- High-active reset driven by external logic\r
signal rst_n_i : std_logic; -- Low-active version of rst_i\r
-\r
- signal clk_serdes_rx_ref : std_logic;\r
- signal clk_serdes_tx_ref : std_logic;\r
\r
-- SERDES/PCS \r
-- status\r
signal lsm_status_i : std_logic;\r
\r
signal rx_dec_error_i: std_logic;\r
+ signal rx_dec_errors2_i : std_logic_vector(1 downto 0);\r
signal rx_dec_error_125_i, rx_dec_error_125_buf_i: std_logic_vector(1 downto 0);\r
\r
signal rx_error_delay : std_logic_vector(3 downto 0); -- shift register to detect a "stable error condition"\r
\r
signal rx_data_sp_i0, rx_data_sp_i1, rx_data_sp_i2, rx_data_sp_i3 : std_logic_vector(17 downto 0);\r
\r
+ --signal see_dlm_lb_i, see_dlm_lb_buf_i : std_logic_vector(15 downto 0) := (others => '0');\r
+ --signal see_dlm_lb_aggr_i, see_dlm_hb_i, see_dlm_hb_buf_i : std_logic;\r
+ --signal stat_sync_dlm_counter_i, stat_sync_dlm_inv_counter_i : unsigned(7 downto 0);\r
+ \r
begin\r
assert IS_SYNC_SLAVE = c_YES \r
report "Support of clock master PHY is not tested anymore and probably broken"\r
DETERMINISTIC_LATENCY_C <= '1' when DETERMINISTIC_LATENCY = c_YES else '0';\r
\r
clk_125_local <= CLK;\r
- CLK_RX_HALF_OUT <= rclk_125_i when IS_SYNC_SLAVE = c_YES else clk_tx_half_i;\r
+ CLK_RX_HALF_OUT <= rclk_125_i;\r
CLK_RX_FULL_OUT <= rclk_250_i;\r
\r
SD_TXDIS_OUT <= '0';\r
rst_i <= (CLEAR or CTRL_OP(0));\r
rst_n_i <= not rst_i;\r
\r
- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate\r
- clk_125_i <= rclk_125_i;\r
- clk_serdes_rx_ref <= clk_125_local;\r
- clk_serdes_tx_ref <= rclk_125_i;\r
- end generate;\r
-\r
- gen_master_clock : if IS_SYNC_SLAVE = c_NO generate\r
- clk_125_i <= clk_tx_half_i; \r
- clk_serdes_rx_ref <= clk_tx_half_i;\r
- clk_serdes_tx_ref <= clk_125_local;\r
- end generate;\r
-\r
------------------------------------------------- \r
-- Serdes\r
------------------------------------------------- \r
tx_full_clk_ch0 => clk_tx_full_i,\r
tx_half_clk_ch0 => open,\r
\r
- fpga_rxrefclk_ch0 => clk_serdes_rx_ref,\r
- fpga_txrefclk => clk_serdes_tx_ref,\r
- txiclk_ch0 => clk_tx_full_i,\r
+ fpga_rxrefclk_ch0 => clk_125_local,\r
+ fpga_txrefclk => rclk_125_i,\r
+ txiclk_ch0 => rclk_250_i,\r
\r
-- RESETS\r
rst_qd_c => rst_qd_i,\r
rx_los_low_ch0_s => rx_los_low_i,\r
rx_cdr_lol_ch0_s => rx_cdr_lol_i,\r
lsm_status_ch0_s => lsm_status_i,\r
- \r
+ \r
SCI_WRDATA => sci_data_in_i,\r
SCI_RDDATA => sci_data_out_i,\r
SCI_ADDR => sci_addr_i(5 downto 0),\r
SCI_RD => sci_read_i,\r
SCI_WRN => sci_write_i\r
);\r
+ \r
+ THE_RX_GEAR: CBMNET_PHY_RX_GEAR \r
+ generic map (\r
+ IS_SYNC_SLAVE => IS_SYNC_SLAVE\r
+ ) port map (\r
+ -- SERDES PORT\r
+ CLK_250_IN => rclk_250_i, -- in std_logic;\r
+ PCS_READY_IN => rx_rst_fsm_ready_i, -- in std_logic;\r
+ SERDES_RESET_OUT=> gear_to_fsm_rst_i, -- out std_logic;\r
+ DATA_IN => rx_data_from_serdes_i, -- in std_logic_vector( 8 downto 0);\r
+\r
+ -- RM PORT\r
+ RM_RESET_IN => rm_rx_to_gear_reset_i, -- in std_logic;\r
+ CLK_125_OUT => rclk_125_i, -- out std_logic;\r
+ RESET_OUT => gear_to_rm_rst_i, -- out std_logic;\r
+ DATA_OUT => rx_data_from_gear_i, -- out std_logic_vector(17 downto 0)\r
+ \r
+ DEBUG_OUT => rx_gear_debug_i\r
+ );\r
+ \r
+ rx_data_i <= rx_data_from_gear_i when rising_edge(clk_125_local);\r
+ \r
+ THE_TX_GEAR: CBMNET_PHY_TX_GEAR\r
+ generic map (IS_SYNC_SLAVE => IS_SYNC_SLAVE)\r
+ port map (\r
+ CLK_250_IN => clk_tx_full_i, -- in std_logic;\r
+ CLK_125_IN => rclk_125_i, -- in std_logic;\r
+ CLK_125_OUT => clk_tx_half_i,\r
+ \r
+ RESET_IN => tx_gear_reset_i, -- in std_logic;\r
+ ALLOW_RELOCK_IN => tx_gear_allow_relock_i, -- in std_logic\r
+ \r
+ TX_READY_OUT => tx_gear_ready_i,\r
+ \r
+ DATA_IN => tx_data_i, -- in std_logic_vector(17 downto 0)\r
+ DATA_OUT => tx_data_to_serdes_i -- out std_logic_vector(8 downto 0);\r
+ );\r
+ tx_gear_reset_i <= not tx_rst_fsm_ready_i;\r
+ tx_gear_allow_relock_i <= '0';\r
\r
+ \r
+ \r
tx_serdes_rst_i <= '0'; --no function\r
serdes_rst_qd_i <= '0'; --included in rst_qd_i\r
\r
rx_error_delay <= rx_error_delay(rx_error_delay'high - 2 downto 0) & rx_dec_error_125_buf_i when rising_edge(clk_125_local);\r
process is \r
begin\r
- wait until rising_edge(clk_125_i);\r
+ wait until rising_edge(rclk_125_i);\r
if RESET='1' then\r
stat_decode_error_counter_i <= (others => '0');\r
elsif rx_dec_error_125_buf_i = "11" then\r
tx_rst_fsm_ready_i <= '1';\r
end if;\r
end process;\r
- \r
- THE_RX_GEAR: CBMNET_PHY_RX_GEAR \r
- generic map (\r
- IS_SYNC_SLAVE => IS_SYNC_SLAVE\r
- ) port map (\r
- -- SERDES PORT\r
- CLK_250_IN => rclk_250_i, -- in std_logic;\r
- PCS_READY_IN => rx_rst_fsm_ready_i, -- in std_logic;\r
- SERDES_RESET_OUT=> gear_to_fsm_rst_i, -- out std_logic;\r
- DATA_IN => rx_data_from_serdes_i, -- in std_logic_vector( 8 downto 0);\r
-\r
- -- RM PORT\r
- RM_RESET_IN => rm_rx_to_gear_reset_i, -- in std_logic;\r
- CLK_125_OUT => rclk_125_i, -- out std_logic;\r
- RESET_OUT => gear_to_rm_rst_i, -- out std_logic;\r
- DATA_OUT => rx_data_from_gear_i, -- out std_logic_vector(17 downto 0)\r
- \r
- DEBUG_OUT => rx_gear_debug_i\r
- );\r
- \r
- process is \r
- variable state_v : std_logic;\r
- variable data_buf_v : std_logic_vector(8 downto 0);\r
- begin\r
- wait until rising_edge(rclk_250_i);\r
- \r
- if state_v = '0' then\r
- rx_data_debug_i(7 downto 0) <= data_buf_v(7 downto 0);\r
- rx_data_debug_i(16) <= data_buf_v(8);\r
- else\r
- rx_data_debug_i(15 downto 8) <= data_buf_v(7 downto 0);\r
- rx_data_debug_i(17) <= data_buf_v(8);\r
- end if;\r
- \r
- data_buf_v := data_buf_v;\r
- state_v := not state_v;\r
- end process;\r
- \r
- rx_data_i <= rx_data_from_gear_i when rising_edge(clk_125_local) or (IS_SYNC_SLAVE = c_YES);\r
- \r
- THE_TX_GEAR: CBMNET_PHY_TX_GEAR\r
- generic map (IS_SYNC_SLAVE => IS_SYNC_SLAVE)\r
- port map (\r
- CLK_250_IN => clk_tx_full_i, -- in std_logic;\r
- CLK_125_IN => clk_serdes_tx_ref, -- in std_logic;\r
- CLK_125_OUT => clk_tx_half_i,\r
- \r
- RESET_IN => tx_gear_reset_i, -- in std_logic;\r
- ALLOW_RELOCK_IN => tx_gear_allow_relock_i, -- in std_logic\r
- \r
- TX_READY_OUT => tx_gear_ready_i,\r
- \r
- DATA_IN => tx_data_i, -- in std_logic_vector(17 downto 0)\r
- \r
- DATA_OUT => tx_data_to_serdes_i -- out std_logic_vector(8 downto 0);\r
- );\r
- tx_gear_reset_i <= not tx_rst_fsm_ready_i;\r
- tx_gear_allow_relock_i <= (not tx_rst_fsm_ready_i and not CTRL_OP(1) and DETERMINISTIC_LATENCY_C) or CTRL_OP(2);\r
- \r
--- process is\r
--- begin\r
--- wait until rising_edge(clk_tx_full_i);\r
--- \r
--- tx_data_debug_state_i <= not tx_data_debug_state_i;\r
--- \r
--- if tx_data_debug_state_i = '1' then\r
--- tx_data_debug_i(7 downto 0) <= tx_data_to_serdes_i(7 downto 0);\r
--- tx_data_debug_i(16) <= tx_data_to_serdes_i(8);\r
--- \r
--- else\r
--- tx_data_debug_i(15 downto 8) <= tx_data_to_serdes_i(7 downto 0);\r
--- tx_data_debug_i(17) <= tx_data_to_serdes_i(8);\r
--- \r
--- end if;\r
--- end process;\r
\r
------------------------------------------------- \r
-- CBMNet Ready Modules\r
INCL_8B10B_DEC => 0\r
)\r
port map ( \r
- rx_clk => clk_125_i, -- in std_logic;\r
+ rx_clk => rclk_125_i, -- in std_logic;\r
res_n_rx => gear_to_rm_n_rst_i, -- in std_logic;\r
rxpcs_reinit => rm_tx_to_rx_reinit_i, -- in std_logic; -- Reinit RXPCS \r
rxdata_in(17 downto 0) => rx_data_i,\r
\r
PHY_RXDATA_OUT <= rx_data_i(15 downto 0);\r
PHY_RXDATA_K_OUT <= rx_data_i(17 downto 16);\r
- gear_to_rm_n_rst_i <= not gear_to_rm_rst_i when rising_edge(clk_125_i);\r
+ gear_to_rm_n_rst_i <= not gear_to_rm_rst_i when rising_edge(rclk_125_i);\r
\r
\r
THE_TX_READY: cn_tx_pcs_wrapper \r
generic map (\r
--- READY_CHAR0 => , --std_logic_vector( 7 downto 0) := K284;\r
--- READY_CHAR1 => , --std_logic_vector( 7 downto 0) := K287;\r
--- ALIGN_CHAR => , --std_logic_vector( 7 downto 0) := K285;\r
--- PMA_INIT_CHAR => , --std_logic_vector(19 downto 0) := x"aaaaa";\r
- \r
REVERSE_OUTPUT => 0, --integer range 0 to 1 := 1;\r
LINK_MASTER => 0, --integer range 0 to 1 := 1;\r
SYNC_SIGNALS => 1, --integer range 0 to 1 := 1;\r
\r
INCL_8B10B_ENC => 0 --integer range 0 to 1 := 1\r
) port map (\r
- tx_clk => clk_125_i, --in std_logic;\r
+ tx_clk => rclk_125_i, --in std_logic;\r
res_n_tx => tx_rst_fsm_ready_buf_i, --in std_logic;\r
pcs_restart => CTRL_OP(14), --in std_logic; -- restart pcs layer\r
pma_ready => tx_gear_ready_i, --in std_logic;\r
\r
rm_rx_status_for_tx_i <= rm_rx_almost_ready_i or rm_rx_ready_i;\r
\r
- -- clock domain crossing from clk_125_local to clk_125_i\r
+ -- clock domain crossing from clk_125_local to rclk_125_i\r
PROC_SYNC_FSM_READY: process is begin\r
- wait until rising_edge(clk_125_i);\r
+ wait until rising_edge(rclk_125_i);\r
\r
if IS_SYNC_SLAVE = c_YES then\r
tx_rst_fsm_ready_buf_i <= tx_rst_fsm_ready_i and not gear_to_rm_rst_i;\r
end if;\r
end process;\r
\r
- serdes_ready_i <= rm_tx_ready_i and rm_rx_rxpcs_ready_i when rising_edge(clk_125_i);\r
+ serdes_ready_i <= rm_tx_ready_i and rm_rx_rxpcs_ready_i when rising_edge(rclk_125_i);\r
led_ok_i <= serdes_ready_i;\r
SERDES_ready <= serdes_ready_i;\r
\r
last_rx_serdes_rst_i := rx_serdes_rst_i;\r
end process;\r
\r
--- PROC_SENSE_RX_DLM0: process is \r
--- variable detected_first_word_v : std_logic := '0';\r
--- begin\r
--- wait until rising_edge(rclk_250_i);\r
--- low_level_rx_see_dlm0 <= '0';\r
--- \r
--- if detected_first_word_v = '0' then\r
--- if rx_data_from_serdes_i = "1" & x"fb" then\r
--- detected_first_word_v := '1';\r
--- end if;\r
--- \r
--- else\r
--- detected_first_word_v := '0';\r
--- if rx_data_from_serdes_i = "001101010" then\r
--- low_level_rx_see_dlm0 <= '1';\r
--- end if;\r
--- \r
--- end if;\r
--- end process;\r
- \r
--- PROC_SENSE_TX_DLM0: process is \r
--- variable detected_first_word_v : std_logic := '0';\r
--- begin\r
--- wait until rising_edge(clk_tx_full_i);\r
--- low_level_tx_see_dlm0 <= '0';\r
--- \r
--- if detected_first_word_v = '0' then\r
--- if tx_data_to_serdes_i = "1" & x"fb" then\r
--- detected_first_word_v := '1';\r
--- end if;\r
--- \r
--- else\r
--- detected_first_word_v := '0';\r
--- if tx_data_to_serdes_i = "001101010" then\r
--- low_level_tx_see_dlm0 <= '1';\r
--- end if;\r
--- \r
--- end if;\r
--- end process;\r
- \r
PROC_SENSE_TX_DLM125: process is\r
begin\r
- wait until rising_edge(clk_125_i);\r
+ wait until rising_edge(rclk_125_i);\r
\r
low_level_tx_see_dlm0_125 <= '0';\r
if tx_data_i = "10" & x"fb6a" then\r
end if;\r
end process;\r
\r
- proc_sense_init_ack: process is \r
- begin\r
- wait until rising_edge(clk_125_i);\r
- if reset = '1' then\r
- stat_init_ack_counter_i <= (others => '0');\r
- elsif rx_data_i = "11" & K297 & K283 then \r
- stat_init_ack_counter_i <= stat_init_ack_counter_i + 1;\r
- end if;\r
- end process;\r
- \r
- process is\r
+ process is\r
variable rx_v, tx_v : std_logic_vector(17 downto 0);\r
- begin\r
- wait until rising_edge(clk_125_i);\r
- \r
+ begin\r
+ wait until rising_edge(rclk_125_i);\r
+\r
if reset = '1' or rx_v /= rx_data_i then rx_stab_i <= (others => '0');\r
- else rx_stab_i <= rx_stab_i + 1; end if;\r
+ else rx_stab_i <= rx_stab_i + 1; end if;\r
\r
if reset = '1' or tx_v /= tx_data_i then tx_stab_i <= (others => '0');\r
else tx_stab_i <= tx_stab_i + 1; end if;\r
- \r
- rx_v := rx_data_i;\r
- tx_v := tx_data_i;\r
- end process;\r
+\r
+ rx_v := rx_data_i;\r
+ tx_v := tx_data_i;\r
+ end process;\r
\r
\r
PROC_SENSE_DLMS: process begin\r
- wait until rising_edge(clk_125_i);\r
+ wait until rising_edge(rclk_125_i);\r
\r
if serdes_ready_i = '0' then\r
stat_dlm_counter_i <= (others => '0');\r
DEBUG_OUT(315 downto 244) <= rx_data_sp_i3(17 downto 0) & rx_data_sp_i2(17 downto 0) & rx_data_sp_i1(17 downto 0) & rx_data_sp_i0(17 downto 0);\r
\r
DEBUG_OUT(333 downto 316) <= PHY_TXDATA_K_IN(1 downto 0) & PHY_TXDATA_IN(15 downto 0);\r
+ --DEBUG_OUT(341 downto 334) <= stat_sync_dlm_inv_counter_i(7 downto 0) when rising_edge(rclk_125_i);\r
+ --DEBUG_OUT(349 downto 342) <= stat_sync_dlm_counter_i(7 downto 0) when rising_edge(rclk_125_i); \r
+ \r
+\r
\r
--DEBUG_OUT(255 downto 170) <= (others => '0');\r
\r
-- DEBUG_OUT_END\r
\r
- process is\r
- begin\r
- wait until rising_edge(rclk_125_i);\r
- if rx_data_i /= "10" & x"fcc3" then\r
- rx_data_sp_i0 <= rx_data_i;\r
- rx_data_sp_i1 <= rx_data_sp_i0;\r
- rx_data_sp_i2 <= rx_data_sp_i1;\r
- rx_data_sp_i3 <= rx_data_sp_i2;\r
- end if;\r
- end process;\r
+ process is\r
+ begin\r
+ wait until rising_edge(rclk_125_i);\r
+ if rx_data_i /= "10" & x"fcc3" then\r
+ rx_data_sp_i0 <= rx_data_i;\r
+ rx_data_sp_i1 <= rx_data_sp_i0;\r
+ rx_data_sp_i2 <= rx_data_sp_i1;\r
+ rx_data_sp_i3 <= rx_data_sp_i2;\r
+ end if;\r
+ end process;\r
\r
+ --PROC_SEE_FAST_DLM: process is\r
+ --variable saw_lb_v, saw_hb_v : std_logic;\r
+ --begin\r
+ --wait until rising_edge(rclk_250_i);\r
+ \r
+ --see_dlm_hb_i <= '0' ;\r
+ --if rx_data_from_serdes_i = '1' & K277 then\r
+ --see_dlm_hb_i <= '1';\r
+ --end if;\r
+ --see_dlm_hb_buf_i <= see_dlm_hb_i;\r
+ \r
+ --see_dlm_lb_aggr_i <= '0';\r
+ --if rx_data_from_serdes_i = '1' & K277 then\r
+ --see_dlm_lb_aggr_i <= OR_ALL(see_dlm_lb_buf_i);\r
+ --end if;\r
+ \r
+\r
+ \r
+ --if rst_i = '1' then\r
+ --stat_sync_dlm_counter_i <= (others => '0');\r
+ --stat_sync_dlm_inv_counter_i <= (others => '0');\r
+ --saw_lb_v := '0';\r
+ --saw_hb_v := '0';\r
+ \r
+ --else\r
+ --if see_dlm_hb_buf_i = '1' and saw_lb_v = '1' then\r
+ --stat_sync_dlm_counter_i <= stat_sync_dlm_counter_i + 1;\r
+ --end if;\r
+ \r
+ --if see_dlm_lb_aggr_i = '1' and saw_hb_v = '1' then\r
+ --stat_sync_dlm_inv_counter_i <= stat_sync_dlm_inv_counter_i + 1;\r
+ --end if;\r
+ \r
+ --saw_lb_v := see_dlm_lb_aggr_i;\r
+ --saw_hb_v := see_dlm_hb_buf_i;\r
+ --end if;\r
+ --end process;\r
+ \r
+ --see_dlm_lb_i(0) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(10, 3) else '0';\r
+ --see_dlm_lb_i(1) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(14, 1) else '0';\r
+ --see_dlm_lb_i(2) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(20, 1) else '0';\r
+ --see_dlm_lb_i(3) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(20, 6) else '0';\r
+ \r
+ --see_dlm_lb_i(4) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(22, 3) else '0';\r
+ --see_dlm_lb_i(5) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(28, 2) else '0';\r
+ --see_dlm_lb_i(6) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(28, 5) else '0';\r
+ --see_dlm_lb_i(7) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(06, 2) else '0';\r
+ \r
+ --see_dlm_lb_i(8) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(14, 6) else '0';\r
+ --see_dlm_lb_i(9) <= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 3, 1) else '0';\r
+ --see_dlm_lb_i(10)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(11, 2) else '0';\r
+ --see_dlm_lb_i(11)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(17, 2) else '0';\r
+ \r
+ --see_dlm_lb_i(12)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(25, 3) else '0';\r
+ --see_dlm_lb_i(13)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE(17, 5) else '0';\r
+ --see_dlm_lb_i(14)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 3, 6) else '0';\r
+ --see_dlm_lb_i(15)<= '1' when rx_data_from_serdes_i = '0' & EBTB_D_ENCODE( 5, 3) else '0';\r
+\r
+ --see_dlm_lb_buf_i <= see_dlm_lb_i when rising_edge(rclk_250_i);\r
\r
--- DEBUG_OUT(127 downto 108) <= "00" & tx_data_debug_i(17 downto 0);\r
--- DEBUG_OUT(147 downto 128) <= "00" & rx_data_debug_i(17 downto 0) when rising_edge(clk_125_local);\r
-\r
- -- STAT_OP REGISTER\r
--- STAT_OP <= tx_data_i(15 downto 0) when CTRL_OP(9 downto 8) = "01" else \r
--- rx_data_i(15 downto 0) when CTRL_OP(9 downto 8) = "10" else\r
--- test_line_i;\r
--- \r
--- test_line_i <= test_line_i(14 downto 0) & test_line_i(15) when rising_edge(clk_125_local);\r
\r
--- STAT_OP(6 downto 0) <= tx_data_to_serdes_i(6 downto 0);\r
--- STAT_OP( 7) <= low_level_rx_see_dlm0;\r
--- STAT_OP( 8) <= clk_125_local;\r
--- STAT_OP( 9) <= rclk_250_i;\r
--- STAT_OP(10) <= rclk_125_i;\r
--- STAT_OP(11) <= clk_tx_full_i;\r
--- STAT_OP(12) <= clk_tx_half_i;\r
--- STAT_OP(13) <= low_level_tx_see_dlm0;\r
end generate;\r
end architecture;
\ No newline at end of file
show8b10b( ($data >> 0) & 0xff, ($data >> 16) & 1 );
}
+sub cbmnet_definitions {
+ my $inp = shift;
+ my %cbmnet_defs = (
+ "K.28.3 D.14.1", "SOP0 ", "K.27.7 D.03.1", "DLM9 ",
+ "K.28.3 D.20.1", "SOP1 ", "K.27.7 D.11.2", "DLM10 ",
+ "K.28.3 D.20.6", "SOP2 ", "K.27.7 D.17.2", "DLM11 ",
+ "K.28.3 D.22.3", "SOP3 ", "K.27.7 D.25.3", "DLM12 ",
+ "K.28.3 D.28.2", "SOSC0 ", "K.27.7 D.17.5", "DLM13 ",
+ "K.28.3 D.28.5", "SOSC1 ", "K.27.7 D.03.6", "DLM14 ",
+ "K.28.3 D.06.2", "SOSC2 ", "K.27.7 D.05.3", "DLM15 ",
+ "K.28.3 D.14.6", "SOSC3 ", "K.28.7 D.10.3", "NACK0 ",
+ "K.28.3 D.03.1", "ACK0 ", "K.28.7 D.14.1", "NACK1 ",
+ "K.28.3 D.11.2", "ACK1 ", "K.28.7 D.20.1", "NACK2 ",
+ "K.28.3 D.17.2", "ACK2 ", "K.28.7 D.20.6", "NACK3 ",
+ "K.28.3 D.25.3", "ACK3 ", "K.28.7 D.22.3", "NACK00 ",
+ "K.28.3 D.17.5", "ACK00 ", "K.28.7 D.28.2", "NACK01 ",
+ "K.28.3 D.03.6", "ACK01 ", "K.28.7 D.28.5", "NACK02 ",
+ "K.28.3 D.05.3", "ACK02 ", "K.28.7 D.06.2", "NACK03 ",
+ "K.28.3 D.10.3", "ACK03 ", "K.28.7 D.03.1", "EOP_ERR ",
+ "K.27.7 D.10.3", "DLM0 ", "K.28.7 D.11.2", "EOP_C ",
+ "K.27.7 D.14.1", "DLM1 ", "K.28.7 D.17.2", "EOP ",
+ "K.27.7 D.20.1", "DLM2 ", "K.28.7 D.17.5", "RETRANS ",
+ "K.27.7 D.20.6", "DLM3 ", "K.28.7 D.03.6", "IDLESYNC",
+ "K.27.7 D.22.3", "DLM4 ", "K.28.7 D.05.3", "INIT ",
+ "K.27.7 D.28.2", "DLM5 ", "K.29.7 K.28.3", "ACK_INIT",
+ "K.27.7 D.28.5", "DLM6 ", "K.28.7 D.14.6", "SLAVE1 ",
+ "K.27.7 D.06.2", "DLM7 ", "K.28.7 D.25.3", "SLAVE2 ",
+ "K.27.7 D.14.6", "DLM8 ", "K.30.7 K.28.3", "SLAVE3 ",
+ "D.00.0 K.28.4", "READY0 ", "D.00.0 K.28.7", "READY1 ",
+ "D.00.0 K.28.5", "ALIGN ");
+ return exists $cbmnet_defs{$inp} ? $cbmnet_defs{$inp} : " ";
+}
my @old_results;
my $first_one = 1;
my $len = $def->[2];
my $text = sprintf($len == 1 ? "%x" : "0x%0" . (ceil(($len+3) / 4.0)) . "x", ($reg >> $idx) & ((1 << $len) - 1));
if ($len == 18) {
- $text .= " " . show8b10bWord(($reg >> $idx) & ((1 << $len) - 1));
+ my $ebtb = show8b10bWord(($reg >> $idx) & ((1 << $len) - 1));
+ $text .= " " . $ebtb . ": " . cbmnet_definitions($ebtb);
}
push @slices, $text;
}
}
@old_results = @results;
-
-
+
+print `trbcmd rm 0x8001 0xa010 7 0`;
sleep 1;
print $first_one ? `clear` : chr(27) . "[1;1H";
$first_one = 0;
jspc29 / trb3.git / commitdiff