architecture RTL of FiFoDataMuxWithConversion is
signal ticks_counter : unsigned(f_log2(g_clockspeed) - 1 downto 0) := (others => '0');
- signal inword_counter : t_counter32_array(0 to g_inputs - 1) := (others => (others => '0'));
+ signal inword_counter : t_counter32_array(0 to g_inputs - 1) := (others => (others => '0'));
signal increase_counter : std_logic_vector(g_inputs - 1 downto 0) := (others => '0');
signal fifo_full_i : std_logic;
end component RoundRobinArbiter;
--data width converter signals
- constant padding_0 : std_logic_vector(23 downto 0) := (others => '0');
- constant padding_1 : std_logic_vector(15 downto 0) := (others => '0');
- constant padding_2 : std_logic_vector(7 downto 0) := (others => '0');
+ constant padding_0 : std_logic_vector(23 downto 0) := (others => '0');
+ constant padding_1 : std_logic_vector(15 downto 0) := (others => '0');
+ constant padding_2 : std_logic_vector(7 downto 0) := (others => '0');
type convert_mem_type is array (0 to 1) of std_logic_vector(c_mupixhitsize - 1 downto 0);
- signal data_shift : convert_mem_type := (others => (others => '0'));
- signal conversioncounter : integer range 0 to 6 := 0;
- signal empty_delay : std_logic_vector(1 downto 0) := (others => '0');
+ signal data_shift : convert_mem_type := (others => (others => '0'));
+ signal data_select : std_logic_vector(c_mupixhitsize - 1 downto 0) := (others => '0');
+ signal conversioncounter : integer range 0 to 6 := 0;
+ signal empty_delay : std_logic_vector(1 downto 0) := (others => '0');
begin
request_i <= not fifo_empty and fifo_mask;
+ -- arbitration of inputs
arbiter_1 : component RoundRobinArbiter
generic map(
g_num_channels => g_inputs
requests => request_i,
grant => grant_i);
+ -- select fifo by grant from arbiter
fifo_select_proc : process(grant_i) is
variable sel : integer range -1 to g_inputs - 1;
begin
fifo_full_i <= full;
end process full_flag_proc;
+ -- measure input words per second of arbiter inputs
input_freq : process (clk) is
begin
if rising_edge(clk) then
end if;
end process input_freq;
+ -- purpose: select data from fifo data input (assume max of four inputs)
+ -- type : combinational
+ data_sel_2 : if g_inputs = 2 generate
+ data_select_proc : process (fifo_datain, fifo_sel_reg) is
+ begin -- process data_select
+ case fifo_sel_reg is
+ when 0 =>
+ data_select <= fifo_datain(g_datawidthfifo - 1 downto 0);
+ when 1 =>
+ data_select <= fifo_datain(2 * g_datawidthfifo - 1 downto g_datawidthfifo);
+ when others =>
+ data_select <= (others => '0');
+ end case;
+ end process data_select_proc;
+ end generate data_sel_2;
+ data_sel_3 : if g_inputs = 3 generate
+ data_select_proc : process (fifo_datain, fifo_sel_reg) is
+ begin -- process data_select
+ case fifo_sel_reg is
+ when 0 =>
+ data_select <= fifo_datain(g_datawidthfifo - 1 downto 0);
+ when 1 =>
+ data_select <= fifo_datain(2 * g_datawidthfifo - 1 downto g_datawidthfifo);
+ when 2 =>
+ data_select <= fifo_datain(3 * g_datawidthfifo - 1 downto 2 * g_datawidthfifo);
+ when others =>
+ data_select <= (others => '0');
+ end case;
+ end process data_select_proc;
+ end generate data_sel_3;
+
+ data_sel_4 : if g_inputs = 4 generate
+ data_select_proc : process (fifo_datain, fifo_sel_reg) is
+ begin -- process data_select
+ case fifo_sel_reg is
+ when 0 =>
+ data_select <= fifo_datain(g_datawidthfifo - 1 downto 0);
+ when 1 =>
+ data_select <= fifo_datain(2 * g_datawidthfifo - 1 downto g_datawidthfifo);
+ when 2 =>
+ data_select <= fifo_datain(3 * g_datawidthfifo - 1 downto 2 * g_datawidthfifo);
+ when 3 =>
+ data_select <= fifo_datain(4 * g_datawidthfifo - 1 downto 3 * g_datawidthfifo);
+ when others =>
+ data_select <= (others => '0');
+ end case;
+ end process data_select_proc;
+ end generate data_sel_4;
+
+
+ -- multiplexing of fifo data inputs into output and width conversion from
+ -- mupix hit word width to 32 bit
mux_proc : process(clk) is
begin
if rising_edge(clk) then
-- width conversion
conversioncounter <= conversioncounter + 1;
data_shift(1) <= data_shift(0);
- data_shift(0) <= fifo_datain((fifo_sel_reg + 1)*g_datawidthfifo - 1 downto g_datawidthfifo*fifo_sel_reg);
+ data_shift(0) <= data_select;
if empty_delay = "11" then
mux_fsm <= idle;
end if;
end if;
end process mux_proc;
-
fifo_full_o <= fifo_full_i;
end architecture RTL;
sync_output : out std_logic_vector(width - 1 downto 0));
end component InputSynchronizer;
- component serdes_fifo
+ component serdes_fifo -- regenerate if number of mupix hit bits changes
port (
Data : in std_logic_vector(39 downto 0);
WrClock : in std_logic;
signal rx_komma_sync : std_logic_vector(3 downto 0);
-- fifo signals
- signal fifo_data_oi : std_logic_vector(c_links*c_mupixhitsize - 1 downto 0);
signal fifo_data_ii : std_logic_vector(c_links*c_mupixhitsize - 1 downto 0);
- signal fifo_empty_i : std_logic_vector(c_links - 1 downto 0) := (others => '0');
- signal fifo_full_i : std_logic_vector(c_links - 1 downto 0) := (others => '0');
signal fifo_wren_i : std_logic_vector(c_links - 1 downto 0) := (others => '0');
- signal fifo_rden_i : std_logic_vector(c_links - 1 downto 0) := (others => '0');
constant fifo_depth : integer := 11; -- fifo depth (change when regenerating FIFO IP core)
signal fifo_readcnt_i : std_logic_vector(c_links*fifo_depth - 1 downto 0);
WrClock => clkrx(j),
RdClock => sysclk,
WrEn => fifo_wren_i(j),
- RdEn => fifo_rden_i(j),
+ RdEn => fifo_rden(j),
Reset => reset_fifos_i,
RPReset => reset_fifos_i,
- Q => fifo_data_oi((j + 1)*c_mupixhitsize - 1 downto j*c_mupixhitsize),
+ Q => fifo_data((j + 1)*c_mupixhitsize - 1 downto j*c_mupixhitsize),
RCNT => fifo_readcnt_i((j + 1)*fifo_depth - 1 downto j*fifo_depth),
- Empty => fifo_empty_i(j),
- Full => fifo_full_i(j));
+ Empty => fifo_empty(j),
+ Full => fifo_full(j));
end generate generate_fifo;
-- error counters (using gray counters because of possible clock domain
jspc29 / trb3.git / commitdiff