signal fwd_data : std_logic_vector(4 * 8 - 1 downto 0);
signal fwd_dv, fwd_sop, fwd_eop, fwd_ready, fwd_full : std_logic_vector(3 downto 0);
+ signal fwd_mac : std_logic_vector(4 * 48 - 1 downto 0);
+ signal fwd_ip : std_logic_vector(4 * 32 - 1 downto 0);
+ signal fwd_udp : std_logic_vector(4 * 16 - 1 downto 0);
component OSCF is
port (
BUS_REG_RX => busgbereg_rx,
BUS_REG_TX => busgbereg_tx,
+ FWD_DST_MAC_IN => fwd_mac,
+ FWD_DST_IP_IN => fwd_ip,
+ FWD_DST_UDP_IN => fwd_udp,
FWD_DATA_IN => fwd_data,
FWD_DATA_VALID_IN => fwd_dv,
FWD_SOP_IN => fwd_sop,