\r
library work;\r
use work.trb_net_std.all;\r
-use work.trb_net_components.all;\r
+--use work.trb_net_components.all;\r
use work.gbe_protocols.all;\r
\r
--********\r
-- data by FR_FRAME_VALID_OUT.\r
\r
entity gbe_frame_receiver is\r
-port (\r
- CLK : in std_logic; -- system clock\r
- RESET : in std_logic;\r
- LINK_OK_IN : in std_logic;\r
- ALLOW_RX_IN : in std_logic;\r
- MY_MAC_IN : in std_logic_vector(47 downto 0);\r
--- killer ping\r
- MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
- ISSUE_REBOOT_OUT : out std_logic;\r
--- input signals from TS_MAC\r
- MAC_RX_EOF_IN : in std_logic; -- End Of Frame\r
- MAC_RX_ER_IN : in std_logic; -- only for statistics\r
- MAC_RXD_IN : in std_logic_vector(7 downto 0); -- RX data\r
- MAC_RX_EN_IN : in std_logic; -- write signal\r
--- output signal to control logic\r
- FR_Q_OUT : out std_logic_vector(8 downto 0);\r
- FR_RD_EN_IN : in std_logic;\r
- FR_FRAME_VALID_OUT : out std_logic;\r
- FR_GET_FRAME_IN : in std_logic;\r
- FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);\r
- FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0);\r
- FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0);\r
- FR_ALLOWED_TYPES_IN : in std_logic_vector(31 downto 0);\r
- FR_ALLOWED_IP_IN : in std_logic_vector(31 downto 0);\r
- FR_ALLOWED_UDP_IN : in std_logic_vector(31 downto 0);\r
- FR_VLAN_ID_IN : in std_logic_vector(31 downto 0);\r
---\r
- FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);\r
- FR_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);\r
- FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);\r
- FR_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);\r
- FR_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);\r
- FR_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);\r
---\r
- OOB_REGISTER_0_OUT : out std_logic_vector(31 downto 0);\r
- OOB_REGISTER_1_OUT : out std_logic_vector(31 downto 0);\r
- OOB_REGISTER_2_OUT : out std_logic_vector(31 downto 0);\r
- OOB_REGISTER_3_OUT : out std_logic_vector(31 downto 0);\r
---\r
- MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0);\r
- MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0);\r
- MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0);\r
- DEBUG_OUT : out std_logic_vector(15 downto 0)\r
-);\r
+ port(\r
+ CLK : in std_logic; -- system clock\r
+ RESET : in std_logic;\r
+ LINK_OK_IN : in std_logic;\r
+ ALLOW_RX_IN : in std_logic;\r
+ MY_MAC_IN : in std_logic_vector(47 downto 0);\r
+ -- killer ping\r
+ MY_TRBNET_ADDRESS_IN : in std_logic_vector(15 downto 0) := (others => '0');\r
+ ISSUE_REBOOT_OUT : out std_logic;\r
+ -- input signals from TS_MAC\r
+ MAC_RX_EOF_IN : in std_logic; -- End Of Frame\r
+ MAC_RX_ER_IN : in std_logic; -- only for statistics\r
+ MAC_RXD_IN : in std_logic_vector(7 downto 0); -- RX data\r
+ MAC_RX_EN_IN : in std_logic; -- write signal\r
+ -- output signal to control logic\r
+ FR_Q_OUT : out std_logic_vector(8 downto 0); -- interconnect to gbe_receive_control\r
+ FR_RD_EN_IN : in std_logic; -- interconnect to gbe_receive_control\r
+ FR_FRAME_VALID_OUT : out std_logic; -- interconnect to gbe_receive_control\r
+ FR_GET_FRAME_IN : in std_logic; -- interconnect to gbe_receive_control\r
+ FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); -- interconnect to gbe_receive_control\r
+ FR_FRAME_PROTO_OUT : out std_logic_vector(15 downto 0); -- interconnect to gbe_receive_control\r
+ FR_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); -- interconnect to gbe_receive_control\r
+ FR_PS_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
+ --\r
+ FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);\r
+ FR_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);\r
+ FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);\r
+ FR_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);\r
+ FR_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);\r
+ FR_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);\r
+ --\r
+ OOB_REGISTER_0_OUT : out std_logic_vector(31 downto 0);\r
+ OOB_REGISTER_1_OUT : out std_logic_vector(31 downto 0);\r
+ OOB_REGISTER_2_OUT : out std_logic_vector(31 downto 0);\r
+ OOB_REGISTER_3_OUT : out std_logic_vector(31 downto 0);\r
+ --\r
+ MONITOR_RX_BYTES_OUT : out std_logic_vector(31 downto 0);\r
+ MONITOR_RX_FRAMES_OUT : out std_logic_vector(31 downto 0);\r
+ MONITOR_DROPPED_OUT : out std_logic_vector(31 downto 0);\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
end gbe_frame_receiver;\r
\r
-architecture gbe_frame_receiver_arch of gbe_frame_receiver is\r
+-- This entity receives frames from the MAC. The MAC will send the frames once they are received \r
+-- from SGMII core. Start of frame is marked by 'new_frame' signal. The incoming frame will be \r
+-- reviewed, and checked if it should be forwarded to the next level.\r
+-- First check is MAC address: only broadcast frames and frames with the board's MAC address are accepted.\r
+-- VLAN tagged frames are handled, but will be checked later.\r
+-- Second check is done inside gbe_type_validator: IPV4 UDP with correct port number are accepted,\r
+-- as well as ICMP inside IPv4. In addition, in gbe_protocols more accepted combinations can be defined.\r
+-- VLAN tagged frames are accepted, in case of tag == 0x0000, or if the VLAN tag is identical to one of the\r
+-- two stored ones.\r
\r
-attribute syn_encoding : string;\r
-type filter_states is (IDLE, REMOVE_DEST, REMOVE_SRC, REMOVE_TYPE, SAVE_FRAME, DROP_FRAME,\r
- REMOVE_VID, REMOVE_VTYPE, REMOVE_IP, REMOVE_UDP, DECIDE, CLEANUP);\r
-signal filter_current_state, filter_next_state : filter_states;\r
-attribute syn_encoding of filter_current_state : signal is "onehot";\r
-\r
-signal fifo_wr_en : std_logic;\r
-signal rx_bytes_ctr : std_logic_vector(15 downto 0);\r
-signal frame_valid_q : std_logic;\r
-signal delayed_frame_valid : std_logic;\r
-signal delayed_frame_valid_q : std_logic;\r
-\r
-signal rec_fifo_empty : std_logic;\r
-signal rec_fifo_full : std_logic;\r
-signal sizes_fifo_full : std_logic;\r
-signal sizes_fifo_empty : std_logic;\r
-\r
-signal remove_ctr : unsigned(7 downto 0);\r
-signal new_frame : std_logic;\r
-signal new_frame_lock : std_logic := '0';\r
-signal saved_frame_type : std_logic_vector(15 downto 0);\r
-signal saved_vid : std_logic_vector(15 downto 0) := (others => '0');\r
-signal saved_src_mac : std_logic_vector(47 downto 0);\r
-signal saved_dest_mac : std_logic_vector(47 downto 0);\r
-signal frame_type_valid : std_logic;\r
-signal saved_proto : std_logic_vector(7 downto 0);\r
-signal saved_src_ip : std_logic_vector(31 downto 0);\r
-signal saved_dest_ip : std_logic_vector(31 downto 0);\r
-signal saved_src_udp : std_logic_vector(15 downto 0);\r
-signal saved_dest_udp : std_logic_vector(15 downto 0);\r
-\r
-signal error_frames_ctr : unsigned(15 downto 0);\r
-signal dbg_rec_frames : unsigned(31 downto 0);\r
-signal dbg_drp_frames : unsigned(31 downto 0);\r
-signal mon_rec_bytes : unsigned(31 downto 0);\r
-\r
-signal state : std_logic_vector(3 downto 0);\r
-\r
-signal rx_data : std_logic_vector(8 downto 0);\r
-signal fr_q : std_logic_vector(8 downto 0);\r
-\r
-signal fr_src_ip : std_logic_vector(31 downto 0);\r
-signal fr_dest_ip : std_logic_vector(31 downto 0);\r
-signal fr_dest_udp : std_logic_vector(15 downto 0);\r
-signal fr_src_udp : std_logic_vector(15 downto 0);\r
-signal fr_frame_size : std_logic_vector(15 downto 0);\r
-signal fr_frame_proto : std_logic_vector(15 downto 0);\r
-signal fr_dest_mac : std_logic_vector(47 downto 0);\r
-signal fr_src_mac : std_logic_vector(47 downto 0);\r
-signal fr_ip_proto : std_logic_vector(7 downto 0);\r
-\r
-signal xxx0 : std_logic_vector(7 downto 0);\r
-signal xxx1 : std_logic_vector(7 downto 0);\r
-\r
-signal oob_register_0_int : std_logic_vector(31 downto 0);\r
-signal oob_register_1_int : std_logic_vector(31 downto 0);\r
-signal oob_register_2_int : std_logic_vector(31 downto 0);\r
-signal oob_register_3_int : std_logic_vector(31 downto 0);\r
-signal oob_write : std_logic;\r
-\r
-attribute syn_preserve : boolean;\r
-attribute syn_keep : boolean;\r
-attribute syn_keep of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true;\r
-attribute syn_preserve of rec_fifo_empty, rec_fifo_full, state, sizes_fifo_empty, sizes_fifo_full : signal is true;\r
+-- BUG: MAC_RX_ERROR is not really used. Broken frames will not be discarded!\r
\r
-begin\r
+-- BUG: no protection against overflow of FIFOs!\r
\r
--- new_frame is asserted when first byte of the frame arrives\r
-THE_NEW_FRAME_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) )then\r
- if ( (LINK_OK_IN = '0') or (MAC_RX_EOF_IN = '1') ) then\r
- new_frame <= '0';\r
- new_frame_lock <= '0';\r
- elsif( (new_frame_lock = '0') and (MAC_RX_EN_IN = '1') ) then\r
- new_frame <= '1';\r
- new_frame_lock <= '1';\r
- else\r
- new_frame <= '0';\r
- end if;\r
- end if;\r
-end process THE_NEW_FRAME_PROC;\r
+architecture gbe_frame_receiver_arch of gbe_frame_receiver is\r
\r
-THE_FILTER_MACHINE_PROC: process( CLK, RESET )\r
-begin\r
- if ( RESET = '1' ) then\r
- filter_current_state <= IDLE;\r
- elsif( rising_edge(CLK) ) then\r
- filter_current_state <= filter_next_state;\r
- end if;\r
-end process THE_FILTER_MACHINE_PROC;\r
+ attribute syn_encoding : string;\r
+ type filter_states is (IDLE, REMOVE_DEST, REMOVE_SRC, REMOVE_TYPE, SAVE_FRAME, DROP_FRAME,\r
+ REMOVE_IP, REMOVE_UDP, DELAY, CLEANUP);\r
+ signal filter_current_state, filter_next_state : filter_states;\r
+ attribute syn_encoding of filter_current_state : signal is "onehot";\r
+\r
+ signal fifo_wr_en : std_logic;\r
+ signal rx_bytes_ctr : std_logic_vector(15 downto 0);\r
+ signal frame_valid_q : std_logic;\r
+ signal delayed_frame_valid : std_logic;\r
+ signal delayed_frame_valid_q : std_logic;\r
+\r
+ signal rec_fifo_empty : std_logic;\r
+ signal rec_fifo_full : std_logic;\r
+ signal sizes_fifo_full : std_logic;\r
+ signal sizes_fifo_empty : std_logic;\r
+\r
+ signal remove_ctr : unsigned(7 downto 0);\r
+ signal new_frame : std_logic;\r
+ signal new_frame_lock : std_logic := '0';\r
+ signal saved_frame_type : std_logic_vector(15 downto 0);\r
+ signal saved_src_mac : std_logic_vector(47 downto 0);\r
+ signal saved_dest_mac : std_logic_vector(47 downto 0);\r
+ signal frame_type_valid : std_logic;\r
+ signal saved_proto : std_logic_vector(7 downto 0);\r
+ signal saved_src_ip : std_logic_vector(31 downto 0);\r
+ signal saved_dest_ip : std_logic_vector(31 downto 0);\r
+ signal saved_src_udp : std_logic_vector(15 downto 0);\r
+ signal saved_dest_udp : std_logic_vector(15 downto 0);\r
+\r
+ signal error_frames_ctr : unsigned(15 downto 0);\r
+ signal dbg_rec_frames : unsigned(31 downto 0);\r
+ signal dbg_drp_frames : unsigned(31 downto 0);\r
+ signal mon_rec_bytes : unsigned(31 downto 0);\r
+\r
+ signal state : std_logic_vector(3 downto 0);\r
+\r
+ signal rx_data : std_logic_vector(8 downto 0);\r
+ signal fr_q : std_logic_vector(8 downto 0);\r
+\r
+ signal fr_src_ip : std_logic_vector(31 downto 0);\r
+ signal fr_dest_ip : std_logic_vector(31 downto 0);\r
+ signal fr_dest_udp : std_logic_vector(15 downto 0);\r
+ signal fr_src_udp : std_logic_vector(15 downto 0);\r
+ signal fr_frame_size : std_logic_vector(15 downto 0);\r
+ signal fr_frame_proto : std_logic_vector(15 downto 0);\r
+ signal fr_dest_mac : std_logic_vector(47 downto 0);\r
+ signal fr_src_mac : std_logic_vector(47 downto 0);\r
+ signal fr_ip_proto : std_logic_vector(7 downto 0);\r
+ signal fr_ps : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
+\r
+ signal xxx0 : std_logic_vector(7 downto 0);\r
+ signal xxx1 : std_logic_vector(7 downto 0);\r
+\r
+ signal oob_register_0_int : std_logic_vector(31 downto 0);\r
+ signal oob_register_1_int : std_logic_vector(31 downto 0);\r
+ signal oob_register_2_int : std_logic_vector(31 downto 0);\r
+ signal oob_register_3_int : std_logic_vector(31 downto 0);\r
+ signal oob_write : std_logic;\r
+\r
+ signal proto_select_x : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
+ signal proto_select : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
+\r
+ signal set_proto_x : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);\r
\r
-THE_FILTER_MACHINE : process( filter_current_state, saved_frame_type, LINK_OK_IN, saved_proto, MY_MAC_IN,\r
- saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN)\r
begin\r
- case filter_current_state is\r
\r
- when IDLE =>\r
- state <= x"1";\r
- if( (new_frame = '1') and (ALLOW_RX_IN = '1') and (LINK_OK_IN = '1') ) then\r
- filter_next_state <= REMOVE_DEST;\r
+ -- Debug lines\r
+ DEBUG_OUT(31 downto 26) <= (others => '0');\r
+ \r
+ DEBUG_OUT(15) <= frame_valid_q;\r
+ DEBUG_OUT(14) <= fifo_wr_en;\r
+ DEBUG_OUT(13) <= frame_type_valid;\r
+ DEBUG_OUT(12) <= new_frame_lock;\r
+ DEBUG_OUT(11) <= new_frame;\r
+ DEBUG_OUT(10) <= MAC_RX_ER_IN;\r
+ DEBUG_OUT(9) <= MAC_RX_EOF_IN;\r
+ DEBUG_OUT(8) <= MAC_RX_EN_IN;\r
+ DEBUG_OUT(7 downto 0) <= MAC_RXD_IN;\r
+\r
+ -- new_frame is asserted when first byte of the frame arrives\r
+ PROC_NEW_FRAME: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) )then\r
+ if ( (LINK_OK_IN = '0') or (MAC_RX_EOF_IN = '1') ) then\r
+ new_frame <= '0';\r
+ new_frame_lock <= '0';\r
+ elsif( (new_frame_lock = '0') and (MAC_RX_EN_IN = '1') ) then\r
+ new_frame <= '1';\r
+ new_frame_lock <= '1';\r
else\r
- filter_next_state <= IDLE;\r
+ new_frame <= '0';\r
end if;\r
+ end if;\r
+ end process PROC_NEW_FRAME;\r
+\r
+ PROC_FILTER_FSM: process( CLK, RESET )\r
+ begin\r
+ if ( RESET = '1' ) then\r
+ filter_current_state <= IDLE;\r
+ elsif( rising_edge(CLK) ) then\r
+ filter_current_state <= filter_next_state;\r
+ end if;\r
+ end process PROC_FILTER_FSM;\r
\r
- -- frames arrive without preamble!\r
- when REMOVE_DEST =>\r
- state <= x"3";\r
- if( remove_ctr = x"03" ) then -- counter starts with a delay that's why only 3\r
- -- destination MAC address filtering here\r
- if( (saved_dest_mac = MY_MAC_IN) or (saved_dest_mac = x"ffffffffffff") ) then -- must accept broadcasts for ARP\r
- filter_next_state <= REMOVE_SRC;\r
+ PROC_FILTER_TRANSITIONS : process( filter_current_state, saved_frame_type, LINK_OK_IN, saved_proto, MY_MAC_IN,\r
+ saved_dest_mac, remove_ctr, new_frame, MAC_RX_EOF_IN, frame_type_valid, ALLOW_RX_IN)\r
+ begin\r
+ set_proto_x <= (others => '0');\r
+\r
+ case filter_current_state is\r
+\r
+ when IDLE =>\r
+ state <= x"1";\r
+ if( (new_frame = '1') and (ALLOW_RX_IN = '1') and (LINK_OK_IN = '1') ) then\r
+ filter_next_state <= REMOVE_DEST;\r
else\r
- filter_next_state <= DECIDE;\r
+ filter_next_state <= IDLE;\r
end if;\r
- else\r
- filter_next_state <= REMOVE_DEST;\r
- end if;\r
\r
- when REMOVE_SRC =>\r
- state <= x"4";\r
- if( remove_ctr = x"09" ) then\r
- filter_next_state <= REMOVE_TYPE;\r
- else\r
- filter_next_state <= REMOVE_SRC;\r
- end if;\r
-\r
- when REMOVE_TYPE =>\r
- state <= x"5";\r
- if( remove_ctr = x"0b" ) then\r
- if( saved_frame_type = x"8100" ) then -- VLAN tagged frame\r
- filter_next_state <= REMOVE_VID;\r
- else -- no VLAN tag\r
- if( saved_frame_type = x"0800" ) then -- in case of IP continue removing headers\r
- filter_next_state <= REMOVE_IP;\r
+ -- frames arrive without preamble!\r
+ when REMOVE_DEST =>\r
+ state <= x"3";\r
+ if( remove_ctr = x"03" ) then -- counter starts with a delay that's why only 3\r
+ -- destination MAC address filtering here\r
+ if( (saved_dest_mac = MY_MAC_IN) or (saved_dest_mac = x"ffffffffffff") ) then -- must accept broadcasts for ARP\r
+ filter_next_state <= REMOVE_SRC;\r
else\r
- filter_next_state <= DECIDE;\r
+ filter_next_state <= DROP_FRAME; -- wrong MAC, were are done\r
+ -- could be done in REMOVE_SRC to gain some clock cycles\r
end if;\r
+ else\r
+ filter_next_state <= REMOVE_DEST;\r
end if;\r
- else\r
- filter_next_state <= REMOVE_TYPE;\r
- end if;\r
-\r
- when REMOVE_VID =>\r
- state <= x"a";\r
- if( remove_ctr = x"0d" ) then\r
- filter_next_state <= REMOVE_VTYPE;\r
- else\r
- filter_next_state <= REMOVE_VID;\r
- end if;\r
\r
- when REMOVE_VTYPE =>\r
- state <= x"b";\r
- if( remove_ctr = x"0f" ) then\r
- if( saved_frame_type = x"0800" ) then -- in case of IP continue removing headers\r
- filter_next_state <= REMOVE_IP;\r
+ when REMOVE_SRC =>\r
+ state <= x"4";\r
+ if( remove_ctr = x"09" ) then\r
+ filter_next_state <= REMOVE_TYPE;\r
else\r
- filter_next_state <= DECIDE;\r
+ filter_next_state <= REMOVE_SRC;\r
end if;\r
- else\r
- filter_next_state <= REMOVE_VTYPE;\r
- end if;\r
\r
- when REMOVE_IP =>\r
- state <= x"c";\r
- if( remove_ctr = x"11" ) then\r
- if( saved_proto = x"11" ) then -- forced to recognize udp only, TODO check all protocols\r
- filter_next_state <= REMOVE_UDP;\r
+ when REMOVE_TYPE =>\r
+ state <= x"5";\r
+ if( remove_ctr = x"0b" ) then\r
+ case saved_frame_type is \r
+ when x"0800" =>\r
+ -- IPv4 frame, to be investigated\r
+ filter_next_state <= REMOVE_IP;\r
+ when x"0806" =>\r
+ -- ARP frame, to be stored\r
+ filter_next_state <= DELAY;\r
+ set_proto_x(0) <= '1';\r
+ -- NB: first two bytes of ARP frame are dropped silently\r
+ when others =>\r
+ filter_next_state <= DROP_FRAME;\r
+ end case;\r
else\r
- filter_next_state <= DECIDE; -- changed from drop\r
+ filter_next_state <= REMOVE_TYPE;\r
end if;\r
- else\r
- filter_next_state <= REMOVE_IP;\r
- end if;\r
\r
- when REMOVE_UDP =>\r
- state <= x"d";\r
- if( remove_ctr = x"19" ) then\r
- filter_next_state <= DECIDE;\r
- else\r
- filter_next_state <= REMOVE_UDP;\r
- end if;\r
+ when REMOVE_IP =>\r
+ state <= x"c";\r
+ if( remove_ctr = x"11" ) then\r
+ -- BUG: add check for 0x45 (IP version, header length) here.\r
+ -- Drop frames which do not comply with this!\r
+ case saved_proto is\r
+ when x"11" =>\r
+ -- UDP, to be investigated\r
+ filter_next_state <= REMOVE_UDP;\r
+ when x"01" =>\r
+ -- ICMP, to be stored \r
+ filter_next_state <= DELAY;\r
+ set_proto_x(4) <= '1';\r
+ when others =>\r
+ filter_next_state <= DROP_FRAME;\r
+ end case;\r
+ else\r
+ filter_next_state <= REMOVE_IP;\r
+ end if;\r
\r
- when DECIDE =>\r
- state <= x"6";\r
- if ( frame_type_valid = '1' ) then\r
- filter_next_state <= SAVE_FRAME;\r
- elsif( saved_frame_type = x"0806" ) then\r
- -- ARP?\r
- filter_next_state <= SAVE_FRAME;\r
- else\r
- filter_next_state <= DROP_FRAME;\r
- end if;\r
+ when REMOVE_UDP =>\r
+ state <= x"d";\r
+ if( remove_ctr = x"19" ) then\r
+ case saved_dest_udp is\r
+ when x"0044" =>\r
+ -- DHCP frame, to be stored\r
+ filter_next_state <= DELAY;\r
+ set_proto_x(1) <= '1';\r
+ when x"6590" =>\r
+ -- SCTRL frame, to be stored\r
+ filter_next_state <= DELAY;\r
+ set_proto_x(2) <= '1';\r
+ when others =>\r
+ filter_next_state <= DROP_FRAME;\r
+ end case;\r
+ else\r
+ filter_next_state <= REMOVE_UDP;\r
+ end if;\r
\r
- when SAVE_FRAME =>\r
- state <= x"7";\r
- if( MAC_RX_EOF_IN = '1' ) then\r
- filter_next_state <= CLEANUP;\r
- else\r
+ when DELAY =>\r
+ state <= x"6";\r
filter_next_state <= SAVE_FRAME;\r
- end if;\r
\r
- when DROP_FRAME =>\r
- state <= x"8";\r
- if( MAC_RX_EOF_IN = '1' ) then\r
- filter_next_state <= CLEANUP;\r
- else\r
- filter_next_state <= DROP_FRAME;\r
- end if;\r
-\r
- when CLEANUP =>\r
- state <= x"9";\r
- filter_next_state <= IDLE;\r
-\r
- when others => null;\r
+ when SAVE_FRAME =>\r
+ state <= x"7";\r
+ if( MAC_RX_EOF_IN = '1' ) then\r
+ filter_next_state <= CLEANUP;\r
+ else\r
+ filter_next_state <= SAVE_FRAME;\r
+ end if;\r
\r
- end case;\r
-end process THE_FILTER_MACHINE;\r
+ when DROP_FRAME =>\r
+ state <= x"8";\r
+ if( MAC_RX_EOF_IN = '1' ) then\r
+ filter_next_state <= CLEANUP;\r
+ else\r
+ filter_next_state <= DROP_FRAME;\r
+ end if;\r
\r
--- counts the bytes to be removed from the ethernet headers fields\r
-REMOVE_CTR_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( (filter_current_state = IDLE) or\r
- ((filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0f")) or\r
- ((filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0b") and (saved_frame_type /= x"8100")) ) then\r
- remove_ctr <= (others => '1');\r
- elsif( (MAC_RX_EN_IN = '1') and (filter_current_state /= IDLE) ) then\r
- remove_ctr <= remove_ctr + 1;\r
- end if;\r
- end if;\r
-end process REMOVE_CTR_PROC;\r
+ when CLEANUP =>\r
+ state <= x"9";\r
+ filter_next_state <= IDLE;\r
\r
-THE_SAVED_PROTO_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( filter_current_state = CLEANUP ) then\r
- saved_proto <= (others => '0');\r
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"07") ) then\r
- saved_proto <= MAC_RXD_IN;\r
+ when others => null;\r
+\r
+ end case;\r
+ end process PROC_FILTER_TRANSITIONS;\r
+\r
+ -- determine the protocol handler for later usage\r
+ -- ARP\r
+ proto_select_x(0) <= '1' when ( (saved_frame_type = x"0806") ) else '0';\r
+ -- DHCP\r
+ proto_select_x(1) <= '1' when ( (saved_frame_type = x"0800") and (saved_proto = x"11") and (saved_dest_udp = x"0044") ) else '0';\r
+ -- SCTRL\r
+ proto_select_x(2) <= '1' when ( (saved_frame_type = x"0800") and (saved_proto = x"11") and (saved_dest_udp = x"6590") ) else '0';\r
+ -- ???\r
+ proto_select_x(3) <= '0';\r
+ -- ICMP\r
+ proto_select_x(4) <= '1' when ( (saved_frame_type = x"0800") and (saved_proto = x"01") ) else '0';\r
+ -- FWD???\r
+ proto_select_x(5) <= '0';\r
+ -- TO BE INCLUDED INTO FSM!!!\r
+\r
+ -- protocol selection\r
+ PROC_PROTO_SEL: process( CLK, RESET )\r
+ begin\r
+ if ( RESET = '1' ) then\r
+ proto_select <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ for I in c_MAX_PROTOCOLS - 1 downto 0 loop\r
+ if ( set_proto_x(I) = '1' ) then\r
+ proto_select(I) <= '1';\r
+ elsif( filter_current_state = CLEANUP ) then\r
+ proto_select(I) <= '0';\r
+ end if;\r
+ end loop;\r
end if;\r
+ end process PROC_PROTO_SEL;\r
+\r
+ -- counts the bytes to be removed from the ethernet headers fields\r
+ PROC_REMOVE_CTR: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( (filter_current_state = IDLE) or\r
+ ((filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0b")) ) then\r
+ remove_ctr <= (others => '1');\r
+ elsif( (MAC_RX_EN_IN = '1') and (filter_current_state /= IDLE) ) then\r
+ remove_ctr <= remove_ctr + 1;\r
+ end if;\r
end if;\r
-end process THE_SAVED_PROTO_PROC;\r
-\r
--- saves the destination mac address of the incoming frame\r
-THE_SAVED_DEST_MAC_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( filter_current_state = CLEANUP ) then\r
- saved_dest_mac <= (others => '0');\r
- elsif( (filter_current_state = IDLE) and (MAC_RX_EN_IN = '1') and (new_frame = '0') ) then\r
- saved_dest_mac(7 downto 0) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = IDLE) and (new_frame = '1') and (ALLOW_RX_IN = '1') ) then\r
- saved_dest_mac(15 downto 8) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"FF") ) then\r
- saved_dest_mac(23 downto 16) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"00") ) then\r
- saved_dest_mac(31 downto 24) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"01") ) then\r
- saved_dest_mac(39 downto 32) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"02") ) then\r
- saved_dest_mac(47 downto 40) <= MAC_RXD_IN;\r
+ end process PROC_REMOVE_CTR;\r
+\r
+ -- saves the IP protocol\r
+ PROC_SAVED_PROTO: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_proto <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"07") ) then\r
+ saved_proto <= MAC_RXD_IN;\r
+ end if;\r
end if;\r
- end if;\r
-end process THE_SAVED_DEST_MAC_PROC;\r
-\r
--- saves the source mac address of the incoming frame\r
-THE_SAVED_SRC_MAC_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( filter_current_state = CLEANUP ) then\r
- saved_src_mac <= (others => '0');\r
- elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"03") )then\r
- saved_src_mac(7 downto 0) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"04") ) then\r
- saved_src_mac(15 downto 8) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"05") ) then\r
- saved_src_mac(23 downto 16) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"06") ) then\r
- saved_src_mac(31 downto 24) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"07") ) then\r
- saved_src_mac(39 downto 32) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"08") ) then\r
- saved_src_mac(47 downto 40) <= MAC_RXD_IN;\r
+ end process PROC_SAVED_PROTO;\r
+\r
+ -- saves the destination mac address of the incoming frame\r
+ PROC_SAVED_DEST_MAC: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_dest_mac <= (others => '0');\r
+ elsif( (filter_current_state = IDLE) and (MAC_RX_EN_IN = '1') and (new_frame = '0') ) then\r
+ saved_dest_mac(7 downto 0) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = IDLE) and (new_frame = '1') and (ALLOW_RX_IN = '1') ) then\r
+ saved_dest_mac(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"FF") ) then\r
+ saved_dest_mac(23 downto 16) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"00") ) then\r
+ saved_dest_mac(31 downto 24) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"01") ) then\r
+ saved_dest_mac(39 downto 32) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"02") ) then\r
+ saved_dest_mac(47 downto 40) <= MAC_RXD_IN;\r
+ end if;\r
end if;\r
- end if;\r
-end process THE_SAVED_SRC_MAC_PROC;\r
-\r
--- saves the frame type of the incoming frame for futher check\r
-THE_SAVED_FRAME_TYPE_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( filter_current_state = CLEANUP ) then\r
- saved_frame_type <= (others => '0');\r
- elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"09") ) then\r
- saved_frame_type(15 downto 8) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0a") ) then\r
- saved_frame_type(7 downto 0) <= MAC_RXD_IN;\r
- -- two more cases for VLAN tagged frame\r
- elsif( (filter_current_state = REMOVE_VID) and (remove_ctr = x"0d") ) then\r
- saved_frame_type(15 downto 8) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0e") ) then\r
- saved_frame_type(7 downto 0) <= MAC_RXD_IN;\r
+ end process PROC_SAVED_DEST_MAC;\r
+\r
+ -- saves the source mac address of the incoming frame\r
+ PROC_SAVED_SRC_MAC: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_src_mac <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_DEST) and (remove_ctr = x"03") )then\r
+ saved_src_mac(7 downto 0) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"04") ) then\r
+ saved_src_mac(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"05") ) then\r
+ saved_src_mac(23 downto 16) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"06") ) then\r
+ saved_src_mac(31 downto 24) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"07") ) then\r
+ saved_src_mac(39 downto 32) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"08") ) then\r
+ saved_src_mac(47 downto 40) <= MAC_RXD_IN;\r
+ end if;\r
end if;\r
- end if;\r
-end process THE_SAVED_FRAME_TYPE_PROC;\r
-\r
-THE_SAVED_SRC_IP_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( filter_current_state = CLEANUP ) then\r
- saved_src_ip <= (others => '0');\r
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0a") ) then\r
- saved_src_ip(7 downto 0) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0b") ) then\r
- saved_src_ip(15 downto 8) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0c") ) then\r
- saved_src_ip(23 downto 16) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0d") ) then\r
- saved_src_ip(31 downto 24) <= MAC_RXD_IN;\r
+ end process PROC_SAVED_SRC_MAC;\r
+\r
+ -- saves the frame type of the incoming frame for futher check\r
+ PROC_SAVED_FRAME_TYPE: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_frame_type <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_SRC) and (remove_ctr = x"09") ) then\r
+ saved_frame_type(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0a") ) then\r
+ saved_frame_type(7 downto 0) <= MAC_RXD_IN;\r
+ end if;\r
end if;\r
- end if;\r
-end process THE_SAVED_SRC_IP_PROC;\r
-\r
-THE_SAVED_DEST_IP_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( filter_current_state = CLEANUP ) then\r
- saved_dest_ip <= (others => '0');\r
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0e") ) then\r
- saved_dest_ip(7 downto 0) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0f") ) then\r
- saved_dest_ip(15 downto 8) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"10") ) then\r
- saved_dest_ip(23 downto 16) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"11") ) then\r
- saved_dest_ip(31 downto 24) <= MAC_RXD_IN;\r
+ end process PROC_SAVED_FRAME_TYPE;\r
+\r
+ PROC_SAVED_SRC_IP: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_src_ip <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0a") ) then\r
+ saved_src_ip(7 downto 0) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0b") ) then\r
+ saved_src_ip(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0c") ) then\r
+ saved_src_ip(23 downto 16) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0d") ) then\r
+ saved_src_ip(31 downto 24) <= MAC_RXD_IN;\r
+ end if;\r
end if;\r
- end if;\r
-end process THE_SAVED_DEST_IP_PROC;\r
-\r
-THE_SAVED_SRC_UDP_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( filter_current_state = CLEANUP ) then\r
- saved_src_udp <= (others => '0');\r
- elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"12") ) then\r
- saved_src_udp(15 downto 8) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"13") ) then\r
- saved_src_udp(7 downto 0) <= MAC_RXD_IN;\r
+ end process PROC_SAVED_SRC_IP;\r
+\r
+ PROC_SAVED_DEST_IP: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_dest_ip <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0e") ) then\r
+ saved_dest_ip(7 downto 0) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"0f") ) then\r
+ saved_dest_ip(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"10") ) then\r
+ saved_dest_ip(23 downto 16) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_IP) and (remove_ctr = x"11") ) then\r
+ saved_dest_ip(31 downto 24) <= MAC_RXD_IN;\r
+ end if;\r
end if;\r
- end if;\r
-end process THE_SAVED_SRC_UDP_PROC;\r
-\r
-THE_SAVED_DEST_UDP_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( filter_current_state = CLEANUP ) then\r
- saved_dest_udp <= (others => '0');\r
- elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"14") ) then\r
- saved_dest_udp(15 downto 8) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"15") ) then\r
- saved_dest_udp(7 downto 0) <= MAC_RXD_IN;\r
+ end process PROC_SAVED_DEST_IP;\r
+\r
+ PROC_SAVED_SRC_UDP: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_src_udp <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"12") ) then\r
+ saved_src_udp(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"13") ) then\r
+ saved_src_udp(7 downto 0) <= MAC_RXD_IN;\r
+ end if;\r
end if;\r
- end if;\r
-end process THE_SAVED_DEST_UDP_PROC;\r
+ end process PROC_SAVED_SRC_UDP;\r
+\r
+ PROC_SAVED_DEST_UDP: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if ( filter_current_state = CLEANUP ) then\r
+ saved_dest_udp <= (others => '0');\r
+ elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"14") ) then\r
+ saved_dest_udp(15 downto 8) <= MAC_RXD_IN;\r
+ elsif( (filter_current_state = REMOVE_UDP) and (remove_ctr = x"15") ) then\r
+ saved_dest_udp(7 downto 0) <= MAC_RXD_IN;\r
+ end if;\r
+ end if;\r
+ end process PROC_SAVED_DEST_UDP;\r
\r
--- saves VLAN id when tagged frame spotted\r
-THE_SAVED_VID_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if ( filter_current_state = CLEANUP ) then\r
- saved_vid <= (others => '0');\r
- elsif( (filter_current_state = REMOVE_TYPE) and (remove_ctr = x"0b") and (saved_frame_type = x"8100") ) then\r
- saved_vid(15 downto 8) <= MAC_RXD_IN;\r
- elsif( (filter_current_state = REMOVE_VID) and (remove_ctr = x"0c") ) then\r
- saved_vid(7 downto 0) <= MAC_RXD_IN;\r
+ PROC_FRAME_TYPE_VALID: process( CLK, RESET ) \r
+ begin\r
+ if ( RESET = '1' ) then\r
+ frame_type_valid <= '0';\r
+ elsif( rising_edge(CLK) ) then\r
+ if ( filter_current_state = SAVE_FRAME ) then\r
+ frame_type_valid <= '1';\r
+ elsif( filter_current_state = CLEANUP ) then\r
+ frame_type_valid <= '0';\r
+ end if;\r
end if;\r
- end if;\r
-end process THE_SAVED_VID_PROC;\r
-\r
-THE_TYPE_VALIDATOR: entity gbe_type_validator\r
-port map(\r
- CLK => CLK,\r
- RESET => RESET,\r
- FRAME_TYPE_IN => saved_frame_type,\r
- ALLOWED_TYPES_IN => FR_ALLOWED_TYPES_IN,\r
- SAVED_VLAN_ID_IN => saved_vid,\r
- VLAN_ID_IN => FR_VLAN_ID_IN,\r
- -- IP level\r
- IP_PROTOCOLS_IN => saved_proto,\r
- ALLOWED_IP_PROTOCOLS_IN => FR_ALLOWED_IP_IN,\r
- -- UDP level\r
- UDP_PROTOCOL_IN => saved_dest_udp,\r
- ALLOWED_UDP_PROTOCOLS_IN => FR_ALLOWED_UDP_IN,\r
- --\r
- VALID_OUT => frame_type_valid\r
-);\r
-\r
-THE_RECEIVE_FIFO: entity fifo_4096x9\r
-port map(\r
- Data => rx_data,\r
- WrClock => CLK,\r
- RdClock => CLK,\r
- WrEn => fifo_wr_en,\r
- RdEn => FR_RD_EN_IN,\r
- Reset => RESET,\r
- RPReset => RESET,\r
- Q => fr_q,\r
- Empty => rec_fifo_empty,\r
- Full => rec_fifo_full\r
-);\r
-\r
--- killer ping\r
-THE_KILLER_PING_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if( (filter_current_state = SAVE_FRAME) and \r
- (saved_proto = x"01") and \r
- (saved_frame_type = x"0800") and\r
- (rx_bytes_ctr = x"001A") and \r
- (rx_data(7 downto 0) = MY_TRBNET_ADDRESS_IN(7 downto 0)) and\r
- (MAC_RXD_IN = MY_TRBNET_ADDRESS_IN(15 downto 8)) ) then\r
- ISSUE_REBOOT_OUT <= '1';\r
- else\r
- ISSUE_REBOOT_OUT <= '0';\r
+ end process PROC_FRAME_TYPE_VALID;\r
+\r
+ THE_RECEIVE_FIFO: entity work.fifo_4096x9\r
+ port map(\r
+ Data => rx_data,\r
+ WrClock => CLK,\r
+ RdClock => CLK,\r
+ WrEn => fifo_wr_en,\r
+ RdEn => FR_RD_EN_IN,\r
+ Reset => RESET,\r
+ RPReset => RESET,\r
+ Q => fr_q,\r
+ Empty => rec_fifo_empty,\r
+ Full => rec_fifo_full\r
+ );\r
+\r
+ -- killer ping\r
+ PROC_KILLER_PING: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if( (filter_current_state = SAVE_FRAME) and \r
+ (saved_proto = x"01") and \r
+ (saved_frame_type = x"0800") and\r
+ (rx_bytes_ctr = x"001A") and \r
+ (rx_data(7 downto 0) = MY_TRBNET_ADDRESS_IN(7 downto 0)) and\r
+ (MAC_RXD_IN = MY_TRBNET_ADDRESS_IN(15 downto 8)) ) then\r
+ ISSUE_REBOOT_OUT <= '1';\r
+ else\r
+ ISSUE_REBOOT_OUT <= '0';\r
+ end if;\r
end if;\r
- end if;\r
-end process THE_KILLER_PING_PROC;\r
-\r
-THE_SECRET_FRAME_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if( (filter_current_state = DECIDE) and \r
- (saved_proto = x"11") and \r
- (saved_frame_type = x"0800") and\r
- (saved_dest_udp = x"d903") and \r
- (saved_src_udp = x"2b67") ) then\r
- oob_write <= '1';\r
- else\r
- oob_write <= '0';\r
+ end process PROC_KILLER_PING;\r
+\r
+ PROC_SECRET_FRAME: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if( (filter_current_state = DELAY) and \r
+ (saved_proto = x"11") and \r
+ (saved_frame_type = x"0800") and\r
+ (saved_dest_udp = x"d903") and \r
+ (saved_src_udp = x"2b67") ) then\r
+ oob_write <= '1';\r
+ else\r
+ oob_write <= '0';\r
+ end if;\r
end if;\r
- end if;\r
-end process THE_SECRET_FRAME_PROC;\r
-\r
-THE_REGISTERS_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if( oob_write = '1' ) then\r
- case saved_src_ip(1 downto 0) is\r
- when b"00" => oob_register_0_int <= saved_dest_ip;\r
- when b"01" => oob_register_1_int <= saved_dest_ip;\r
- when b"10" => oob_register_2_int <= saved_dest_ip;\r
- when others => oob_register_3_int <= saved_dest_ip;\r
- end case;\r
+ end process PROC_SECRET_FRAME;\r
+\r
+ PROC_SECRET_REGISTERS: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if( oob_write = '1' ) then\r
+ case saved_src_ip(1 downto 0) is\r
+ when b"00" => oob_register_0_int <= saved_dest_ip;\r
+ when b"01" => oob_register_1_int <= saved_dest_ip;\r
+ when b"10" => oob_register_2_int <= saved_dest_ip;\r
+ when others => oob_register_3_int <= saved_dest_ip;\r
+ end case;\r
+ end if;\r
end if;\r
- end if;\r
-end process THE_REGISTERS_PROC;\r
+ end process PROC_SECRET_REGISTERS;\r
\r
-OOB_REGISTER_0_OUT <= oob_register_0_int;\r
-OOB_REGISTER_1_OUT <= oob_register_1_int;\r
-OOB_REGISTER_2_OUT <= oob_register_2_int;\r
-OOB_REGISTER_3_OUT <= oob_register_3_int;\r
+ OOB_REGISTER_0_OUT <= oob_register_0_int;\r
+ OOB_REGISTER_1_OUT <= oob_register_1_int;\r
+ OOB_REGISTER_2_OUT <= oob_register_2_int;\r
+ OOB_REGISTER_3_OUT <= oob_register_3_int;\r
\r
-THE_RX_FIFO_SYNC: process( CLK )\r
-begin\r
- if rising_edge(CLK) then\r
+ PROC_RX_FIFO_SYNC: process( CLK )\r
+ begin\r
+ if rising_edge(CLK) then\r
\r
- rx_data(8) <= MAC_RX_EOF_IN;\r
- rx_data(7 downto 0) <= MAC_RXD_IN;\r
+ rx_data(8) <= MAC_RX_EOF_IN;\r
+ rx_data(7 downto 0) <= MAC_RXD_IN;\r
\r
- if( MAC_RX_EN_IN = '1' ) then\r
- if ( filter_current_state = SAVE_FRAME ) then\r
- fifo_wr_en <= '1';\r
--- elsif( (filter_current_state = REMOVE_VTYPE) and (remove_ctr = x"0f") ) then\r
--- fifo_wr_en <= '1';\r
- elsif( (filter_current_state = DECIDE) and (frame_type_valid = '1') ) then\r
- fifo_wr_en <= '1';\r
+ if( MAC_RX_EN_IN = '1' ) then\r
+ if ( filter_current_state = SAVE_FRAME ) then\r
+ fifo_wr_en <= '1';\r
+ elsif( (filter_current_state = DELAY) ) then\r
+ fifo_wr_en <= '1';\r
+ else\r
+ fifo_wr_en <= '0';\r
+ end if;\r
else\r
fifo_wr_en <= '0';\r
end if;\r
- else\r
- fifo_wr_en <= '0';\r
- end if;\r
-\r
- end if;\r
-end process THE_RX_FIFO_SYNC;\r
-\r
-THE_SIZES_FIFO: entity fifo_512x32\r
-port map(\r
- Data(15 downto 0) => rx_bytes_ctr,\r
- Data(31 downto 16) => saved_frame_type,\r
- WrClock => CLK,\r
- RdClock => CLK,\r
- WrEn => frame_valid_q,\r
- RdEn => FR_GET_FRAME_IN,\r
- Reset => RESET,\r
- RPReset => RESET,\r
- Q(15 downto 0) => fr_frame_size,\r
- Q(31 downto 16) => fr_frame_proto,\r
- Empty => sizes_fifo_empty,\r
- Full => sizes_fifo_full\r
-);\r
-\r
-THE_MACS_FIFO: entity fifo_512x72\r
-port map(\r
- Data(47 downto 0) => saved_src_mac,\r
- Data(63 downto 48) => saved_src_udp,\r
- Data(71 downto 64) => (others => '0'),\r
- WrClock => CLK,\r
- RdClock => CLK,\r
- WrEn => frame_valid_q,\r
- RdEn => FR_GET_FRAME_IN,\r
- Reset => RESET,\r
- RPReset => RESET,\r
- Q(47 downto 0) => fr_src_mac,\r
- Q(63 downto 48) => fr_src_udp,\r
- Q(71 downto 64) => xxx0, --open,\r
- Empty => open,\r
- Full => open\r
-);\r
-\r
-THE_MACD_FIFO: entity fifo_512x72\r
-port map(\r
- Data(47 downto 0) => saved_dest_mac,\r
- Data(63 downto 48) => saved_dest_udp,\r
- Data(71 downto 64) => (others => '0'),\r
- WrClock => CLK,\r
- RdClock => CLK,\r
- WrEn => frame_valid_q,\r
- RdEn => FR_GET_FRAME_IN,\r
- Reset => RESET,\r
- RPReset => RESET,\r
- Q(47 downto 0) => fr_dest_mac,\r
- Q(63 downto 48) => fr_dest_udp,\r
- Q(71 downto 64) => xxx1, --open,\r
- Empty => open,\r
- Full => open\r
-);\r
-\r
-THE_IP_FIFO: entity fifo_512x72\r
-port map(\r
- Data(31 downto 0) => saved_src_ip,\r
- Data(63 downto 32) => saved_dest_ip,\r
- Data(71 downto 64) => saved_proto,\r
- WrClock => CLK,\r
- RdClock => CLK,\r
- WrEn => frame_valid_q,\r
- RdEn => FR_GET_FRAME_IN,\r
- Reset => RESET,\r
- RPReset => RESET,\r
- Q(31 downto 0) => fr_src_ip,\r
- Q(63 downto 32) => fr_dest_ip,\r
- Q(71 downto 64) => fr_ip_proto,\r
- Empty => open,\r
- Full => open\r
-);\r
-\r
-THE_SYNC_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- FR_SRC_IP_ADDRESS_OUT <= fr_src_ip;\r
- FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip;\r
- FR_IP_PROTOCOL_OUT <= fr_ip_proto;\r
- FR_DEST_UDP_PORT_OUT <= fr_dest_udp;\r
- FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac;\r
- FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac;\r
- FR_SRC_UDP_PORT_OUT <= fr_src_udp;\r
- FR_FRAME_PROTO_OUT <= fr_frame_proto;\r
- FR_FRAME_SIZE_OUT <= fr_frame_size;\r
- FR_Q_OUT <= fr_q;\r
- --\r
- delayed_frame_valid <= MAC_RX_EOF_IN;\r
- delayed_frame_valid_q <= delayed_frame_valid;\r
- end if;\r
-end process THE_SYNC_PROC;\r
\r
-THE_FRAME_VALID_PROC: process( CLK )\r
-begin\r
- if( rising_edge(CLK) ) then\r
- if( (MAC_RX_EOF_IN = '1') and (ALLOW_RX_IN = '1') and (frame_type_valid = '1') ) then\r
- frame_valid_q <= '1';\r
- else\r
- frame_valid_q <= '0';\r
end if;\r
- end if;\r
-end process THE_FRAME_VALID_PROC;\r
+ end process PROC_RX_FIFO_SYNC;\r
+\r
+ THE_SIZES_FIFO: entity work.fifo_512x32\r
+ port map(\r
+ Data(15 downto 0) => rx_bytes_ctr,\r
+ Data(31 downto 16) => saved_frame_type,\r
+ WrClock => CLK,\r
+ RdClock => CLK,\r
+ WrEn => frame_valid_q,\r
+ RdEn => FR_GET_FRAME_IN,\r
+ Reset => RESET,\r
+ RPReset => RESET,\r
+ Q(15 downto 0) => fr_frame_size,\r
+ Q(31 downto 16) => fr_frame_proto,\r
+ Empty => sizes_fifo_empty,\r
+ Full => sizes_fifo_full\r
+ );\r
+\r
+ THE_MACS_FIFO: entity work.fifo_512x72\r
+ port map(\r
+ Data(47 downto 0) => saved_src_mac,\r
+ Data(63 downto 48) => saved_src_udp,\r
+ Data(71 downto 64) => (others => '0'),\r
+ WrClock => CLK,\r
+ RdClock => CLK,\r
+ WrEn => frame_valid_q,\r
+ RdEn => FR_GET_FRAME_IN,\r
+ Reset => RESET,\r
+ RPReset => RESET,\r
+ Q(47 downto 0) => fr_src_mac,\r
+ Q(63 downto 48) => fr_src_udp,\r
+ Q(71 downto 64) => xxx0, --open,\r
+ Empty => open,\r
+ Full => open\r
+ );\r
+\r
+ THE_MACD_FIFO: entity work.fifo_512x72\r
+ port map(\r
+ Data(47 downto 0) => saved_dest_mac,\r
+ Data(63 downto 48) => saved_dest_udp,\r
+-- Data(71 downto 64) => (others => '0'),\r
+ Data(69 downto 64) => proto_select,\r
+ Data(71 downto 70) => (others => '0'),\r
+ WrClock => CLK,\r
+ RdClock => CLK,\r
+ WrEn => frame_valid_q,\r
+ RdEn => FR_GET_FRAME_IN,\r
+ Reset => RESET,\r
+ RPReset => RESET,\r
+ Q(47 downto 0) => fr_dest_mac,\r
+ Q(63 downto 48) => fr_dest_udp,\r
+-- Q(71 downto 64) => xxx1, --open,\r
+ Q(69 downto 64) => fr_ps, --open,\r
+ Q(71 downto 70) => xxx1(1 downto 0), --open,\r
+ Empty => open,\r
+ Full => open\r
+ );\r
+\r
+ THE_IP_FIFO: entity work.fifo_512x72\r
+ port map(\r
+ Data(31 downto 0) => saved_src_ip,\r
+ Data(63 downto 32) => saved_dest_ip,\r
+ Data(71 downto 64) => saved_proto,\r
+ WrClock => CLK,\r
+ RdClock => CLK,\r
+ WrEn => frame_valid_q,\r
+ RdEn => FR_GET_FRAME_IN,\r
+ Reset => RESET,\r
+ RPReset => RESET,\r
+ Q(31 downto 0) => fr_src_ip,\r
+ Q(63 downto 32) => fr_dest_ip,\r
+ Q(71 downto 64) => fr_ip_proto,\r
+ Empty => open,\r
+ Full => open\r
+ );\r
+\r
+ PROC_SYNC: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ FR_SRC_IP_ADDRESS_OUT <= fr_src_ip;\r
+ FR_DEST_IP_ADDRESS_OUT <= fr_dest_ip;\r
+ FR_IP_PROTOCOL_OUT <= fr_ip_proto;\r
+ FR_DEST_UDP_PORT_OUT <= fr_dest_udp;\r
+ FR_DEST_MAC_ADDRESS_OUT <= fr_dest_mac;\r
+ FR_SRC_MAC_ADDRESS_OUT <= fr_src_mac;\r
+ FR_SRC_UDP_PORT_OUT <= fr_src_udp;\r
+ FR_FRAME_PROTO_OUT <= fr_frame_proto;\r
+ FR_FRAME_SIZE_OUT <= fr_frame_size;\r
+ FR_Q_OUT <= fr_q;\r
+ FR_PS_OUT <= fr_ps;\r
+ --\r
+ delayed_frame_valid <= MAC_RX_EOF_IN;\r
+ delayed_frame_valid_q <= delayed_frame_valid;\r
+-- proto_select <= proto_select_x;\r
+ end if;\r
+ end process PROC_SYNC;\r
+\r
+ -- Signal used to store auxiliary FIFO data at the end of frame\r
+ PROC_FRAME_VALID: process( CLK )\r
+ begin\r
+ if( rising_edge(CLK) ) then\r
+ if( (MAC_RX_EOF_IN = '1') and (ALLOW_RX_IN = '1') and (frame_type_valid = '1') ) then\r
+ frame_valid_q <= '1';\r
+ else\r
+ frame_valid_q <= '0';\r
+ end if;\r
+ end if;\r
+ end process PROC_FRAME_VALID;\r
\r
-THE_RX_BYTES_CTR_PROC: process( CLK, RESET )\r
-begin\r
- if ( RESET = '1' ) then\r
- rx_bytes_ctr <= x"0001";\r
- elsif( rising_edge(CLK) ) then\r
- if( delayed_frame_valid_q = '1' ) then\r
+ PROC_RX_BYTES_CTR: process( CLK, RESET )\r
+ begin\r
+ if ( RESET = '1' ) then\r
rx_bytes_ctr <= x"0001";\r
- elsif( fifo_wr_en = '1' ) then\r
- rx_bytes_ctr <= rx_bytes_ctr + 1;\r
+ elsif( rising_edge(CLK) ) then\r
+ if( delayed_frame_valid_q = '1' ) then\r
+ rx_bytes_ctr <= x"0001";\r
+ elsif( fifo_wr_en = '1' ) then\r
+ rx_bytes_ctr <= rx_bytes_ctr + 1;\r
+ end if;\r
end if;\r
- end if;\r
-end process THE_RX_BYTES_CTR_PROC;\r
-\r
-THE_ERROR_FRAMES_CTR_PROC: process( CLK, RESET )\r
-begin\r
- if ( RESET = '1' ) then\r
- error_frames_ctr <= (others => '0');\r
- elsif( rising_edge(CLK) ) then\r
- error_frames_ctr <= error_frames_ctr + 1;\r
- end if;\r
-end process THE_ERROR_FRAMES_CTR_PROC;\r
-\r
-FR_FRAME_VALID_OUT <= frame_valid_q when rising_edge(CLK);\r
-\r
-THE_RECEIVED_FRAMES_CTR: process( CLK, RESET )\r
-begin\r
- if ( RESET = '1' ) then\r
- dbg_rec_frames <= (others => '0');\r
- elsif( rising_edge(CLK) ) then\r
- dbg_rec_frames <= dbg_rec_frames + 1;\r
- end if;\r
-end process THE_RECEIVED_FRAMES_CTR;\r
-\r
-THE_DROPPED_FRAMES_CTR: process( CLK, RESET )\r
-begin\r
- if ( RESET = '1' ) then\r
- dbg_drp_frames <= (others => '0');\r
- elsif( rising_edge(CLK) ) then\r
- if( (filter_current_state = DECIDE) and (frame_type_valid = '0') ) then\r
- dbg_drp_frames <= dbg_drp_frames + 1;\r
+ end process PROC_RX_BYTES_CTR;\r
+\r
+ -- Bullshit counter. Count condition is missing.\r
+ PROC_ERROR_FRAMES_CTR: process( CLK, RESET )\r
+ begin\r
+ if ( RESET = '1' ) then\r
+ error_frames_ctr <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ error_frames_ctr <= error_frames_ctr + 1;\r
end if;\r
- end if;\r
-end process THE_DROPPED_FRAMES_CTR;\r
+ end process PROC_ERROR_FRAMES_CTR;\r
\r
-MONITOR_DROPPED_OUT <= std_logic_vector(dbg_drp_frames);\r
-MONITOR_RX_FRAMES_OUT <= std_logic_vector(dbg_rec_frames);\r
-MONITOR_RX_BYTES_OUT <= std_logic_vector(mon_rec_bytes);\r
+ FR_FRAME_VALID_OUT <= frame_valid_q when rising_edge(CLK);\r
\r
-THE_MON_REC_BYTES_PROC: process( CLK, RESET )\r
-begin\r
- if ( RESET = '1' ) then\r
- mon_rec_bytes <= (others => '0');\r
- elsif( rising_edge(CLK) ) then\r
- if( fifo_wr_en = '1' ) then\r
- mon_rec_bytes <= mon_rec_bytes + x"1";\r
+ -- Bullshit counter. Count condition is missing.\r
+ PROC_RECEIVED_FRAMES_CTR: process( CLK, RESET )\r
+ begin\r
+ if ( RESET = '1' ) then\r
+ dbg_rec_frames <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ dbg_rec_frames <= dbg_rec_frames + 1;\r
end if;\r
- end if;\r
-end process;\r
+ end process PROC_RECEIVED_FRAMES_CTR;\r
+\r
+ -- Counts dropped frames.\r
+ PROC_DROPPED_FRAMES_CTR: process( CLK, RESET )\r
+ begin\r
+ if ( RESET = '1' ) then\r
+ dbg_drp_frames <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ if( (filter_current_state = DELAY) and (frame_type_valid = '0') ) then\r
+ dbg_drp_frames <= dbg_drp_frames + 1;\r
+ end if;\r
+ end if;\r
+ end process PROC_DROPPED_FRAMES_CTR;\r
+\r
+ MONITOR_DROPPED_OUT <= std_logic_vector(dbg_drp_frames);\r
+ MONITOR_RX_FRAMES_OUT <= std_logic_vector(dbg_rec_frames);\r
+ MONITOR_RX_BYTES_OUT <= std_logic_vector(mon_rec_bytes);\r
+\r
+ -- Counts received bytes as payload.\r
+ PROC_MON_REC_BYTES: process( CLK, RESET )\r
+ begin\r
+ if ( RESET = '1' ) then\r
+ mon_rec_bytes <= (others => '0');\r
+ elsif( rising_edge(CLK) ) then\r
+ if( fifo_wr_en = '1' ) then\r
+ mon_rec_bytes <= mon_rec_bytes + x"1";\r
+ end if;\r
+ end if;\r
+ end process PROC_MON_REC_BYTES;\r
\r
end gbe_frame_receiver_arch;\r
library work;
use work.trb_net_std.all;
-use work.trb_net_components.all;
use work.gbe_protocols.all;
entity gbe_receive_control is
-port (
- CLK : in std_logic; -- system clock
- RESET : in std_logic;
--- signals to/from frame_receiver
- RC_DATA_IN : in std_logic_vector(8 downto 0);
- FR_RD_EN_OUT : out std_logic;
- FR_FRAME_VALID_IN : in std_logic;
- FR_GET_FRAME_OUT : out std_logic;
- FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
- FR_FRAME_PROTO_IN : in std_logic_vector(15 downto 0);
- FR_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
-
- FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
- FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
- FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
- -- signals to/from main controller
- RC_RD_EN_IN : in std_logic;
- RC_Q_OUT : out std_logic_vector(8 downto 0);
- RC_FRAME_WAITING_OUT : out std_logic;
- RC_LOADING_DONE_IN : in std_logic;
- RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
- RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
- RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
- RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
- RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
- -- statistics
- FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0);
- BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0);
- --
- DEBUG_OUT : out std_logic_vector(63 downto 0)
-);
+ port (
+ CLK : in std_logic; -- system clock
+ RESET : in std_logic;
+ -- signals to/from frame_receiver
+ RC_DATA_IN : in std_logic_vector(8 downto 0);
+ FR_RD_EN_OUT : out std_logic;
+ FR_FRAME_VALID_IN : in std_logic;
+ FR_GET_FRAME_OUT : out std_logic;
+ FR_FRAME_SIZE_IN : in std_logic_vector(15 downto 0);
+ FR_FRAME_PROTO_IN : in std_logic_vector(15 downto 0);
+ FR_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0);
+ FR_PS_IN : in std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ FR_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ FR_DEST_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0);
+ FR_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ FR_DEST_IP_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ FR_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ FR_DEST_UDP_PORT_IN : in std_logic_vector(15 downto 0);
+ -- signals to/from main controller
+ RC_RD_EN_IN : in std_logic;
+ RC_Q_OUT : out std_logic_vector(8 downto 0);
+ RC_FRAME_WAITING_OUT : out std_logic;
+ RC_LOADING_DONE_IN : in std_logic;
+ RC_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0);
+ RC_FRAME_PROTO_OUT : out std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ RC_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
+ RC_DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0);
+ RC_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
+ RC_DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0);
+ RC_SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
+ RC_DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0);
+ -- statistics
+ FRAMES_RECEIVED_OUT : out std_logic_vector(31 downto 0);
+ BYTES_RECEIVED_OUT : out std_logic_vector(31 downto 0);
+ --
+ DEBUG_OUT : out std_logic_vector(63 downto 0)
+ );
end gbe_receive_control;
architecture gbe_receive_control_arch of gbe_receive_control is
-attribute syn_encoding : string;
+ attribute syn_encoding : string;
-type load_states is (IDLE, PREPARE, WAIT_ONE, READY);
-signal load_current_state, load_next_state : load_states;
-attribute syn_encoding of load_current_state : signal is "onehot";
+ type load_states is (IDLE, PREPARE, WAIT_ONE, READY);
+ signal load_current_state, load_next_state : load_states;
+ attribute syn_encoding of load_current_state : signal is "onehot";
-signal frames_received_ctr : unsigned(31 downto 0);
-signal frames_readout_ctr : unsigned(31 downto 0);
-signal bytes_rec_ctr : unsigned(31 downto 0);
+ signal frames_received_ctr : unsigned(31 downto 0);
+ signal frames_readout_ctr : unsigned(31 downto 0);
+ signal bytes_rec_ctr : unsigned(31 downto 0);
-signal state : std_logic_vector(3 downto 0);
-signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
-signal reset_prioritizer : std_logic;
-signal frame_waiting : std_logic;
+ signal state : std_logic_vector(3 downto 0);
+ signal proto_code : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ signal reset_prioritizer : std_logic;
--- debug only
-signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
+ -- debug only
+ signal saved_proto : std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
begin
-FR_RD_EN_OUT <= RC_RD_EN_IN;
-RC_Q_OUT <= RC_DATA_IN;
-RC_FRAME_SIZE_OUT <= FR_FRAME_SIZE_IN;
-RC_SRC_MAC_ADDRESS_OUT <= FR_SRC_MAC_ADDRESS_IN;
-RC_DEST_MAC_ADDRESS_OUT <= FR_DEST_MAC_ADDRESS_IN;
-RC_SRC_IP_ADDRESS_OUT <= FR_SRC_IP_ADDRESS_IN;
-RC_DEST_IP_ADDRESS_OUT <= FR_DEST_IP_ADDRESS_IN;
-RC_SRC_UDP_PORT_OUT <= FR_SRC_UDP_PORT_IN;
-RC_DEST_UDP_PORT_OUT <= FR_DEST_UDP_PORT_IN;
-
-protocol_prioritizer: entity gbe_protocol_prioritizer
-port map(
- CLK => CLK,
- RESET => reset_prioritizer,
- --
- FRAME_TYPE_IN => FR_FRAME_PROTO_IN,
- PROTOCOL_CODE_IN => FR_IP_PROTOCOL_IN,
- UDP_PROTOCOL_IN => FR_DEST_UDP_PORT_IN,
- --
- CODE_OUT => proto_code
-);
-
-reset_prioritizer <= '1' when load_current_state = IDLE else '0';
-
-RC_FRAME_PROTO_OUT <= proto_code; -- no more ones as the incorrect value, last slot for Trash
-
-LOAD_MACHINE_PROC: process( CLK, RESET )
-begin
- if ( RESET = '1' ) then
- load_current_state <= IDLE;
- elsif( rising_edge(CLK) ) then
- load_current_state <= load_next_state;
- end if;
-end process LOAD_MACHINE_PROC;
-
-LOAD_MACHINE: process( load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN )
-begin
- case load_current_state is
+ FR_RD_EN_OUT <= RC_RD_EN_IN;
+ RC_Q_OUT <= RC_DATA_IN;
+ RC_FRAME_SIZE_OUT <= FR_FRAME_SIZE_IN;
+ RC_SRC_MAC_ADDRESS_OUT <= FR_SRC_MAC_ADDRESS_IN;
+ RC_DEST_MAC_ADDRESS_OUT <= FR_DEST_MAC_ADDRESS_IN;
+ RC_SRC_IP_ADDRESS_OUT <= FR_SRC_IP_ADDRESS_IN;
+ RC_DEST_IP_ADDRESS_OUT <= FR_DEST_IP_ADDRESS_IN;
+ RC_SRC_UDP_PORT_OUT <= FR_SRC_UDP_PORT_IN;
+ RC_DEST_UDP_PORT_OUT <= FR_DEST_UDP_PORT_IN;
+
+-- protocol_prioritizer: entity work.gbe_protocol_prioritizer
+-- port map(
+-- CLK => CLK,
+-- RESET => reset_prioritizer,
+-- --
+-- FRAME_TYPE_IN => FR_FRAME_PROTO_IN,
+-- PROTOCOL_CODE_IN => FR_IP_PROTOCOL_IN,
+-- UDP_PROTOCOL_IN => FR_DEST_UDP_PORT_IN,
+-- --
+-- CODE_OUT => proto_code
+-- );
+--
+-- reset_prioritizer <= '1' when load_current_state = IDLE else '0';
+--
+-- RC_FRAME_PROTO_OUT <= proto_code; -- no more ones as the incorrect value, last slot for Trash
+\r
+ RC_FRAME_PROTO_OUT <= FR_PS_IN when (load_current_state /= IDLE) else (others => '0');\r
+
+ LOAD_MACHINE_PROC: process( CLK, RESET )
+ begin
+ if ( RESET = '1' ) then
+ load_current_state <= IDLE;
+ elsif( rising_edge(CLK) ) then
+ load_current_state <= load_next_state;
+ end if;
+ end process LOAD_MACHINE_PROC;
+
+ LOAD_MACHINE: process( load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN )
+ begin
+ case load_current_state is
+
+ when IDLE =>
+ state <= x"1";
+ if( frames_readout_ctr /= frames_received_ctr ) then -- frame is still waiting in frame_receiver
+ load_next_state <= PREPARE;
+ else
+ load_next_state <= IDLE;
+ end if;
+
+ when PREPARE => -- prepare frame size
+ state <= x"2";
+ load_next_state <= WAIT_ONE;
+
+ when WAIT_ONE =>
+ load_next_state <= READY;
- when IDLE =>
- state <= x"1";
- if( frames_readout_ctr /= frames_received_ctr ) then -- frame is still waiting in frame_receiver
- load_next_state <= PREPARE;
+ when READY => -- wait for reading out the whole frame
+ state <= x"3";
+ if( RC_LOADING_DONE_IN = '1' ) then
+ load_next_state <= IDLE;
+ else
+ load_next_state <= READY;
+ end if;
+
+ end case;
+ end process LOAD_MACHINE;
+
+ process( CLK )
+ begin
+ if( rising_edge(CLK) ) then
+ if( load_current_state = PREPARE ) then
+ FR_GET_FRAME_OUT <= '1';
else
- load_next_state <= IDLE;
+ FR_GET_FRAME_OUT <= '0';
end if;
- when PREPARE => -- prepare frame size
- state <= x"2";
- load_next_state <= WAIT_ONE;
-
- when WAIT_ONE =>
- load_next_state <= READY;
-
- when READY => -- wait for reading out the whole frame
- state <= x"3";
- if( RC_LOADING_DONE_IN = '1' ) then
- load_next_state <= IDLE;
+ if( (load_current_state = READY) and (RC_LOADING_DONE_IN = '0') ) then
+ RC_FRAME_WAITING_OUT <= '1';
else
- load_next_state <= READY;
+ RC_FRAME_WAITING_OUT <= '0';
end if;
-
- end case;
-end process LOAD_MACHINE;
-
-process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if( load_current_state = PREPARE ) then
- FR_GET_FRAME_OUT <= '1';
- else
- FR_GET_FRAME_OUT <= '0';
end if;
-
- if( (load_current_state = READY) and (RC_LOADING_DONE_IN = '0') ) then
- RC_FRAME_WAITING_OUT <= '1';
- else
- RC_FRAME_WAITING_OUT <= '0';
+ end process;
+
+ FRAMES_REC_CTR_PROC: process( CLK, RESET )
+ begin
+ if ( RESET = '1' ) then
+ frames_received_ctr <= (others => '0');
+ elsif( rising_edge(CLK) ) then
+ if( FR_FRAME_VALID_IN = '1' ) then
+ frames_received_ctr <= frames_received_ctr + 1;
+ end if;
end if;
- end if;
-end process;
+ end process FRAMES_REC_CTR_PROC;
-FRAMES_REC_CTR_PROC: process( CLK, RESET )
-begin
- if ( RESET = '1' ) then
- frames_received_ctr <= (others => '0');
- elsif( rising_edge(CLK) ) then
- if( FR_FRAME_VALID_IN = '1' ) then
- frames_received_ctr <= frames_received_ctr + 1;
+ FRAMES_READOUT_CTR_PROC: process( CLK, RESET )
+ begin
+ if ( RESET = '1' ) then
+ frames_readout_ctr <= (others => '0');
+ elsif( rising_edge(CLK) ) then
+ if( RC_LOADING_DONE_IN = '1' ) then
+ frames_readout_ctr <= frames_readout_ctr + 1;
+ end if;
end if;
- end if;
-end process FRAMES_REC_CTR_PROC;
-
-FRAMES_READOUT_CTR_PROC: process( CLK, RESET )
-begin
- if ( RESET = '1' ) then
- frames_readout_ctr <= (others => '0');
- elsif( rising_edge(CLK) ) then
- if( RC_LOADING_DONE_IN = '1' ) then
- frames_readout_ctr <= frames_readout_ctr + 1;
- end if;
- end if;
-end process FRAMES_READOUT_CTR_PROC;
-
--- debug only
-BYTES_REC_CTR_PROC : process( CLK )
-begin
- if ( RESET = '1' ) then
- bytes_rec_ctr <= (others => '0');
- elsif( rising_edge(CLK) ) then
- if( FR_FRAME_VALID_IN = '1' ) then
- bytes_rec_ctr <= bytes_rec_ctr + unsigned(FR_FRAME_SIZE_IN);
+ end process FRAMES_READOUT_CTR_PROC;
+
+ -- debug only
+ BYTES_REC_CTR_PROC : process( CLK )
+ begin
+ if ( RESET = '1' ) then
+ bytes_rec_ctr <= (others => '0');
+ elsif( rising_edge(CLK) ) then
+ if( FR_FRAME_VALID_IN = '1' ) then
+ bytes_rec_ctr <= bytes_rec_ctr + unsigned(FR_FRAME_SIZE_IN);
+ end if;
end if;
- end if;
-end process BYTES_REC_CTR_PROC;
-
-SAVED_PROTO_PROC : process( CLK )
-begin
- if( rising_edge(CLK) ) then
- if( load_current_state = READY ) then
- if( and_all(proto_code) = '0' ) then
- saved_proto <= proto_code;
+ end process BYTES_REC_CTR_PROC;
+
+ SAVED_PROTO_PROC : process( CLK )
+ begin
+ if( rising_edge(CLK) ) then
+ if( load_current_state = READY ) then
+ if( and_all(proto_code) = '0' ) then
+ saved_proto <= proto_code;
+ else
+ saved_proto <= (others => '0');
+ end if;
else
- saved_proto <= (others => '0');
+ saved_proto <= saved_proto;
end if;
- else
- saved_proto <= saved_proto;
end if;
- end if;
-end process SAVED_PROTO_PROC;
+ end process SAVED_PROTO_PROC;
end gbe_receive_control_arch;
jspc29 / trbnet.git / commitdiff