end entity;\r
\r
architecture arch of thresholds is\r
+ type ram_t is array (15 downto 0) of std_logic_vector(15 downto 0);\r
+\r
signal clk_osc, clk_i : std_logic;\r
\r
signal spi_rx_data : std_logic_vector(15 downto 0);\r
signal bus_read : std_logic := '0';\r
signal bus_write : std_logic := '0';\r
signal bus_ready : std_logic; \r
- signal spi_busy : std_logic; \r
+ --signal spi_busy : std_logic; \r
\r
signal sed_error : std_logic;\r
signal sed_debug : std_logic_vector(31 downto 0);\r
signal pwm_data_i : std_logic_vector(15 downto 0);\r
signal pwm_write_i : std_logic;\r
signal pwm_addr_i : std_logic_vector(4 downto 0);\r
+ signal pwm_data_ii : std_logic_vector(15 downto 0);\r
+ signal pwm_write_ii : std_logic;\r
+ signal pwm_addr_ii : std_logic_vector(4 downto 0);\r
\r
- signal ram_write_i : std_logic;\r
- signal ram_data_i: std_logic_vector(7 downto 0);\r
- signal ram_data_o: std_logic_vector(7 downto 0);\r
- signal ram_addr_i: std_logic_vector(3 downto 0);\r
-\r
- signal flashram_addr_i : std_logic_vector(3 downto 0);\r
- signal flashram_cen_i : std_logic;\r
- signal flashram_reset : std_logic;\r
- signal flashram_write_i: std_logic;\r
+-- signal flashram_reset : std_logic;\r
+ --signal flashram_write_i: std_logic;\r
signal flashram_data_i : std_logic_vector(7 downto 0);\r
signal flashram_data_o : std_logic_vector(7 downto 0);\r
+ signal ram_data : ram_t := (others =>("0000000000000000"));--: std_logic_vector(15 downto 0);\r
+ --signal ram_data_o : ram_t := (others =>("0000000000000000"));--std_logic_vector(15 downto 0);\r
\r
- signal flash_command : std_logic_vector(2 downto 0);\r
- signal flash_page : std_logic_vector(12 downto 0);\r
+ signal flash_command : std_logic;\r
+ --signal flash_page : std_logic_vector(12 downto 0);\r
signal flash_go : std_logic;\r
signal flash_busy : std_logic;\r
signal flash_err : std_logic;\r
\r
signal compensate_i : signed(15 downto 0);\r
signal pwm_i : std_logic_vector(15 downto 0);\r
- signal dummy_register : std_logic_vector(15 downto 0);\r
+ signal ufm_bus_ready_in : std_logic;\r
+ signal ufm_bus_ready_out : std_logic;\r
+ signal ufm_databyte_counter : unsigned(14 downto 0);\r
+ \r
+ signal ram_data_f_spi_addr : std_logic_vector( 7 downto 0);\r
+ signal ram_data_f_spi_data : std_logic_vector(15 downto 0);\r
+ signal ram_data_f_spi_write : std_logic;\r
\r
+ \r
component OSCH\r
generic (NOM_FREQ: string := "33.25");\r
port (\r
- STDBY :IN std_logic;\r
- OSC :OUT std_logic;\r
- SEDSTDBY :OUT std_logic\r
+ STDBY : IN std_logic;\r
+ OSC : OUT std_logic;\r
+ SEDSTDBY : OUT std_logic\r
);\r
end component; \r
- \r
- component UFM_WB\r
- port(\r
- clk_i : in std_logic;\r
- rst_n : in std_logic;\r
- cmd : in std_logic_vector(2 downto 0);\r
- ufm_page : in std_logic_vector(12 downto 0);\r
- GO : in std_logic;\r
- BUSY : out std_logic;\r
- ERR : out std_logic;\r
- mem_clk : out std_logic;\r
- mem_we : out std_logic;\r
- mem_ce : out std_logic;\r
- mem_addr : out std_logic_vector(3 downto 0);\r
- mem_wr_data : out std_logic_vector(7 downto 0);\r
- mem_rd_data : in std_logic_vector(7 downto 0)\r
- );\r
- end component;\r
+\r
\r
begin\r
\r
-\r
-LED <= dummy_register(7 downto 0);\r
---------------------------------------------------------------------------\r
-- Clock\r
---------------------------------------------------------------------------\r
clk_i <= clk_osc; \r
\r
---------------------------------------------------------------------------\r
--- UART\r
+-- SPI\r
---------------------------------------------------------------------------\r
THE_SPI : entity work.spi_slave\r
port map(\r
- CLK => clk_i,\r
- SPI_CLK => SCLK_IN,\r
- SPI_CS => CS_IN ,\r
- SPI_IN => MOSI_IN,\r
- SPI_OUT => MISO_OUT,\r
+ CLK => clk_i,\r
+ SPI_CLK => SCLK_IN,\r
+ SPI_CS => CS_IN ,\r
+ SPI_IN => MOSI_IN,\r
+ SPI_OUT => MISO_OUT,\r
\r
DATA_OUT => spi_rx_data,\r
DATA_IN => spi_tx_data,\r
READY_IN => bus_ready,\r
\r
DEBUG => open\r
- );\r
+ );\r
\r
\r
PROC_REGS : process begin\r
wait until rising_edge(clk_i);\r
- bus_ready <= '0';\r
- pwm_write_i<= '0';\r
- if bus_read = '1' then\r
+ bus_ready <= '0';\r
+ pwm_write_i <= '0';\r
+ flash_go <= '0';\r
+ ram_data_f_spi_write <= '0';\r
+ \r
+ if pwm_write_ii = '1' then\r
+ pwm_data_i <= pwm_data_ii;\r
+ pwm_addr_i <= pwm_addr_ii;\r
+ pwm_write_i <= pwm_write_ii;\r
+ \r
+ elsif bus_read = '1' then\r
bus_ready <= '1';\r
- case spi_addr is\r
- when x"10" => uart_tx_data <= std_logic_vector(compensate_i);\r
- when x"ee" => spi_tx_data <= sed_debug(15 downto 0);\r
- when x"ef" => spi_tx_data <= sed_debug(31 downto 16);\r
- when x"e4" => spi_tx_data <= dummy_register;\r
- end case;\r
+ if spi_addr >= x"10" and spi_addr < x"20" then \r
+ spi_tx_data <= ram_data(to_integer(unsigned(spi_addr)));\r
+ else\r
+ case spi_addr is\r
+ when x"30" => spi_tx_data <= std_logic_vector(compensate_i);\r
+ when x"ee" => spi_tx_data <= sed_debug(15 downto 0);\r
+ when x"ef" => spi_tx_data <= sed_debug(31 downto 16);\r
+ when others => null;\r
+ end case;\r
+ end if;\r
+ \r
elsif bus_write = '1' then\r
- if spi_addr < x"10" then\r
- pwm_data_i <= spi_rx_data(15 downto 0);\r
- pwm_addr_i <= spi_addr(4 downto 0);\r
- pwm_write_i<= '1';\r
+ if spi_addr < x"10" then -- 0 to 15 0x00 to 0x10 -- write directly to pwm\r
+ if flash_busy = '0' or flash_command = '0' then -- avoid conflict with writing from flash\r
+ pwm_data_i <= spi_rx_data(15 downto 0);\r
+ pwm_addr_i <= spi_addr(4 downto 0);\r
+ pwm_write_i <= '1';\r
+ end if;\r
+ elsif spi_addr >= x"10" and spi_addr < x"20" then -- write to ram\r
+ --ram_data(to_integer(unsigned(spi_addr(3 downto 0)))) <= spi_rx_data; \r
+ ram_data_f_spi_write <= '1';\r
+ ram_data_f_spi_addr <= spi_addr;\r
+ ram_data_f_spi_data <= spi_rx_data;\r
else\r
- case spi_addr is\r
- when x"10" => compensate_i <= signed(uart_rx_data(15 downto 0);\r
- when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);\r
- when x"ee" => controlsed_i <= spi_rx_data(3 downto 0);\r
- when x"e4" => dummy_register <= spi_rx_data ;\r
+ case spi_addr is\r
+ -- when x"20" => flash_command <= spi_rx_data(0); --read/write to flash;\r
+ -- flash_go <= '1';\r
+ when x"30" => compensate_i <= spi_rx_data(15 downto 0);--signed(uart_rx_data(15 downto 0);\r
+ when x"ee" => controlsed_i <= spi_rx_data(3 downto 0);\r
end case;\r
end if; \r
end if;\r
)\r
port map(\r
CLK => clk_i,\r
- DATA_IN => pwm_data_i,\r
+ DATA_IN => pwm_data_i, -- 16 Bits\r
DATA_OUT => open,\r
- COMP_IN => compensate_i,\r
- WRITE_IN => pwm_write_i,\r
- ADDR_IN => pwm_addr_i,\r
- PWM => pwm_i\r
+ COMP_IN => compensate_i, -- 16 Bits\r
+ WRITE_IN => pwm_write_i, -- 16 Bits\r
+ ADDR_IN => pwm_addr_i, -- 5 Bits\r
+ PWM => pwm_i -- 16 Bits\r
); \r
\r
--TODO connect to output according to ID\r
OUTPUT <= pwm_i;\r
+\r
+ \r
\r
---------------------------------------------------------------------------\r
-- Flash Controller\r
--------------------------------------------------------------------------- \r
\r
--- THE_FLASH_RAM : entity work.flashram\r
--- port map(\r
--- DataInA => ram_data_i,\r
--- AddressA => ram_addr_i,\r
--- ClockA => clk_i, \r
--- ClockEnA => '1',\r
--- WrA => ram_write_i, \r
--- ResetA => '0',\r
--- QA => ram_data_o,\r
--- \r
--- DataInB => flashram_data_i,\r
--- AddressB => flashram_addr_i,\r
--- ClockB => clk_i,\r
--- ClockEnB => flashram_cen_i,\r
--- WrB => flashram_write_i, \r
--- ResetB => flashram_reset,\r
--- QB => flashram_data_o\r
--- );\r
--- \r
--- \r
--- \r
--- THE_FLASH : UFM_WB\r
--- port map(\r
--- clk_i => clk_i,\r
--- rst_n => '1',\r
--- cmd => flash_command,\r
--- ufm_page => flash_page,\r
--- GO => flash_go,\r
--- BUSY => flash_busy,\r
--- ERR => flash_err,\r
--- mem_clk => open,\r
--- mem_we => flashram_write_i,\r
--- mem_ce => flashram_cen_i,\r
--- mem_addr => flashram_addr_i,\r
--- mem_wr_data => flashram_data_i,\r
--- mem_rd_data => flashram_data_o\r
--- ); \r
+--THE_UFM : entity work.UFM_control\r
+-- generic map(\r
+-- NO_DATAPAGES => 2,\r
+-- UFM_STARTPAGE => "00"&x"00"\r
+-- )\r
+-- port map(\r
+-- CLK => clk_i,\r
+-- CMD => flash_command,\r
+-- GO => flash_go,\r
+-- BUSY => flash_busy,\r
+-- RESET => '0',\r
+-- DATA_IN => flashram_data_i,\r
+-- DATA_OUT => flashram_data_o,\r
+-- DATABYTE_COUNTER => ufm_databyte_counter, --specifies current databyte \r
+-- BUS_READY_IN => ufm_bus_ready_in,\r
+-- BUS_READY_OUT => ufm_bus_ready_out,\r
+-- FLASH_ERROR => flash_err\r
+-- );\r
+\r
+\r
+--PROC_REGS_FLASH: process begin\r
+--wait until rising_edge( clk_i );\r
+-- ufm_bus_ready_in <= '0';\r
+-- pwm_write_ii <= '0';\r
+-- if flash_command = '0' and ufm_bus_ready_out = '1' then\r
+-- -- copy data from UFM to registers\r
+-- ufm_bus_ready_in <= '1';\r
+-- case to_integer ( ufm_databyte_counter ) is\r
+-- when 0 => ram_data( 0)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 1 => ram_data( 0)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "00000";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 2 => ram_data( 1)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 3 => ram_data( 1)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "00001";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 4 => ram_data( 2)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 5 => ram_data( 2)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "00010";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 6 => ram_data( 3)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 7 => ram_data( 3)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "00011";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 8 => ram_data( 4)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 9 => ram_data( 4)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "00100";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 10 => ram_data( 5)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 11 => ram_data( 5)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "00101";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 12 => ram_data( 6)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 13 => ram_data( 6)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "00110";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 14 => ram_data( 7)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 15 => ram_data( 7)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "00111";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 16 => ram_data( 8)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 17 => ram_data( 8)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "01000";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 18 => ram_data( 9)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 19 => ram_data( 9)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "01001";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 20 => ram_data(10)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 21 => ram_data(10)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "01010";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 22 => ram_data(11)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 23 => ram_data(11)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "01011";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 24 => ram_data(12)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 25 => ram_data(12)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "01100";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 26 => ram_data(13)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 27 => ram_data(13)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "01101";\r
+-- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
+-- when 28 => ram_data(14)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 29 => ram_data(14)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "01110";\r
+-- pwm_data_ii(15 downto 8) <= flashram_data_o;\r
+-- when 30 => ram_data(15)( 7 downto 0) <= flashram_data_o;\r
+-- pwm_write_ii <= '0';\r
+-- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
+-- when 31 => ram_data(15)(15 downto 8) <= flashram_data_o;\r
+-- pwm_write_ii <= '1';\r
+-- pwm_addr_ii <= "01111";\r
+-- pwm_data_ii(15 downto 8) <= flashram_data_o;\r
+-- when others => null;\r
+-- end case ;\r
+-- \r
+-- elsif flash_command = '1' and ufm_bus_ready_out = '1' then\r
+-- -- save data from registers to UFM\r
+-- ufm_bus_ready_in <= '1';\r
+-- case to_integer ( ufm_databyte_counter ) is\r
+-- when 0 => flashram_data_i <= ram_data( 0)( 7 downto 0);\r
+-- when 1 => flashram_data_i <= ram_data( 0)(15 downto 8);\r
+-- when 2 => flashram_data_i <= ram_data( 1)( 7 downto 0);\r
+-- when 3 => flashram_data_i <= ram_data( 1)(15 downto 8);\r
+-- when 4 => flashram_data_i <= ram_data( 2)( 7 downto 0);\r
+-- when 5 => flashram_data_i <= ram_data( 2)(15 downto 8);\r
+-- when 6 => flashram_data_i <= ram_data( 3)( 7 downto 0);\r
+-- when 7 => flashram_data_i <= ram_data( 3)(15 downto 8);\r
+-- when 8 => flashram_data_i <= ram_data( 4)( 7 downto 0);\r
+-- when 9 => flashram_data_i <= ram_data( 4)(15 downto 8);\r
+-- when 10 => flashram_data_i <= ram_data( 5)( 7 downto 0);\r
+-- when 11 => flashram_data_i <= ram_data( 5)(15 downto 8);\r
+-- when 12 => flashram_data_i <= ram_data( 6)( 7 downto 0);\r
+-- when 13 => flashram_data_i <= ram_data( 6)(15 downto 8);\r
+-- when 14 => flashram_data_i <= ram_data( 7)( 7 downto 0);\r
+-- when 15 => flashram_data_i <= ram_data( 7)(15 downto 8);\r
+-- when 16 => flashram_data_i <= ram_data( 8)( 7 downto 0);\r
+-- when 17 => flashram_data_i <= ram_data( 8)(15 downto 8);\r
+-- when 18 => flashram_data_i <= ram_data( 9)( 7 downto 0);\r
+-- when 19 => flashram_data_i <= ram_data( 9)(15 downto 8);\r
+-- when 20 => flashram_data_i <= ram_data(10)( 7 downto 0);\r
+-- when 21 => flashram_data_i <= ram_data(10)(15 downto 8);\r
+-- when 22 => flashram_data_i <= ram_data(11)( 7 downto 0);\r
+-- when 23 => flashram_data_i <= ram_data(11)(15 downto 8);\r
+-- when 24 => flashram_data_i <= ram_data(12)( 7 downto 0);\r
+-- when 25 => flashram_data_i <= ram_data(12)(15 downto 8);\r
+-- when 26 => flashram_data_i <= ram_data(13)( 7 downto 0);\r
+-- when 27 => flashram_data_i <= ram_data(13)(15 downto 8);\r
+-- when 28 => flashram_data_i <= ram_data(14)( 7 downto 0);\r
+-- when 29 => flashram_data_i <= ram_data(14)(15 downto 8);\r
+-- when 30 => flashram_data_i <= ram_data(15)( 7 downto 0);\r
+-- when 31 => flashram_data_i <= ram_data(15)(15 downto 8);\r
+-- when others => null ;\r
+-- end case ;\r
+-- \r
+-- elsif ram_data_f_spi_write = '1' then\r
+-- ram_data(to_integer(unsigned(ram_data_f_spi_addr))) <= ram_data_f_spi_data;\r
+-- end if ;\r
+-- end process ;\r
+\r
\r
\r
end architecture;\r
\r
\r
\r
+\r
jspc29 / dirich.git / commitdiff