digital part working, IF

diff --git a/amps2/padiwa_amps2.prj b/amps2/padiwa_amps2.prj
index 1ac8a31a1478fb4054777055b7406f84431e9800..00d0b62faeda254d7e1487f6cdb71a74c69b0308 100644 (file)
--- a/amps2/padiwa_amps2.prj
+++ b/amps2/padiwa_amps2.prj
@@ -7,14 +7,14 @@
 add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.9_x64/cae_library/synthesis/vhdl/machxo3lf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "workdir/version.vhd"
-#add_file -vhdl -lib work "../source/spi_slave.vhd"
-add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave_async.vhd"
+#add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave.vhd"
 add_file -vhdl -lib work "../source/Stretcher.vhd"
 add_file -vhdl -lib work "../source/Stretcher_A.vhd"
 add_file -vhdl -lib work "../source/Stretcher_B.vhd"
 
 add_file -vhdl -lib work "../source/pwm.vhd"
-add_file -vhdl -lib work "../cores/pll_in133_out33_133_266.vhd"
+add_file -vhdl -lib work "../cores/pll_in133_out33_133_66.vhd"
 add_file -vhdl -lib work "padiwa_amps2.vhd"
 
 add_file -vhdl -lib work "../source/timer.vhd"

diff --git a/amps2/padiwa_amps2.vhd b/amps2/padiwa_amps2.vhd
index 9d40c3376f9d298871ff896a83a032e2ad6bad0e..4fabdd78970c5ab338e2e69e8c313e74bd62c0fa 100644 (file)
--- a/amps2/padiwa_amps2.vhd
+++ b/amps2/padiwa_amps2.vhd
@@ -46,16 +46,12 @@ architecture arch of padiwa_amps2 is
   attribute NOM_FREQ : string;\r
   attribute NOM_FREQ of clk_source : label is "133.00";\r
 \r
-  signal clk_i, clk_osc, clk_33,clk_266 : std_logic;\r
+  signal clk_i, clk_osc, clk_33,clk_66 : std_logic;\r
 \r
   type led_timer_t is array(1 to 8) of unsigned(24 downto 0);\r
   signal led_timer : led_timer_t;\r
   signal led_state : std_logic_vector(8 downto 1);\r
 \r
---  signal ram_write_i : std_logic;\r
---  signal ram_data_i: std_logic_vector(7 downto 0);\r
---  signal ram_data_o: std_logic_vector(7 downto 0);\r
---  signal ram_addr_i: std_logic_vector(3 downto 0);\r
   signal temperature_i : std_logic_vector(11 downto 0);\r
   signal ID_OUT : std_logic_vector(31 downto 0);\r
  \r
@@ -63,17 +59,7 @@ architecture arch of padiwa_amps2 is
   signal INP_i       : std_logic_vector(15 downto 0);\r
   signal fast_input  : std_logic_vector(8  downto 1);\r
   signal slow_input  : std_logic_vector(8  downto 1);\r
---  signal spi_reg00_i : std_logic_vector(15 downto 0);\r
---  signal spi_reg10_i : std_logic_vector(15 downto 0);\r
---  signal spi_reg20_i : std_logic_vector(15 downto 0);\r
---  signal spi_reg40_i : std_logic_vector(15 downto 0);\r
---  signal spi_data_i  : std_logic_vector(15 downto 0);\r
---  signal spi_operation_i : std_logic_vector(3 downto 0);\r
---  signal spi_channel_i   : std_logic_vector(7 downto 0);\r
---  signal spi_write_i     : std_logic_vector(15 downto 0);\r
---  signal buf_SPI_OUT     : std_logic;\r
---  signal spi_debug_i     : std_logic_vector(15 downto 0);\r
---  signal last_spi_channel: std_logic_vector(7 downto 0);\r
+\r
   signal spi_rx_data : std_logic_vector(15 downto 0);\r
   signal spi_tx_data : std_logic_vector(15 downto 0);\r
   signal spi_addr    : std_logic_vector(7 downto 0);\r
@@ -91,8 +77,6 @@ architecture arch of padiwa_amps2 is
   signal spi_ready_in  : std_logic;\r
   signal spi_busy_out  : std_logic;\r
   \r
-  \r
-\r
   signal inp_select    : integer range 0 to 31 := 0;\r
   signal inp_invert   : std_logic_vector(15 downto 0) := x"aaaa"; --invert slow inputs only\r
   signal input_enable : std_logic_vector(15 downto 0);\r
@@ -133,7 +117,6 @@ architecture arch of padiwa_amps2 is
   signal delayed_inputs   : std_logic_vector(511 downto 0);\r
   signal selected_delay   : std_logic_vector(8 downto 1);\r
   signal delayselect      : integer range 0 to 63;\r
-\r
   \r
   component OSCH\r
     generic (NOM_FREQ: string := "133.00");\r
@@ -158,12 +141,12 @@ clk_source: OSCH
     SEDSTDBY => open\r
   );\r
   \r
-THE_PLL : entity work.pll_in133_out33_133_266 \r
+THE_PLL : entity work.pll_in133_out33_133_66 \r
   port map (\r
     CLKI => clk_osc,\r
     CLKOP => clk_i, --133\r
     CLKOS => clk_33, --33 \r
-    CLKOS2=> clk_266 --266\r
+    CLKOS2=> clk_66  --66\r
   );\r
 \r
 \r
@@ -177,9 +160,10 @@ THE_PLL : entity work.pll_in133_out33_133_266
   PWM <= pwm_i(16 downto 1);\r
   \r
 \r
-  inp_status <= INP_i when rising_edge(clk_i);\r
-  last_inp <= inp_status(15 downto 0) when rising_edge(clk_i);\r
-\r
+  --inp_status <= INP_i when rising_edge(clk_i);\r
+  inp_status <= INP_i when rising_edge(clk_66);\r
+  --last_inp <= inp_status(15 downto 0) when rising_edge(clk_i);\r
+  last_inp <= inp_status(15 downto 0) when rising_edge(clk_66); \r
 \r
 ---------------------------------------------------------------------------\r
 -- SPI Interface\r
@@ -187,7 +171,9 @@ THE_PLL : entity work.pll_in133_out33_133_266
 \r
 THE_SPI : entity work.spi_slave\r
   port map(\r
-    CLK       => clk_i,\r
+    CLK_ext   => clk_i,\r
+    CLK_int   => clk_66,\r
+--    CLK   => clk_66,\r
     SPI_CLK   => SPI_CLK,\r
     SPI_CS    => SPI_CS,\r
     SPI_IN    => SPI_IN,\r
@@ -210,7 +196,7 @@ THE_SPI : entity work.spi_slave
 THE_FLASH_CONTROLLER : entity generic_flash_ctrl\r
   port map(\r
 \r
-    CLK_l => clk_i,\r
+    CLK_l => clk_66,\r
     CLK_f => clk_33,\r
     RESET => '0',\r
 \r
@@ -220,7 +206,7 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
     SPI_WRITE_IN  => spi_write_out,\r
     SPI_READ_IN   => spi_read_out,\r
     SPI_READY_OUT => spi_ready_in,\r
-    SPI_BUSY_IN   => spi_busy_out,\r
+    SPI_BUSY_IN   => '0',\r
 \r
     LOC_DATA_OUT  => spi_rx_data,\r
     LOC_DATA_IN   => spi_tx_data,\r
@@ -231,6 +217,13 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
     LOC_BUSY_OUT  => bus_busy\r
   );\r
     \r
+--spi_rx_data <= spi_data_out;\r
+--spi_data_in <= spi_tx_data;\r
+--spi_addr <= spi_addr_out;\r
+--bus_write <= spi_write_out;\r
+--bus_read <= spi_read_out;\r
+--spi_ready_in <= bus_ready;\r
+--bus_busy <= spi_busy_out;\r
 \r
 ---------------------------------------------------------------------------\r
 -- Temperature and UID reader\r
@@ -238,24 +231,27 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
 \r
 TEMP_SENSOR_AND_UID: entity Amps2_TempSensor_UID\r
   port map(\r
-    clk => clk_i,\r
+--    clk => clk_i,\r
+    clk => clk_66,\r
     temperature => temperature_i,\r
     ID_OUT => ID_OUT,\r
     sda => I2C_SDA,\r
     scl => I2C_SCL\r
   );\r
 \r
+--temperature_i <= "000000000000";\r
+--ID_OUT <= x"00000000";\r
 \r
 ---------------------------------------------------------------------------\r
 -- Temperature Compensation\r
 ---------------------------------------------------------------------------  \r
-temperature_i_s <= temperature_i when rising_edge(clk_33);\r
-comp_setting_s <= comp_setting when rising_edge(clk_33);\r
-temp_calc_i <= signed(temperature_i_s) * signed(comp_setting_s) when rising_edge(clk_33);\r
+temperature_i_s <= temperature_i when rising_edge(clk_66);\r
+comp_setting_s <= comp_setting when rising_edge(clk_66);\r
+temp_calc_i <= signed(temperature_i_s) * signed(comp_setting_s) when rising_edge(clk_66);\r
 \r
 \r
 gen_comp: if TEMP_CORRECTION = 1 generate\r
-  compensate_i <= temp_calc_i(27 downto 12) when rising_edge(clk_33);\r
+  compensate_i <= temp_calc_i(27 downto 12) when rising_edge(clk_66);\r
 end generate;\r
 \r
 gen_no_comp: if TEMP_CORRECTION = 0 generate\r
@@ -267,31 +263,28 @@ end generate;
 ---------------------------------------------------------------------------  \r
 \r
 THE_IO_REG : process begin\r
-  wait until rising_edge(clk_i);\r
+--  wait until rising_edge(clk_i);\r
+  wait until rising_edge(clk_66);\r
   bus_ready     <= '0';\r
   pwm_write_i   <= '0';    \r
   spi_tx_data   <= x"0000";\r
   \r
   if delayed_bus_ready = "01" then\r
-    --bus_ready <= '1';\r
-    spi_tx_data <= pwm_data_o;\r
     delayed_bus_ready <= "10";\r
   elsif delayed_bus_ready = "10" then\r
     bus_ready <= '1';\r
     spi_tx_data <= pwm_data_o;\r
-    delayed_bus_ready <= "00";\r
+    delayed_bus_ready <= "11";\r
   else\r
     delayed_bus_ready <= "00";\r
   end if;\r
       \r
   if bus_read = '1' then\r
-    bus_ready <= '1';\r
-    if (spi_addr >= x"00") and (spi_addr < x"10") and delayed_bus_ready = "00"then\r
-      bus_ready <= '0';\r
+    if spi_addr(7 downto 4) = x"0" and delayed_bus_ready = "00" then\r
       delayed_bus_ready <= "01";\r
-      spi_tx_data <= pwm_data_o;\r
       pwm_addr_i  <= spi_addr(3 downto 0);\r
-    else\r
+    elsif delayed_bus_ready = "00" then\r
+      bus_ready <= '1';\r
       case spi_addr is\r
         when x"10" => spi_tx_data <= ID_OUT(7 downto 0) & "00000000" ;\r
         when x"11" => spi_tx_data <= "00000000" & ID_OUT(31 downto 24);\r
@@ -314,11 +307,12 @@ THE_IO_REG : process begin
         when x"30" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));\r
         when x"31" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));\r
         when x"32" => spi_tx_data <= x"0000";\r
+\r
         when x"ff" => spi_tx_data <= x"0200"; --version\r
         when others => null;\r
       end case;\r
     end if;\r
-  elsif bus_write = '1' then\r
+  elsif bus_write = '1' then    \r
     if (spi_addr >= x"00") and (spi_addr < x"10") then  -- write directly to PWM\r
       pwm_data_i  <= spi_rx_data;\r
       pwm_addr_i  <= spi_addr(3 downto 0);\r
@@ -350,6 +344,7 @@ end process;
 THE_PWM_GEN : entity work.pwm_generator\r
   port map(\r
     CLK        => clk_i,\r
+--    CLK        => clk_66,\r
     DATA_IN    => pwm_data_i,\r
     DATA_OUT   => pwm_data_o,\r
     COMP_IN    => compensate_i,\r
@@ -364,7 +359,8 @@ THE_PWM_GEN : entity work.pwm_generator
 ---------------------------------------------------------------------------\r
 \r
   PROC_LED_STATE : process begin\r
-    wait until rising_edge(clk_i);\r
+--    wait until rising_edge(clk_i);\r
+    wait until rising_edge(clk_66);\r
     for i in 1 to 8 loop\r
       if (last_inp(i/2+1) xor inp_status(i/2+1)) = '1' and (led_timer(i)(23 downto 21) > 0) then\r
         led_state(i) <= not led_state(i);\r
@@ -391,6 +387,8 @@ CON <= inp_gated or (inp_stretched and inp_stretch);
 inp_hold <= (inp_gated or inp_hold) and not inp_hold_reg;\r
 inp_hold_reg <= inp_hold when rising_edge(clk_i);\r
 last_inp_hold_reg <= inp_hold_reg when rising_edge(clk_i);\r
+--  inp_hold_reg <= inp_hold when rising_edge(clk_66);\r
+--  last_inp_hold_reg <= inp_hold_reg when rising_edge(clk_66);\r
 inp_stretched <= inp_hold_reg or last_inp_hold_reg or inp_hold;\r
 \r
 fast_input <= inp_gated(14) & inp_gated(12) & inp_gated(10) & inp_gated(8) & inp_gated(6) & inp_gated(4) & inp_gated(2) & inp_gated(0);\r

diff --git a/amps2/par.p2t b/amps2/par.p2t
index 39a0684ade7695b89ccf550cff63e3bcefbc78c2..e30e2281c33b31c96c8da791600b4d8efeed9f6a 100644 (file)
--- a/amps2/par.p2t
+++ b/amps2/par.p2t
@@ -1,21 +1,9 @@
 -w
--i 15
 -l 5
+-i 6
 -n 1
--y
--s 12
 -t 1
--c 1
--e 2
-#-g guidefile.ncd
-#-m nodelist.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
--exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
+-s 1
+-c 0
+-e 0
+-exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF:parHold=0
\ No newline at end of file

diff --git a/pinout/padiwa_amps2.lpf b/pinout/padiwa_amps2.lpf
index 92b1ef48240fa3e789400fc3c897bce72bb283b2..f60a7ef4f3abfe2b79c3dd2e7d2df76e6ac2a238 100644 (file)
--- a/pinout/padiwa_amps2.lpf
+++ b/pinout/padiwa_amps2.lpf
@@ -148,12 +148,13 @@ LOCATE COMP  "TMP_ALERT"    SITE "A8";
 IOBUF PORT  "TMP_ALERT" IO_TYPE=LVTTL33 PULLMODE=UP;
 
 
-UGROUP "StretchA" BBOX 1 32
+UGROUP "StretchA" BBOX 4 39
   BLKNAME THE_STRETCHER/Stretcher_A_1
   ;
-LOCATE UGROUP "StretchA" SITE "R25C6";  
+LOCATE UGROUP "StretchA" SITE "R22C2";  
   
-UGROUP "StretchB" BBOX 1 32
+UGROUP "StretchB" BBOX 4 39
   BLKNAME THE_STRETCHER/Stretcher_B_1
   ;
-LOCATE UGROUP "StretchB" SITE "R2C6";  
+LOCATE UGROUP "StretchB" SITE "R2C2";  
+#LOCATE UGROUP "StretchB" SITE "R18C2";
\ No newline at end of file

diff --git a/source/Amps2_TempSensor_UID.vhd b/source/Amps2_TempSensor_UID.vhd
index f6678eb4b921b999826d0250161084902a3d8e67..dcc26b99ce34b6febecef02159872585f3329425 100644 (file)
--- a/source/Amps2_TempSensor_UID.vhd
+++ b/source/Amps2_TempSensor_UID.vhd
@@ -39,6 +39,7 @@ begin
     scl             => scl
   );
 
+  
 process begin
   wait until rising_edge(clk);
   count <= count + 1;

diff --git a/source/i2c_master.vhd b/source/i2c_master.vhd
index f63a6c65835c357d62f1fa5f26b873b71c4cf3b7..173c3848a7d66e05c4ac5df2cd16b3bdf3782cb8 100644 (file)
--- a/source/i2c_master.vhd
+++ b/source/i2c_master.vhd
@@ -5,7 +5,8 @@ USE ieee.std_logic_unsigned.all;
 
 ENTITY i2c_master IS
   GENERIC(
-    input_clk : INTEGER := 133_000_000; --input clock speed from user logic in Hz
+    --input_clk : INTEGER := 133_000_000; --input clock speed from user logic in Hz
+    input_clk : INTEGER := 66_500_000;
     bus_clk   : INTEGER := 100_000);     --speed the i2c bus (scl) will run at in Hz
   PORT(
     clk       : IN     STD_LOGIC;                    --system clock