mem to flash working

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index f34676e44e7a8c39c337b6e30fe3b95a412153cd..283e333101d7776ad073c79460cbcdbd32ccab06 100644 (file)
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -170,7 +170,7 @@ architecture arch of generic_flash_ctrl is
   signal master_READ_OUT  : std_logic;
   signal master_readback_reg : std_logic_vector(7 downto 0) := x"00";
   signal readback_reg : std_logic_vector(7 downto 0) := x"00";
-  signal master_readback_num : std_logic_vector(3 downto 0) := x"0";
+  signal master_readback_num : std_logic_vector(4 downto 0) := "00000";
   signal readback_num : std_logic_vector(3 downto 0) := x"0";
   
   
@@ -539,7 +539,7 @@ begin
         master_word_counter <= "0000";
         if master_readback = '1' then
           state <= ReadSPI0;
-          master_readback_num <= readback_num;
+          master_readback_num <= std_logic_vector(unsigned('0' & readback_num) + 1);
           master_readback_reg <= readback_reg;
           master_word_counter <= x"F";
         else
@@ -559,7 +559,7 @@ begin
         state <= WaitFlash2;
         if (flash_busy = '0' and master_flash_go = '0') then
           if master_readback = '1' then
-            if master_readback_num = x"0" then
+            if master_readback_num = "00000" then
               state <= DisableFLASH1;
             else
               state <= ReadSPI0;
@@ -576,30 +576,39 @@ begin
         master_ADDR_OUT <= master_readback_reg;
         master_READ_OUT <= '1';
         state <= ReadSPI1;
-        master_ram_data_i  <= x"01"; --16bit version only
+        if master_readback_num = "00000" then
+          master_ram_data_i  <= x"00"; --stop
+          state <= ReadSPI3;
+        else
+          master_ram_data_i  <= x"01"; --16bit version only
+        end if;
         master_ram_write_i <= '1';
         master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);
       when ReadSPI1 =>
-        state <= ReadSPI2;
-        master_ram_data_i <= master_readback_reg;
-        master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);
+        if LOC_READY_IN = '1' then
+          state <= ReadSPI2;
+          master_ram_data_i <= master_readback_reg;
+          master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);
+        end if;
       when ReadSPI2 =>
         master_ram_data_i <= LOC_DATA_IN(15 downto 8);
         master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);
-        master_readback_num <= std_logic_vector(unsigned(master_readback_num) - 1);
-        master_readback_reg <= std_logic_vector(unsigned(master_readback_reg) + 1);
         state <= ReadSPI3;
       when ReadSPI3 =>
         master_ram_data_i <= LOC_DATA_IN(7 downto 0);
         -- prepare for next cycle
-        if (master_word_counter = x"F" or master_readback_num = x"0") then
+        if (master_word_counter = x"E" or master_readback_num = "00000") then
           state <= WritePage;
-          master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);
         else
           state <= ReadSPI0;
+        end if;
+        if master_readback_num = "00000" then
+          master_ram_write_i <= '0';
+        else
           master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);
+          master_readback_num <= std_logic_vector(unsigned(master_readback_num) - 1);
+          master_readback_reg <= std_logic_vector(unsigned(master_readback_reg) + 1);
         end if;
-
         
       --READ from flash and store to registers
       when ReadRAM =>