type shiftreg_array_t is array (0 to 1) of std_logic_vector(4 * g_datawidthfifo - 1 downto 0);
signal shiftregs : shiftreg_array_t := (others => (others => '0'));
+ -- writing to memory
type writing_fsm_t is (idle, writing);
- signal writing_fsm : writing_fsm_t := idle;
- signal read_index : integer range 0 to 1 := 1;
- signal shiftreg_read : std_logic_vector(4 * g_datawidthfifo - 1 downto 0);
- signal wordssend : integer range 0 to 4 := 0;
- signal buff_wren_i : std_logic := '0';
- signal dataout_i : std_logic_vector(g_datawidthtrb - 1 downto 0) := (others => '0');
+ signal writing_fsm : writing_fsm_t := idle;
+ signal read_index : integer range 0 to 1 := 1;
+ signal shiftreg_read : std_logic_vector(4 * g_datawidthfifo - 1 downto 0);
+ signal wordssend : integer range 0 to 4 := 0;
+ signal buff_wren_i : std_logic := '0';
+ signal dataout_i : std_logic_vector(g_datawidthtrb - 1 downto 0) := (others => '0');
+ signal buff_wren_data : std_logic := '0';
+ signal dataout_data : std_logic_vector(g_datawidthtrb - 1 downto 0) := (others => '0');
+ -- reading from fifo
type fifo_read_fsm_t is (idle, waitfifo, reading);
signal fifo_read_fsm : fifo_read_fsm_t := idle;
signal start_sending, start_sending_accpted : std_logic := '0';
signal fill_index : integer range 0 to 1 := 0;
signal fill_cnt : integer range 0 to 4 := 0;
+ -- handling start/stop of conversion indicators
+ constant send_start_word : std_logic_vector(31 downto 0) := x"C0FEBABE";
+ constant send_stop_word : std_logic_vector(31 downto 0) := x"BEEFBABE";
+ signal runing_i : std_logic := '0';
+ signal send_start_word_i, send_stop_word_i : std_logic := '0';
+ signal start_i : std_logic := '0';
+ signal stop_i : std_logic := '0';
+
begin -- architecture rtl
+ indicator_proc : process (clk) is
+ begin -- process indicator_proc
+ if rising_edge(clk) then -- rising clock edge
+ if reset = '1' then -- synchronous reset (active high)
+ runing_i <= '0';
+ send_stop_word_i <= '0';
+ send_start_word_i <= '0';
+ else
+ send_start_word_i <= '0';
+ send_stop_word_i <= '0';
+ if start_i = '1' and runing_i = '0' then
+ runing_i <= '1';
+ send_start_word_i <= '1';
+ end if;
+ if stop_i = '1' and runing_i = '1' then
+ runing_i <= '0';
+ send_stop_word_i <= '1';
+ end if;
+ end if;
+ end if;
+ end process indicator_proc;
fifo_reading : process (clk) is
begin -- process fifo_reading
start_sending <= '0';
end if;
fifo_rden <= '0';
+ start_i <= '0';
+ stop_i <= '0';
case fifo_read_fsm is
when idle =>
pause_cnt_i <= pause_cnt_i + 1;
readenable_cnt_i <= 1;
wordstosend(fill_index) <= 4;
pause_cnt_i <= 0;
+ start_i <= '1';
elsif pause_cnt_i = 23 then
pause_cnt_i <= 0;
fifo_wrcnt_reg <= fifo_wrcnt;
- if fifo_wrcnt = fifo_wrcnt_reg and fifo_empty = '0' then
- fifo_read_fsm <= waitfifo;
- fifo_rden <= '1';
- readenable_cnt_i <= 1;
- wordstosend(fill_index) <= to_integer(unsigned(fifo_wrcnt));
+ if fifo_empty = '0' then
+ if fifo_wrcnt = fifo_wrcnt_reg and fifo_empty = '0' then
+ fifo_read_fsm <= waitfifo;
+ fifo_rden <= '1';
+ readenable_cnt_i <= 1;
+ wordstosend(fill_index) <= to_integer(unsigned(fifo_wrcnt));
+ start_i <= '1';
+ end if;
+ else
+ stop_i <= '1';
end if;
else
fifo_read_fsm <= idle;
wordstosend(fill_index) <= 0;
end if;
-
+
when waitfifo =>
fifo_wrcnt_reg <= (others => '1');
fifo_read_fsm <= reading;
readenable_cnt_i <= 2;
fifo_rden <= '1';
end if;
-
+
when reading =>
if readenable_cnt_i < wordstosend(fill_index) then
readenable_cnt_i <= readenable_cnt_i + 1;
begin -- process writing
if rising_edge(clk) then -- rising clock edge
if reset = '1' then -- synchronous reset (active high)
- buff_wren_i <= '0';
- dataout_i <= (others => '0');
+ buff_wren_data <= '0';
+ dataout_data <= (others => '0');
read_index <= 1;
start_sending_accpted <= '0';
else
- buff_wren_i <= '0';
- dataout_i <= (others => '0');
+ buff_wren_data <= '0';
+ dataout_data <= (others => '0');
start_sending_accpted <= '0';
case writing_fsm is
when idle =>
start_sending_accpted <= '1';
writing_fsm <= writing;
wordssend <= 0;
- -- extra bondary word, remove for testbench
- buff_wren_i <= '1';
- dataout_i <= x"F0F0F0F0";
if read_index = 1 then
read_index <= 0;
else
read_index <= read_index + 1;
end if;
end if;
-
+
when writing =>
case wordssend is
when 0 =>
- wordssend <= 1;
- buff_wren_i <= '1';
- dataout_i <= shiftreg_read(159 downto 128);
+ wordssend <= 1;
+ buff_wren_data <= '1';
+ dataout_data <= shiftreg_read(159 downto 128);
when 1 =>
- wordssend <= 2;
- buff_wren_i <= '1';
+ wordssend <= 2;
+ buff_wren_data <= '1';
if wordstosend(read_index) = 1 then
- dataout_i <= shiftreg_read(127 downto 120) & padding_0;
- writing_fsm <= idle;
+ dataout_data <= shiftreg_read(127 downto 120) & padding_0;
+ writing_fsm <= idle;
else
- dataout_i <= shiftreg_read(127 downto 96);
+ dataout_data <= shiftreg_read(127 downto 96);
end if;
when 2 =>
- wordssend <= 3;
- buff_wren_i <= '1';
+ wordssend <= 3;
+ buff_wren_data <= '1';
if wordstosend(read_index) = 2 then
- dataout_i <= shiftreg_read(95 downto 80) & padding_1;
- writing_fsm <= idle;
+ dataout_data <= shiftreg_read(95 downto 80) & padding_1;
+ writing_fsm <= idle;
else
- dataout_i <= shiftreg_read(95 downto 64);
+ dataout_data <= shiftreg_read(95 downto 64);
end if;
when 3 =>
- wordssend <= 4;
- buff_wren_i <= '1';
+ wordssend <= 4;
+ buff_wren_data <= '1';
if wordstosend(read_index) = 3 then
- dataout_i <= shiftreg_read(63 downto 40) & padding_2;
- writing_fsm <= idle;
+ dataout_data <= shiftreg_read(63 downto 40) & padding_2;
+ writing_fsm <= idle;
else
- dataout_i <= shiftreg_read(63 downto 32);
+ dataout_data <= shiftreg_read(63 downto 32);
end if;
when 4 =>
- wordssend <= 1;
- writing_fsm <= idle;
- buff_wren_i <= '1';
- dataout_i <= shiftreg_read(31 downto 0);
+ wordssend <= 1;
+ writing_fsm <= idle;
+ buff_wren_data <= '1';
+ dataout_data <= shiftreg_read(31 downto 0);
end case;
end case;
end if;
end if;
end process writing_proc;
+ data_multiplexer : process (send_stop_word_i, send_start_word_i, buff_wren_data, dataout_data) is
+ begin -- process data_multiplexer
+ if send_start_word_i = '1' then
+ buff_wren_i <= '1';
+ dataout_i <= send_start_word;
+ elsif send_stop_word_i = '1' then
+ buff_wren_i <= '1';
+ dataout_i <= send_stop_word;
+ else
+ buff_wren_i <= buff_wren_data;
+ dataout_i <= dataout_data;
+ end if;
+ end process data_multiplexer;
+
output_pipe : process (clk) is
begin -- process output_mux
if rising_edge(clk) then -- rising clock edge
jspc29 / trb3.git / commitdiff