-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO;
--Which external trigger module (ETM) to use?
constant INCLUDE_ETM : integer range c_NO to c_YES := c_YES;
- type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B);
+ type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B, ETM_CHOICE_SPILLMON);
constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM;
constant ETM_ID : std_logic_vector(7 downto 0);
-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO;
--Which external trigger module (ETM) to use?
constant INCLUDE_ETM : integer range c_NO to c_YES := c_YES;
- type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B);
+ type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B, ETM_CHOICE_SPILLMON);
constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM;
constant ETM_ID : std_logic_vector(7 downto 0);
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+use work.trb_net16_hub_func.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+--design options: backplane or front SFP, with or without GBE
+ constant USE_BACKPLANE : integer := c_YES; --not combined with RJADAPT
+ constant USE_ADDON : integer := c_NO;
+ constant USE_RJADAPT : integer := c_NO; --!!! Change pin-out file!
+ constant INCLUDE_GBE : integer := c_YES; --c_NO doesn't work
+
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+ constant USE_200MHZOSCILLATOR : integer := c_YES;
+ constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented.
+ constant CLOCK_FAST_SELECT : integer := c_YES; --fast clock select (135us) or slow (280ms)?
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F3C0";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"63"; --62 for SFP, 63 for backplane
+
+
+ constant INCLUDE_UART : integer := c_YES;
+ constant INCLUDE_SPI : integer := c_YES;
+ constant INCLUDE_LCD : integer := c_NO;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_YES;
+
+ --input monitor and trigger generation logic
+ constant INCLUDE_TDC : integer := c_NO;
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
+ constant INCLUDE_STATISTICS : integer := c_YES;
+ constant TRIG_GEN_INPUT_NUM : integer := 36 - USE_RJADAPT*12 + USE_BACKPLANE*18;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 2;
+ constant MONITOR_INPUT_NUM : integer := 36 - USE_RJADAPT*12 + USE_BACKPLANE*18;
+
+
+ constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5
+
+
+ constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+ constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
+ constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons
+ constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+ -- 0: single edge only,
+ -- 1: same channel,
+ -- 2: alternating channels,
+ -- 3: same channel with stretcher
+ constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 --> change names in constraints file
+ --ring buffer size: 32,64,96,128,dyn
+ constant TDC_DATA_FORMAT : integer := 0;
+
+ constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 1023; --maximum event size. Should not exceed
+
+ constant GEN_BUSY_OUTPUT : integer := c_NO;
+
+ constant TRIGGER_COIN_COUNT : integer := 1;
+ constant TRIGGER_PULSER_COUNT : integer := 3;
+ constant TRIGGER_RAND_PULSER : integer := 1;
+ constant TRIGGER_ADDON_COUNT : integer := 4;
+ constant PERIPH_TRIGGER_COUNT : integer := 0;
+ constant ADDON_LINE_COUNT : integer := 36 - USE_RJADAPT*12 + USE_BACKPLANE*18; --36 with Padiwa, 22 with RJ-adapter, 54 with backplane
+ constant CTS_OUTPUT_MULTIPLEXERS : integer := 1;
+--TODO:
+-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO;
+--Which external trigger module (ETM) to use?
+ constant INCLUDE_ETM : integer range c_NO to c_YES := c_YES;
+ type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B, ETM_CHOICE_SPILLMON);
+ constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM;
+ constant ETM_ID : std_logic_vector(7 downto 0);
+
+ constant INCLUDE_TIMESTAMP_GENERATOR : integer := c_NO;
+
+
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+ type data_t is array (0 to 1023) of std_logic_vector(7 downto 0);
+ constant LCD_DATA : data_t := (
+ x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch
+ x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+ x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch
+
+ x"48", x"75", x"62", x"41", x"64", x"64", x"4f", x"6e", x"0a",
+ x"0a",
+ x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a",
+ x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a",
+ x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a",
+ others => x"00");
+
+
+ type hub_mii_t is array(0 to 3) of integer;
+ type hub_ct is array(0 to 16) of integer;
+ type hub_cfg_t is array(0 to 3) of hub_ct;
+ type hw_info_t is array(0 to 3) of std_logic_vector(31 downto 0);
+ type intlist_t is array(0 to 7) of integer;
+-- 0 opt. link opt. link
+-- 0-7 SFP 1-8
+-- 1(8) CTS read-out internal 0 1 - X X O --downlink only
+-- 2(9) CTS TRG Sctrl GbE 2 3 4 X X X --uplink only
+
+ --Order:
+ -- no backplane, no AddOn, 1x SFP, 1x GBE
+ -- backplane, no AddOn, 1x SFP, 1x GBE
+ -- no backplane, 8x AddOn, 0x SFP, 1x GBE
+
+ constant SFP_NUM_ARR : hub_mii_t := (1,1,8,0);
+ constant INTERFACE_NUM_ARR : hub_mii_t := (1,10,8,0);
+-- 0 1 2 3 4 5 6 7 8 9 a b c d e f
+ constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ (0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0),
+ (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0),
+ (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0));
+ constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ (1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0),
+ (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0),
+ (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0));
+ constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0),
+ (0,0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0),
+ (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0),
+ (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0));
+
+ constant INTERFACE_NUM : integer;
+ constant IS_UPLINK : hub_ct;
+ constant IS_DOWNLINK : hub_ct;
+ constant IS_UPLINK_ONLY : hub_ct;
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ constant cts_rdo_additional_ports : integer := INCLUDE_TDC + INCLUDE_TIMESTAMP_GENERATOR + INCLUDE_ETM; --for TDC
+
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"9500A000";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
+ HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+ constant CFG_MODE : integer := USE_ADDON*2 + USE_BACKPLANE;
+
+ constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE);
+ constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE);
+ constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE);
+ constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE);
+
+ function etm_id_func return std_logic_vector is
+ variable res : unsigned(7 downto 0);
+ begin
+ res := x"00";
+ if INCLUDE_ETM=c_YES then
+ res := x"60";
+ res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4);
+ end if;
+ return std_logic_vector(res);
+ end function;
+
+ constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func;
+
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1
+ t(3 downto 0) := std_logic_vector(TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4));
+ t(7 downto 7) := std_logic_vector(to_unsigned(USE_RJADAPT,1));
+ t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+ t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+ t(15 downto 15) := std_logic_vector(to_unsigned(INCLUDE_TDC,1)); --TDC
+ t(16 downto 16) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --data via GbE
+ t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE
+ t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1));
+ t(26 downto 24) := std_logic_vector(to_unsigned(SFP_NUM_ARR(CFG_MODE),3)); --num SFPs with TrbNet
+ t(28 downto 28) := std_logic_vector(to_unsigned(USE_BACKPLANE,1));
+ t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1));
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
TOPNAME => "trb3sc_cts",
lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
lm_license_file_for_par => "1702\@hadeb05.gsi.de",
-lattice_path => '/d/jspc29/lattice/diamond/3.11_x64',
-synplify_path => '/d/jspc29/lattice/synplify/R-2020.09-SP1',
+lattice_path => '/d/jspc29/lattice/diamond/3.12',
+synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2',
#synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
#pinout_file => 'trb3sc_hub_ctsrj', #with RJ adapter for I/O
-pinout_file => 'trb3sc_hub_kelpadiwa', #with SPI on KEL connectors
+#pinout_file => 'trb3sc_hub_kelpadiwa', #with SPI on KEL connectors
+ pinout_file => 'trb3sc_master', #with backplane
#Include only necessary lpf files
-- constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_NO;
--Which external trigger module (ETM) to use?
constant INCLUDE_ETM : integer range c_NO to c_YES := c_YES;
- type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26);
+ type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26, ETM_CHOICE_R3B, ETM_CHOICE_SPILLMON);
constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_MBS_VULOM;
constant ETM_ID : std_logic_vector(7 downto 0);
-# LOCATE COMP "gen_PCSA.THE_MEDIA_PCSA/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ;
-# LOCATE COMP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-# LOCATE COMP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-# LOCATE COMP "THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC" ;
-# LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST" SITE "PCSD" ;
+
+LOCATE COMP "gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST" SITE "PCSA";
LOCATE COMP "gen_PCSB.THE_MEDIA_PCSB/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB";
LOCATE COMP "gen_PCSB_ADDON.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB";
+LOCATE COMP "gen_PCSB_BKPL.THE_MEDIA_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB";
+
LOCATE COMP "gen_PCSC.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC";
+LOCATE COMP "gen_PCSC_BKPL.THE_MEDIA_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC";
+
LOCATE COMP "GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSD";
BLOCK PATH FROM CELL THE_TDC/calibration_o*;
BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/TheTriggerHandler/trg_in_r[0];
# REGION "MEDIA_GBE" "R89C2" 25 53;
-REGION "MEDIA_C" "R102C128" 13 40;
-REGION "MEDIA_B" "R102C55" 13 40;
-REGION "MEDIA_DOWN1" "R102C20D" 13 120;
-#LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ;
-#LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ;
-#LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ;
-#LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ;
-#LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_DOWN1" ;
+REGION "MEDIA_A" "R75C100D" 45 46;
+# REGION "MEDIA_B" "R102C55" 13 40;
+# REGION "MEDIA_C" "R102C128" 13 40;
+REGION "MEDIA_B" "R75C45D" 45 56;
+REGION "MEDIA_C" "R75C135D" 45 46;
+REGION "MEDIA_D" "R75C19D" 40 36;
+
+LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_A" ;
+
LOCATE UGROUP "gen_PCSB.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_B" ;
-LOCATE UGROUP "gen_PCSC.THE_MEDIA_PCSC/media_interface_group" REGION "MEDIA_C" ;
LOCATE UGROUP "gen_PCSB_ADDON.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_B" ;
+LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_PCSB/media_interface_group" REGION "MEDIA_B" ;
+
+LOCATE UGROUP "gen_PCSC.THE_MEDIA_PCSC/media_interface_group" REGION "MEDIA_C" ;
+LOCATE UGROUP "gen_PCSC_BKPL.THE_MEDIA_PCSC/media_interface_group" REGION "MEDIA_C" ;
# UGROUP "GBE_GROUP" BBOX 44 60
# # BLKNAME GBE;
HUB_MOD2 : inout std_logic_vector(8 downto 1);
HUB_TXDIS : out std_logic_vector(8 downto 1);
HUB_LOS : in std_logic_vector(8 downto 1);
+
+ --Lines to slaves
+ BACK_MASTER_READY : out std_logic_vector(8 downto 0);
+ BACK_SLAVE_READY : in std_logic_vector(8 downto 0);
+ BACK_TRIG1 : in std_logic_vector(8 downto 0);
+ BACK_TRIG2 : in std_logic_vector(8 downto 0);
--Serdes switch
PCSSW_ENSMB : out std_logic;
signal timer : TIMERS;
signal reset_via_gbe : std_logic := '0';
- signal med_dataready_out : std_logic_vector ((1+USE_ADDON*7)-1 downto 0);
- signal med_data_out : std_logic_vector ((1+USE_ADDON*7)*c_DATA_WIDTH-1 downto 0);
- signal med_packet_num_out : std_logic_vector ((1+USE_ADDON*7)*c_NUM_WIDTH-1 downto 0);
- signal med_read_in : std_logic_vector ((1+USE_ADDON*7)-1 downto 0);
- signal med_dataready_in : std_logic_vector ((1+USE_ADDON*7)-1 downto 0);
- signal med_data_in : std_logic_vector ((1+USE_ADDON*7)*c_DATA_WIDTH-1 downto 0);
- signal med_packet_num_in : std_logic_vector ((1+USE_ADDON*7)*c_NUM_WIDTH-1 downto 0);
- signal med_read_out : std_logic_vector ((1+USE_ADDON*7)-1 downto 0);
- signal med_stat_op : std_logic_vector ((1+USE_ADDON*7)*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector ((1+USE_ADDON*7)*16-1 downto 0);
+ signal med_dataready_out : std_logic_vector (INTERFACE_NUM-1 downto 0);--(1+USE_ADDON*7+USE_BACKPLANE*9)
+ signal med_data_out : std_logic_vector (INTERFACE_NUM*c_DATA_WIDTH-1 downto 0);
+ signal med_packet_num_out : std_logic_vector (INTERFACE_NUM*c_NUM_WIDTH-1 downto 0);
+ signal med_read_in : std_logic_vector (INTERFACE_NUM-1 downto 0);
+ signal med_dataready_in : std_logic_vector (INTERFACE_NUM-1 downto 0);
+ signal med_data_in : std_logic_vector (INTERFACE_NUM*c_DATA_WIDTH-1 downto 0);
+ signal med_packet_num_in : std_logic_vector (INTERFACE_NUM*c_NUM_WIDTH-1 downto 0);
+ signal med_read_out : std_logic_vector (INTERFACE_NUM-1 downto 0);
+ signal med_stat_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0);
+ signal med_ctrl_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0);
signal rdack, wrack : std_logic;
signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0);
LOCK => open);
---------------------------------------------------------------------------
--- PCSA
----------------------------------------------------------------------------
-bussci1_tx.data <= (others => '0');
-bussci1_tx.ack <= '0';
-bussci1_tx.nack <= '0';
-bussci1_tx.unknown <= '1';
+-- PCSA First half of backplane
+---------------------------------------------------------------------------
+gen_PCSA : if USE_BACKPLANE = c_YES and USE_ADDON = c_NO generate
+ THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync_4 --PCSA
+ generic map(
+ IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+ IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
+ )
+ port map(
+ CLK_REF_FULL => clk_full_osc,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+
+ --Internal Connection
+ MEDIA_MED2INT(0 to 3) => med2int(0 to 3),
+ MEDIA_INT2MED(0 to 3) => int2med(0 to 3),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN => BACK_SLAVE_READY(3 downto 0),
+ SD_LOS_IN => BACK_SLAVE_READY(3 downto 0),
+ SD_TXDIS_OUT => BACK_MASTER_READY(3 downto 0),
+
+ --Control Interface
+ BUS_RX => bussci1_rx,
+ BUS_TX => bussci1_tx,
+ -- Status and control port
+ STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+end generate;
+
+gen_no_PCSA : if USE_BACKPLANE = c_NO generate
+ bussci1_tx.data <= (others => '0');
+ bussci1_tx.ack <= '0';
+ bussci1_tx.nack <= '0';
+ bussci1_tx.unknown <= '1';
+end generate;
---------------------------------------------------------------------------
--- PCSB Downlink without backplane is SFP
+-- PCSB
---------------------------------------------------------------------------
gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
THE_MEDIA_PCSB : entity work.med_ecp3_sfp_sync
PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1
end generate;
+gen_PCSB_ADDON : if USE_BACKPLANE = c_NO and USE_ADDON = c_YES generate
+ THE_MEDIA_PCSB : entity work.med_ecp3_sfp_sync_4
+ generic map(
+ IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+ IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
+ )
+ port map(
+ CLK_REF_FULL => clk_full_osc,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+
+ --Internal Connection
+ MEDIA_MED2INT(0) => med2int(4),
+ MEDIA_MED2INT(1) => med2int(5),
+ MEDIA_MED2INT(2) => med2int(6),
+ MEDIA_MED2INT(3) => med2int(7),
+ MEDIA_INT2MED(0) => int2med(4),
+ MEDIA_INT2MED(1) => int2med(5),
+ MEDIA_INT2MED(2) => int2med(6),
+ MEDIA_INT2MED(3) => int2med(7),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN(0) => HUB_MOD0(5),
+ SD_PRSNT_N_IN(1) => HUB_MOD0(6),
+ SD_PRSNT_N_IN(2) => HUB_MOD0(7),
+ SD_PRSNT_N_IN(3) => HUB_MOD0(8),
+
+ SD_LOS_IN(0) => HUB_LOS(5),
+ SD_LOS_IN(1) => HUB_LOS(6),
+ SD_LOS_IN(2) => HUB_LOS(7),
+ SD_LOS_IN(3) => HUB_LOS(8),
+
+ SD_TXDIS_OUT(0) => HUB_TXDIS(5),
+ SD_TXDIS_OUT(1) => HUB_TXDIS(6),
+ SD_TXDIS_OUT(2) => HUB_TXDIS(7),
+ SD_TXDIS_OUT(3) => HUB_TXDIS(8),
+
+ --Control Interface
+ BUS_RX => bussci2_rx,
+ BUS_TX => bussci2_tx,
+
+ -- Status and control port
+ STAT_DEBUG => open, --med_stat_debug(63 downto 0),
+ CTRL_DEBUG => open
+ );
+ PCSSW <= "11100100"; --01001110"; --default 1:1
+end generate;
+
+gen_PCSB_BKPL : if USE_BACKPLANE = c_YES and USE_ADDON = c_NO generate
+ THE_MEDIA_PCSB : entity work.med_ecp3_sfp_sync_4
+ generic map(
+ IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
+ IS_USED => (c_YES, c_YES, c_YES ,c_YES)
+ )
+ port map(
+ CLK_REF_FULL => clk_full_osc,
+ CLK_INTERNAL_FULL => clk_full_osc,
+ SYSCLK => clk_sys,
+ RESET => reset_i,
+ CLEAR => clear_i,
+ --Internal Connection
+ MEDIA_MED2INT(0) => med2int(7),
+ MEDIA_MED2INT(1) => med2int(6),
+ MEDIA_MED2INT(2) => med2int(5),
+ MEDIA_MED2INT(3) => med2int(9),
+ MEDIA_INT2MED(0) => int2med(7),
+ MEDIA_INT2MED(1) => int2med(6),
+ MEDIA_INT2MED(2) => int2med(5),
+ MEDIA_INT2MED(3) => int2med(9),
+
+ --Sync operation
+ RX_DLM => open,
+ RX_DLM_WORD => open,
+ TX_DLM => open,
+ TX_DLM_WORD => open,
+
+ --SFP Connection
+ SD_PRSNT_N_IN(0) => BACK_SLAVE_READY(7),
+ SD_LOS_IN(0) => BACK_SLAVE_READY(7),
+ SD_TXDIS_OUT(0) => BACK_MASTER_READY(7),
+ SD_PRSNT_N_IN(1) => BACK_SLAVE_READY(6),
+ SD_LOS_IN(1) => BACK_SLAVE_READY(6),
+ SD_TXDIS_OUT(1) => BACK_MASTER_READY(6),
+ SD_PRSNT_N_IN(2) => BACK_SLAVE_READY(5),
+ SD_LOS_IN(2) => BACK_SLAVE_READY(5),
+ SD_TXDIS_OUT(2) => BACK_MASTER_READY(5),
+ SD_PRSNT_N_IN(3) => SFP_MOD0(1),
+ SD_LOS_IN(3) => SFP_LOS(1),
+ SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
+ --Control Interface
+ BUS_RX => bussci2_rx,
+ BUS_TX => bussci2_tx,
+ -- Status and control port
+ STAT_DEBUG => open,
+ CTRL_DEBUG => open
+ );
+ PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1
+end generate;
---------------------------------------------------------------------------
-- PCSC 4 downlinks
---------------------------------------------------------------------------
--- bussci3_tx.data <= (others => '0');
--- bussci3_tx.ack <= '0';
--- bussci3_tx.nack <= '0';
--- bussci3_tx.unknown <= '1';
+
gen_PCSC : if USE_BACKPLANE = c_NO and USE_ADDON = c_YES generate
THE_MEDIA_PCSC : entity work.med_ecp3_sfp_sync_4
generic map(
);
end generate;
-gen_PCSB_ADDON : if USE_BACKPLANE = c_NO and USE_ADDON = c_YES generate
- THE_MEDIA_PCSB : entity work.med_ecp3_sfp_sync_4
+gen_PCSC_BKPL : if USE_BACKPLANE = c_YES and USE_ADDON = c_NO generate
+ THE_MEDIA_PCSC : entity work.med_ecp3_sfp_sync_4
generic map(
IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
- IS_USED => (c_YES,c_YES ,c_YES ,c_YES)
+ IS_USED => (c_YES,c_YES ,c_NO ,c_NO)
)
port map(
- CLK_REF_FULL => clk_full_osc,
+ CLK_REF_FULL => clk_full_osc,
CLK_INTERNAL_FULL => clk_full_osc,
SYSCLK => clk_sys,
RESET => reset_i,
--Internal Connection
MEDIA_MED2INT(0) => med2int(4),
- MEDIA_MED2INT(1) => med2int(5),
- MEDIA_MED2INT(2) => med2int(6),
- MEDIA_MED2INT(3) => med2int(7),
+ MEDIA_MED2INT(1) => med2int(8),
MEDIA_INT2MED(0) => int2med(4),
- MEDIA_INT2MED(1) => int2med(5),
- MEDIA_INT2MED(2) => int2med(6),
- MEDIA_INT2MED(3) => int2med(7),
+ MEDIA_INT2MED(1) => int2med(8),
--Sync operation
RX_DLM => open,
TX_DLM_WORD => open,
--SFP Connection
- SD_PRSNT_N_IN(0) => HUB_MOD0(5),
- SD_PRSNT_N_IN(1) => HUB_MOD0(6),
- SD_PRSNT_N_IN(2) => HUB_MOD0(7),
- SD_PRSNT_N_IN(3) => HUB_MOD0(8),
-
- SD_LOS_IN(0) => HUB_LOS(5),
- SD_LOS_IN(1) => HUB_LOS(6),
- SD_LOS_IN(2) => HUB_LOS(7),
- SD_LOS_IN(3) => HUB_LOS(8),
-
- SD_TXDIS_OUT(0) => HUB_TXDIS(5),
- SD_TXDIS_OUT(1) => HUB_TXDIS(6),
- SD_TXDIS_OUT(2) => HUB_TXDIS(7),
- SD_TXDIS_OUT(3) => HUB_TXDIS(8),
+ SD_PRSNT_N_IN(0) => BACK_SLAVE_READY(4),
+ SD_PRSNT_N_IN(1) => BACK_SLAVE_READY(8),
+ SD_PRSNT_N_IN(2) => '1',
+ SD_PRSNT_N_IN(3) => '1',
+
+ SD_LOS_IN(0) => BACK_SLAVE_READY(4),
+ SD_LOS_IN(1) => BACK_SLAVE_READY(8),
+ SD_LOS_IN(2) => '1',
+ SD_LOS_IN(3) => '1',
+
+ SD_TXDIS_OUT(0) => BACK_MASTER_READY(4),
+ SD_TXDIS_OUT(1) => BACK_MASTER_READY(8),
+ SD_TXDIS_OUT(2) => open,
+ SD_TXDIS_OUT(3) => open,
--Control Interface
- BUS_RX => bussci2_rx,
- BUS_TX => bussci2_tx,
+ BUS_RX => bussci3_rx,
+ BUS_TX => bussci3_tx,
-- Status and control port
STAT_DEBUG => open, --med_stat_debug(63 downto 0),
CTRL_DEBUG => open
- );
- PCSSW <= "11100100"; --01001110"; --default 1:1
+ );
+end generate;
+
+gen_no_PCSC : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
+ bussci3_tx.data <= (others => '0');
+ bussci3_tx.ack <= '0';
+ bussci3_tx.nack <= '0';
+ bussci3_tx.unknown <= '1';
end generate;
---------------------------------------------------------------------------
THE_CTS : CTS
generic map (
EXTERNAL_TRIGGER_ID => ETM_ID, -- fill in trigger logic enumeration id of external trigger logic
- PLATTFORM => 1+USE_RJADAPT, --TRB3sc+KEL+RJ45
+ PLATTFORM => 1+USE_RJADAPT+2*USE_BACKPLANE, --TRB3sc+KEL+RJ45
OUTPUT_MULTIPLEXERS => CTS_OUTPUT_MULTIPLEXERS,
ADDON_GROUPS => 1,
- ADDON_GROUP_UPPER => (32-USE_RJADAPT*12+3, others => 0)
+ ADDON_GROUP_UPPER => (32-USE_RJADAPT*12+3+USE_BACKPLANE*18, others => 0)
)
port map (
CLK => clk_sys,
FEE_DATA_FINISHED_OUT => cts_rdo_finished
);
-gen_inputs_kel : if USE_RJADAPT = 0 generate
+gen_inputs_kel : if USE_BACKPLANE = 0 and USE_RJADAPT = 0 generate
cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0);
cts_addon_triggers_in(33 downto 2) <= INP(31 downto 0);
cts_addon_triggers_in(35 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys);
end generate;
-gen_inputs_rj : if USE_RJADAPT = 1 generate
+gen_inputs_rj : if USE_BACKPLANE = 0 and USE_RJADAPT = 1 generate
cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0);
cts_addon_triggers_in(21 downto 2) <= INP(19 downto 0);
cts_addon_triggers_in(23 downto 22) <= trigger_gen_outputs_i when rising_edge(clk_sys);
+end generate;
+gen_inputs_bkpl : if USE_BACKPLANE = 1 generate
+ cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0);
+ cts_addon_triggers_in(33 downto 2) <= INP(31 downto 0);
+ cts_addon_triggers_in(35 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys);
+ gen_trg_inputs : for i in 0 to 8 generate
+ cts_addon_triggers_in(i*2+37 downto i*2+36) <= BACK_TRIG2(i) & BACK_TRIG1(i);
+ end generate;
+
end generate;
buscts_tx.nack <= '0';
PCSSW_EQ <= x"0";
PCSSW_PE <= x"F";
+---------------------------------------------------------------------------
+-- Backplane
+---------------------------------------------------------------------------
+gen_BKPL_OUT : if USE_BACKPLANE = c_YES generate
+ BACK_LVDS(0) <= clk_full;
+ BACK_LVDS(1) <= cts_trigger_out;
+end generate;
---------------------------------------------------------------------------
-- I/O
'1';
gen_leds_addon : if USE_ADDON = c_NO generate
LED_SFP_GREEN(1) <= not med2int(0).stat_op(9) when USE_BACKPLANE = 0 else
- '1';
+ med2int(9).stat_op(9);
LED_SFP_RED(1) <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11) or not med2int(0).stat_op(9)) when USE_BACKPLANE = 0 else
- '1';
+ (med2int(9).stat_op(10) or med2int(9).stat_op(11) or not med2int(9).stat_op(9));
end generate;
-- LED_WHITE(0) <= not med2int(10).stat_op(9) when INCLUDE_GBE = 0 and USE_BACKPLANE = 1 else
-- not med2int(8).stat_op(9) when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else
jspc29 / trb3sc.git / commitdiff