use work.trb_net_std.all;\r
use work.trb_net_components.all;
use work.trb_net16_hub_func.all; \r
+use work.soda_components.all;
package soda_components is
- constant c_NOT_IN_SYNC : std_logic := '0'; -- byt2word allignment of soda
- constant c_IN_SYNC : std_logic := '1'; -- byt2word allignment of soda
+ constant c_PHASE_L : std_logic := '0'; -- byt2word allignment of soda
+ constant c_PHASE_H : std_logic := '1'; -- byt2word allignment of soda
constant c_HUB_CHILDREN : natural range 1 to 4 := 2; -- number of children per soda-hub\r
constant cSODA_CLOCK_PERIOD : natural range 1 to 20 := 5; -- soda clock-period in ns
constant cBURST_PERIOD : natural := 2400; -- particle-beam burst-period in ns\r
SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit
EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0');
TIME_CAL_OUT : out std_logic := '0'; --
+ TX_DLM_PREVIEW_OUT : out std_logic := '0'; --
TX_DLM_OUT : out std_logic := '0'; --
TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0')
);
RX_DLM_IN : in std_logic;
TX_DLM_OUT : out std_logic;
TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- TX_DLM_INIT_OUT : out std_logic := '0'; --PL!
+ TX_DLM_PREVIEW_OUT : out std_logic := '0'; --PL!
LINK_PHASE_IN : in std_logic := '0'; --PL!
RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
TX_DLM : in std_logic := '0';
TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";\r
- TX_DLM_INIT : in std_logic := '0'; --PL!\r
+ TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!\r
LINK_PHASE_OUT : out std_logic := '0'; --PL!
--SFP Connection
START_RETRANSMIT_IN : in std_logic := '0';
START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0');
--send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
- TX_DLM_INIT : in std_logic := '0';
+ TX_DLM_PREVIEW_IN : in std_logic := '0';
SEND_DLM : in std_logic := '0';
SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0');
SODA_CMD_WORD_IN : in std_logic_vector(30 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit\r
EXPECTED_REPLY_OUT : out std_logic_vector(7 downto 0) := (others => '0');
TIME_CAL_OUT : out std_logic := '0';
+ TX_DLM_PREVIEW_OUT : out std_logic := '0'; --
TX_DLM_OUT : out std_logic := '0'; --
TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0')\r
);\r
architecture Behavioral of soda_packet_builder is\r
signal soda_cmd_window_S : std_logic;
- signal soda_cmd_strobe_S : std_logic;
- signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator\r
+-- signal soda_cmd_strobe_S : std_logic;
+-- signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator\r
signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0'); -- from slowcontrol\r
signal soda_pkt_word_S : std_logic_vector(7 downto 0) := (others => '0');\r
signal soda_pkt_valid_S : std_logic;\r
);\r
signal packet_state_S : packet_state_type := c_IDLE;\r
\r
+ signal soda_dlm_preview_S : std_logic;
signal soda_cmd_reg_full_S : std_logic;
signal soda_cmd_reg_S : std_logic_vector(31 downto 0) := (others => '0'); -- from super-burst-nr-generator
\r
CRC_VALID_OUT => crc_valid_S
);
- soda_cmd_strobe_S <= SODA_CMD_STROBE_IN;
+-- soda_cmd_strobe_S <= SODA_CMD_STROBE_IN;
soda_cmd_word_S <= SODA_CMD_WORD_IN;\r
- super_burst_nr_S <= SUPER_BURST_NR_IN;
+-- super_burst_nr_S <= SUPER_BURST_NR_IN;
\r
- TX_DLM_WORD_OUT <= soda_pkt_word_S;\r
+ TX_DLM_PREVIEW_OUT <= '1' when (((LINK_PHASE_IN='1') and ((soda_dlm_preview_S='1') or (START_OF_SUPERBURST='1') or (SODA_CMD_STROBE_IN='1'))) or\r
+ ((LINK_PHASE_IN='0') and (soda_dlm_preview_S='1'))) \r
+ else '0';
+-- TX_DLM_PREVIEW_OUT <= soda_dlm_preview_S;
TX_DLM_OUT <= soda_pkt_valid_S;\r
+ TX_DLM_WORD_OUT <= soda_pkt_word_S;
\r
\r
packet_fsm_proc : process(SODACLK)\r
begin\r
if rising_edge(SODACLK) then\r
if (RESET='1') then\r
- packet_state_S <= c_IDLE;\r
+ packet_state_S <= c_IDLE;\r
+ soda_dlm_preview_S <= '0';
+ soda_pkt_valid_S <= '0';
+ soda_pkt_word_S <= (others => '0');
else\r
case packet_state_S is\r
when c_IDLE =>\r
if (START_OF_SUPERBURST='1') then
- if (LINK_PHASE_IN = c_IN_SYNC) then\r
+ soda_dlm_preview_S <= '1';
+ if (LINK_PHASE_IN = c_PHASE_H) then\r
packet_state_S <= c_BST1;
soda_pkt_valid_S <= '1';
- soda_pkt_word_S <= '1' & super_burst_nr_S(30 downto 24);
+ soda_pkt_word_S <= '1' & SUPER_BURST_NR_IN(30 downto 24);
else
packet_state_S <= c_WAIT4BST1;
soda_pkt_valid_S <= '0';
end if;\r
- elsif (soda_cmd_strobe_S='1') then\r
- if (LINK_PHASE_IN = c_IN_SYNC) then\r
+ elsif (SODA_CMD_STROBE_IN='1') then\r
+ soda_dlm_preview_S <= '1';
+ if (LINK_PHASE_IN = c_PHASE_H) then\r
packet_state_S <= c_CMD1;\r
soda_pkt_valid_S <= '1';
soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);
end if;\r
when c_WAIT4BST1 =>\r
packet_state_S <= c_BST1;
+ soda_dlm_preview_S <= '1';
soda_pkt_valid_S <= '1';
- soda_pkt_word_S <= '1' & super_burst_nr_S(30 downto 24);
+ soda_pkt_word_S <= '1' & SUPER_BURST_NR_IN(30 downto 24);
when c_BST1 =>\r
packet_state_S <= c_BST2;\r
soda_pkt_valid_S <= '0';
when c_BST2 =>\r
packet_state_S <= c_BST3;\r
soda_pkt_valid_S <= '1';
- soda_pkt_word_S <= super_burst_nr_S(23 downto 16);
+ soda_pkt_word_S <= SUPER_BURST_NR_IN(23 downto 16);
when c_BST3 =>\r
packet_state_S <= c_BST4;\r
soda_pkt_valid_S <= '0';
when c_BST4 =>\r
packet_state_S <= c_BST5;\r
soda_pkt_valid_S <= '1';
- soda_pkt_word_S <= super_burst_nr_S(15 downto 8);
+ soda_pkt_word_S <= SUPER_BURST_NR_IN(15 downto 8);
when c_BST5 =>\r
packet_state_S <= c_BST6;\r
soda_pkt_valid_S <= '0';
when c_BST6 =>\r
packet_state_S <= c_BST7;\r
soda_pkt_valid_S <= '1';
- soda_pkt_word_S <= super_burst_nr_S(7 downto 0);
+ soda_pkt_word_S <= SUPER_BURST_NR_IN(7 downto 0);
when c_BST7 =>\r
packet_state_S <= c_BST8;\r
+ soda_dlm_preview_S <= '0';
soda_pkt_valid_S <= '0';
when c_BST8 =>\r
- if (soda_cmd_strobe_S='0') then\r
+ if (SODA_CMD_STROBE_IN='0') then\r
+ soda_dlm_preview_S <= '0';
packet_state_S <= c_IDLE;\r
else\r
- packet_state_S <= c_CMD1;\r
+ soda_dlm_preview_S <= '1';
+ packet_state_S <= c_CMD1;\r
end if;\r
- soda_pkt_valid_S <= '0';
- soda_pkt_word_S <= (others=>'0');
+ soda_pkt_valid_S <= '0';
+ soda_pkt_word_S <= (others=>'0');
when c_WAIT4CMD1 =>\r
packet_state_S <= c_CMD1;\r
+ soda_dlm_preview_S <= '1';
soda_pkt_valid_S <= '1';
soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);
when c_CMD1 =>\r
packet_state_S <= c_CMD2;\r
+ soda_dlm_preview_S <= '1';
soda_pkt_valid_S <= '0';
when c_CMD2 =>\r
packet_state_S <= c_CMD3;\r
else
packet_state_S <= c_CMD8;\r
end if;\r
+ soda_dlm_preview_S <= '0';
soda_pkt_valid_S <= '0';
when c_CMD8 =>
packet_state_S <= c_IDLE;\r
+ soda_dlm_preview_S <= '0';
soda_pkt_valid_S <= '0';
soda_pkt_word_S <= (others=>'0');
when c_ERROR =>
packet_state_S <= c_IDLE;\r
+ soda_dlm_preview_S <= '0';
soda_pkt_valid_S <= '0';
when others =>\r
packet_state_S <= c_IDLE;\r
+ soda_dlm_preview_S <= '0';
soda_pkt_valid_S <= '0';
end case;\r
end if;\r
end if;\r
end process;\r
\r
- soda_cmd_reg_proc : process(SODACLK)\r
- begin\r
- if rising_edge(SODACLK) then\r
- if (RESET='1') then\r
- soda_cmd_reg_full_S <= '0';\r
- soda_cmd_reg_S <= (others => '0');\r
- elsif (soda_pkt_valid_S = '1') then\r
- soda_cmd_reg_full_S <= '1';
- soda_cmd_reg_S <= '0' & soda_cmd_word_S;
-
- end if;\r
- end if;
- end process;\r
-\r
-\r
- --soda_packet_fill_proc : process(SODACLK, packet_state_S)\r
- --begin\r
- --if rising_edge(SODACLK) then\r
- --case packet_state_S is\r
- --when c_IDLE =>\r
- --TIME_CAL_OUT <= '0';\r
- --soda_pkt_valid_S <= '0';\r
- --soda_pkt_word_S <= (others=>'0');\r
- --when c_WAIT4BST1 => -- no need to do anything just yet.\r
- --when c_BST1 =>\r
- --soda_pkt_valid_S <= '1';\r
- --soda_pkt_word_S <= '1' & super_burst_nr_S(30 downto 24);\r
- --when c_BST2 =>\r
- --soda_pkt_valid_S <= '0';\r
- --when c_BST3 =>\r
- --soda_pkt_valid_S <= '1';\r
- --soda_pkt_word_S <= super_burst_nr_S(23 downto 16);\r
- --when c_BST4 =>\r
- --soda_pkt_valid_S <= '0';\r
- --when c_BST5 =>\r
- --soda_pkt_valid_S <= '1';\r
- --soda_pkt_word_S <= super_burst_nr_S(15 downto 8);\r
- --when c_BST6 =>\r
- --soda_pkt_valid_S <= '0';\r
- --when c_BST7 =>\r
- --soda_pkt_valid_S <= '1';\r
- --soda_pkt_word_S <= super_burst_nr_S(7 downto 0);\r
- --EXPECTED_REPLY_OUT <= super_burst_nr_S(7 downto 0);\r
- --when c_BST8 =>\r
- --soda_pkt_valid_S <= '0';\r
- --when c_WAIT4CMD1 => -- no need to do anything just yet.\r
- --when c_CMD1 =>\r
- --soda_pkt_valid_S <= '1';\r
- --soda_pkt_word_S <= '0' & soda_cmd_word_S(30 downto 24);\r
- --when c_CMD2 =>\r
- --soda_pkt_valid_S <= '0';\r
- --when c_CMD3 =>\r
- --soda_pkt_valid_S <= '1';\r
- --soda_pkt_word_S <= soda_cmd_word_S(23 downto 16);\r
- --when c_CMD4 =>\r
- --soda_pkt_valid_S <= '0';\r
- --when c_CMD5 =>\r
- --soda_pkt_valid_S <= '1';\r
- --soda_pkt_word_S <= soda_cmd_word_S(15 downto 8);\r
- --when c_CMD6 =>\r
- --soda_pkt_valid_S <= '0';\r
- --when c_CMD7 =>\r
- --soda_pkt_valid_S <= '1';\r
- --soda_pkt_word_S <= crc_out_S;
- --EXPECTED_REPLY_OUT <= crc_out_S;
- --TIME_CAL_OUT <= '1';\r
- --when c_CMD8 =>
- --TIME_CAL_OUT <= '0';\r
- --soda_pkt_valid_S <= '0';\r
- --when others =>\r
- --TIME_CAL_OUT <= '0';\r
- --soda_pkt_valid_S <= '0';\r
- --soda_pkt_word_S <= (others=>'0');\r
- --end case; \r
- --end if;\r
- --end process;\r
+-- soda_cmd_reg_proc : process(SODACLK)\r
+-- begin\r
+-- if rising_edge(SODACLK) then\r
+-- if (RESET='1') then\r
+-- soda_cmd_reg_full_S <= '0';\r
+-- soda_cmd_reg_S <= (others => '0');\r
+-- elsif (soda_pkt_valid_S = '1') then\r
+-- soda_cmd_reg_full_S <= '1';
+-- soda_cmd_reg_S <= '0' & soda_cmd_word_S;
+--
+-- end if;\r
+-- end if;
+-- end process;\r
\r
\r
crc_gen_proc : process(SODACLK, packet_state_S)\r
end if;\r
end process;
\r
+\r
cmd_window_gen : soda_cmd_window_generator
generic map(CLOCK_PERIOD => cSODA_CLOCK_PERIOD, -- clock-period in ns
COMMAND_WINDOS_SIZE => cSODA_COMMAND_WINDOS_SIZE -- command window size in ns
RX_DLM_IN : in std_logic;
TX_DLM_OUT : out std_logic;
TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
- TX_DLM_INIT_OUT : out std_logic := '0'; --PL!
+ TX_DLM_PREVIEW_OUT : out std_logic := '0'; --PL!
LINK_PHASE_IN : in std_logic := '0'; --PL!
SODA_DATA_IN : in std_logic_vector(31 downto 0) := (others => '0');
SUPER_BURST_NR_IN => super_burst_nr_S,
SODA_CMD_WORD_IN => soda_cmd_word_S,
EXPECTED_REPLY_OUT => expected_reply_S,
- TIME_CAL_OUT => start_calibration_S,
+ TIME_CAL_OUT => start_calibration_S,\r
+ TX_DLM_PREVIEW_OUT => TX_DLM_PREVIEW_OUT,
TX_DLM_OUT => TX_DLM_OUT,
TX_DLM_WORD_OUT => TX_DLM_WORD_OUT
);
end process;
\r
\r
-\r
------------------------------------------------------------
--- TX_DLM_INIT for media-interface transmissions --
------------------------------------------------------------
- tx_dlm_init_proc : process (SODACLK, start_of_superburst_S, soda_cmd_strobe_S)\r
- begin\r
- if( RESET = '1' ) then \r
- TX_DLM_INIT_OUT <= '0';\r
- elsif ((start_of_superburst_S='1' or soda_cmd_strobe_sodaclk_S='1') and LINK_PHASE_IN=c_IN_SYNC) then\r
- TX_DLM_INIT_OUT <= '1';\r
- elsif rising_edge(SODACLK) then\r
- if (start_of_superburst_S='1' or soda_cmd_strobe_sodaclk_S='1') then
- TX_DLM_INIT_OUT <= '1';\r
- else\r
- TX_DLM_INIT_OUT <= '0';
- end if;\r
- end if;\r
- end process;
-\r
- \r
-\r
------------------------------------------------------------
--- Phase fsm for 16-bit transmissions --
------------------------------------------------------------
--- phase_fsm_proc : process(SODACLK)
--- begin
--- if rising_edge(SODACLK) then
--- if( RESET = '1' ) then
--- link_phase_S <= '0'; -- (0 => '1', others => '0');
--- elsif (link_phase_S='0') then
--- link_phase_S <= '1';
--- else
--- link_phase_S <= '0'; --(others => '0');
--- end if;
--- end if;
--- end process;
-
---------------------------------------------------------
-- RegIO Statemachine
---------------------------------------------------------