-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity soda_tx_control is
- port(
- CLK_200 : in std_logic;
- CLK_100 : in std_logic;
- RESET_IN : in std_logic;
-
- TX_DATA_IN : in std_logic_vector(15 downto 0);
- TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);
- TX_WRITE_IN : in std_logic;
- TX_READ_OUT : out std_logic;
-
- TX_DATA_OUT : out std_logic_vector( 7 downto 0);
- TX_K_OUT : out std_logic;
-
- REQUEST_RETRANSMIT_IN : in std_logic := '0';
- REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0');
-
- START_RETRANSMIT_IN : in std_logic := '0';
- START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0');
- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
- TX_DLM_PREVIEW_IN : in std_logic := '0';
- SEND_DLM : in std_logic := '0';
- SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0');
-
- SEND_LINK_RESET_IN : in std_logic := '0';
- TX_ALLOW_IN : in std_logic := '0';
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.med_sync_define.all;\r
+use work.soda_components.all;\r
+\r
+entity soda_tx_control is\r
+ port(\r
+ CLK_200 : in std_logic;\r
+ CLK_100 : in std_logic;\r
+ RESET_IN : in std_logic;\r
+\r
+ TX_DATA_IN : in std_logic_vector(15 downto 0);\r
+ TX_PACKET_NUMBER_IN : in std_logic_vector(2 downto 0);\r
+ TX_WRITE_IN : in std_logic;\r
+ TX_READ_OUT : out std_logic;\r
+\r
+ TX_DATA_OUT : out std_logic_vector( 7 downto 0);\r
+ TX_K_OUT : out std_logic;\r
+\r
+ REQUEST_RETRANSMIT_IN : in std_logic := '0';\r
+ REQUEST_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0');\r
+\r
+ START_RETRANSMIT_IN : in std_logic := '0';\r
+ START_POSITION_IN : in std_logic_vector( 7 downto 0) := (others => '0');\r
+ --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM\r
+ TX_DLM_PREVIEW_IN : in std_logic := '0';\r
+ SEND_DLM : in std_logic := '0';\r
+ SEND_DLM_WORD : in std_logic_vector( 7 downto 0) := (others => '0');\r
+ \r
+ SEND_LINK_RESET_IN : in std_logic := '0';\r
+ TX_ALLOW_IN : in std_logic := '0';\r
RX_ALLOW_IN : in std_logic := '0';\r
- LINK_PHASE_OUT : out std_logic := '0';
-
- DEBUG_OUT : out std_logic_vector(31 downto 0);
- STAT_REG_OUT : out std_logic_vector(31 downto 0)
- );
-end entity;
-
-
-
-architecture arch of soda_tx_control is
-
-
- type state_t is (SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, SEND_DLM_L, SEND_DLM_H,
- SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H,
- SEND_RESET, SEND_CHKSUM_L, SEND_CHKSUM_H); -- gk 05.10.10
- signal current_state : state_t;
-
- type ram_t is array(0 to 255) of std_logic_vector(17 downto 0);
- signal ram : ram_t;
+ LINK_PHASE_OUT : out std_logic := '0';\r
+\r
+ DEBUG_OUT : out std_logic_vector(31 downto 0);\r
+ STAT_REG_OUT : out std_logic_vector(31 downto 0)\r
+ );\r
+end entity;\r
+\r
+\r
+\r
+architecture arch of soda_tx_control is\r
+\r
+ attribute syn_hier : string;\r
+ attribute syn_hier of arch : architecture is "hard";\r
+\r
+ type state_t is (SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, SEND_DLM_L, SEND_DLM_H,\r
+ SEND_START_L, SEND_START_H, SEND_REQUEST_L, SEND_REQUEST_H,\r
+ SEND_RESET, SEND_CHKSUM_L, SEND_CHKSUM_H); -- gk 05.10.10\r
+ signal current_state : state_t;\r
+ \r
+ type ram_t is array(0 to 255) of std_logic_vector(17 downto 0);\r
+ signal ram : ram_t;\r
\r
signal link_phase_S : std_logic := '0';\r
-
- signal ram_write : std_logic := '0';
- signal ram_write_addr : unsigned(7 downto 0) := (others => '0');
- signal ram_read : std_logic := '0';
- signal ram_read_addr : unsigned(7 downto 0) := (others => '0');
- signal ram_dout : std_logic_vector(17 downto 0);
- signal next_ram_dout : std_logic_vector(17 downto 0);
- signal ram_fill_level : unsigned(7 downto 0);
- signal ram_empty : std_logic;
- signal ram_afull : std_logic;
-
- signal request_position_q : std_logic_vector( 7 downto 0);
- signal restart_position_q : std_logic_vector( 7 downto 0);
- signal request_position_i : std_logic_vector( 7 downto 0);
- signal restart_position_i : std_logic_vector( 7 downto 0);
- signal make_request_i : std_logic;
- signal make_restart_i : std_logic;
- signal load_read_pointer_i : std_logic;
--- signal SEND_DLM : std_logic;
- signal send_dlm_word_S : std_logic_vector( 7 downto 0); --PL!
- signal send_dlm_i : std_logic;
- signal start_retransmit_i : std_logic;
- signal request_retransmit_i : std_logic;
-
- signal buf_tx_read_out : std_logic;
- signal tx_data_200 : std_logic_vector(17 downto 0);
- signal tx_allow_qtx : std_logic;
- signal rx_allow_qtx : std_logic;
- signal tx_allow_q : std_logic;
- signal send_link_reset_qtx : std_logic;
- signal ct_fifo_empty : std_logic;
- signal ct_fifo_write : std_logic := '0';
- signal ct_fifo_read : std_logic := '0';
- signal ct_fifo_full : std_logic;
- signal ct_fifo_afull : std_logic;
- signal ct_fifo_reset : std_logic;
- signal last_ct_fifo_empty : std_logic;
- signal last_ct_fifo_read : std_logic;
- signal debug_sending_dlm : std_logic;
-
- -- gk 05.10.10
- signal save_sop : std_logic;
- signal save_eop : std_logic;
- signal load_sop : std_logic;
- signal load_eop : std_logic;
- signal crc_reset : std_logic;
- signal crc_q : std_logic_vector(7 downto 0);
- signal crc_en : std_logic;
- signal crc_data : std_logic_vector(7 downto 0);
-
-begin
-
-----------------------------------------------------------------------
--- Clock Domain Transfer
-----------------------------------------------------------------------
--- gk 05.10.10
- THE_CT_FIFO : lattice_ecp3_fifo_18x16_dualport_oreg
- port map(
- Data(15 downto 0) => TX_DATA_IN,
- Data(16) => save_sop,
- Data(17) => save_eop,
- WrClock => CLK_100,
- RdClock => CLK_200,
- WrEn => ct_fifo_write,
- RdEn => ct_fifo_read,
- Reset => ct_fifo_reset,
- RPReset => ct_fifo_reset,
- Q(17 downto 0) => tx_data_200,
- Empty => ct_fifo_empty,
- Full => ct_fifo_full,
- AlmostFull => ct_fifo_afull
- );
-
- THE_RD_PROC : process(CLK_100)
- begin
- if rising_edge(CLK_100) then
- buf_tx_read_out <= tx_allow_q and not ct_fifo_afull ;
- end if;
- end process;
-
- ct_fifo_reset <= not tx_allow_qtx;
- TX_READ_OUT <= buf_tx_read_out;
-
- ct_fifo_write <= buf_tx_read_out and TX_WRITE_IN;
- ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty;
-
- last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_200);
- last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_200);
-
- save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0';
- save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0';
-
-----------------------------------------------------------------------
--- RAM
-----------------------------------------------------------------------
-
-
- THE_RAM_WR_PROC : process(CLK_200, RESET_IN)
- begin
- if RESET_IN = '1' then
- ram_write <= '0';
- elsif rising_edge(CLK_200) then
- ram_write <= last_ct_fifo_read and not last_ct_fifo_empty;
- end if;
- end process;
-
---RAM
- THE_RAM_PROC : process(CLK_200)
- begin
- if rising_edge(CLK_200) then
- if ram_write = '1' then
- ram((to_integer(ram_write_addr))) <= tx_data_200;
- end if;
- next_ram_dout <= ram(to_integer(ram_read_addr));
- ram_dout <= next_ram_dout;
- end if;
- end process;
-
---RAM read pointer
- THE_READ_CNT : process(CLK_200, RESET_IN)
- begin
- if RESET_IN = '1' then
- ram_read_addr <= (others => '0');
- elsif rising_edge(CLK_200) then
- if tx_allow_qtx = '0' then
- ram_read_addr <= (others => '0');
- elsif load_read_pointer_i = '1' then
- ram_read_addr <= unsigned(restart_position_i);
- elsif ram_read = '1' then
- ram_read_addr <= ram_read_addr + to_unsigned(1,1);
- end if;
- end if;
- end process;
-
---RAM write pointer
- THE_WRITE_CNT : process(CLK_200, RESET_IN)
- begin
- if RESET_IN = '1' then
- ram_write_addr <= (others => '0');
- elsif rising_edge(CLK_200) then
- if tx_allow_qtx = '0' then
- ram_write_addr <= (others => '0');
- elsif ram_write = '1' then
- ram_write_addr <= ram_write_addr + to_unsigned(1,1);
- end if;
- end if;
- end process;
-
-
---RAM fill level counter
- THE_FILL_CNT : process(CLK_200, RESET_IN)
- begin
- if RESET_IN = '1' then
- ram_fill_level <= (others => '0');
- elsif rising_edge(CLK_200) then
- if tx_allow_qtx = '0' then
- ram_fill_level <= (others => '0');
- else
- ram_fill_level <= ram_write_addr - ram_read_addr;
- end if;
- end if;
- end process;
-
-
---RAM empty
--- ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN;
- ram_empty <= '1' when (ram_write_addr = ram_read_addr) or RESET_IN = '1' else '0';
- ram_afull <= '1' when ram_fill_level >= 4 else '0';
-
-
-
-----------------------------------------------------------------------
--- TX control state machine
-----------------------------------------------------------------------
-
- THE_DATA_CONTROL_FSM : process(CLK_200, RESET_IN)
- begin
- if rising_edge(CLK_200) then
- TX_K_OUT <= '0';
- debug_sending_dlm <= '0';
- case current_state is
- when SEND_IDLE_L =>
- TX_DATA_OUT <= K_IDLE;
- TX_K_OUT <= '1';
- current_state <= SEND_IDLE_H;
-
- when SEND_IDLE_H =>
- if rx_allow_qtx = '1' then
- TX_DATA_OUT <= D_IDLE1;
- else
- TX_DATA_OUT <= D_IDLE0;
- end if;
-
- when SEND_DATA_L =>
- TX_DATA_OUT <= ram_dout(7 downto 0);
- load_sop <= ram_dout(16);
- load_eop <= ram_dout(17);
- current_state <= SEND_DATA_H;
-
- when SEND_DATA_H =>
- TX_DATA_OUT <= ram_dout(15 downto 8);
-
- when SEND_CHKSUM_L =>
- TX_DATA_OUT <= K_EOP;
- TX_K_OUT <= '1';
- load_sop <= '0';
- load_eop <= '0';
- current_state <= SEND_CHKSUM_H;
-
- when SEND_CHKSUM_H =>
- TX_DATA_OUT <= crc_q;
-
- when SEND_START_L =>
- TX_DATA_OUT <= K_BGN;
- TX_K_OUT <= '1';
- current_state <= SEND_START_H;
-
- when SEND_START_H =>
- TX_DATA_OUT <= std_logic_vector(ram_read_addr);
-
- when SEND_REQUEST_L =>
- TX_DATA_OUT <= K_REQ;
- TX_K_OUT <= '1';
- current_state <= SEND_REQUEST_H;
-
- when SEND_DLM_L =>
- TX_DATA_OUT <= K_DLM;
- TX_K_OUT <= '1';
- current_state <= SEND_DLM_H;
+\r
+ signal ram_write : std_logic := '0';\r
+ signal ram_write_addr : unsigned(7 downto 0) := (others => '0');\r
+ signal ram_read : std_logic := '0';\r
+ signal ram_read_addr : unsigned(7 downto 0) := (others => '0');\r
+ signal ram_dout : std_logic_vector(17 downto 0);\r
+ signal next_ram_dout : std_logic_vector(17 downto 0);\r
+ signal ram_fill_level : unsigned(7 downto 0);\r
+ signal ram_empty : std_logic;\r
+ signal ram_afull : std_logic;\r
+\r
+ signal request_position_q : std_logic_vector( 7 downto 0);\r
+ signal restart_position_q : std_logic_vector( 7 downto 0);\r
+ signal request_position_i : std_logic_vector( 7 downto 0);\r
+ signal restart_position_i : std_logic_vector( 7 downto 0);\r
+ signal make_request_i : std_logic;\r
+ signal make_restart_i : std_logic;\r
+ signal load_read_pointer_i : std_logic;\r
+-- signal SEND_DLM : std_logic;\r
+ signal send_dlm_word_S : std_logic_vector( 7 downto 0); --PL!\r
+ signal send_dlm_i : std_logic;\r
+ signal start_retransmit_i : std_logic;\r
+ signal request_retransmit_i : std_logic;\r
+\r
+ signal buf_tx_read_out : std_logic;\r
+ signal tx_data_200 : std_logic_vector(17 downto 0);\r
+ signal tx_allow_qtx : std_logic;\r
+ signal rx_allow_qtx : std_logic;\r
+ signal tx_allow_q : std_logic;\r
+ signal send_link_reset_qtx : std_logic;\r
+ signal ct_fifo_empty : std_logic;\r
+ signal ct_fifo_write : std_logic := '0';\r
+ signal ct_fifo_read : std_logic := '0';\r
+ signal ct_fifo_full : std_logic;\r
+ signal ct_fifo_afull : std_logic;\r
+ signal ct_fifo_reset : std_logic;\r
+ signal last_ct_fifo_empty : std_logic;\r
+ signal last_ct_fifo_read : std_logic;\r
+ signal debug_sending_dlm : std_logic;\r
+\r
+ -- gk 05.10.10\r
+ signal save_sop : std_logic;\r
+ signal save_eop : std_logic;\r
+ signal load_sop : std_logic;\r
+ signal load_eop : std_logic;\r
+ signal crc_reset : std_logic;\r
+ signal crc_q : std_logic_vector(7 downto 0);\r
+ signal crc_en : std_logic;\r
+ signal crc_data : std_logic_vector(7 downto 0);\r
+\r
+begin\r
+\r
+----------------------------------------------------------------------\r
+-- Clock Domain Transfer\r
+----------------------------------------------------------------------\r
+-- gk 05.10.10\r
+ THE_CT_FIFO : lattice_ecp3_fifo_18x16_dualport_oreg\r
+ port map(\r
+ Data(15 downto 0) => TX_DATA_IN,\r
+ Data(16) => save_sop,\r
+ Data(17) => save_eop,\r
+ WrClock => CLK_100,\r
+ RdClock => CLK_200,\r
+ WrEn => ct_fifo_write,\r
+ RdEn => ct_fifo_read,\r
+ Reset => ct_fifo_reset,\r
+ RPReset => ct_fifo_reset,\r
+ Q(17 downto 0) => tx_data_200,\r
+ Empty => ct_fifo_empty,\r
+ Full => ct_fifo_full,\r
+ AlmostFull => ct_fifo_afull\r
+ );\r
+\r
+ THE_RD_PROC : process(CLK_100)\r
+ begin\r
+ if rising_edge(CLK_100) then\r
+ buf_tx_read_out <= tx_allow_q and not ct_fifo_afull ;\r
+ end if;\r
+ end process;\r
+\r
+ ct_fifo_reset <= not tx_allow_qtx;\r
+ TX_READ_OUT <= buf_tx_read_out;\r
+\r
+ ct_fifo_write <= buf_tx_read_out and TX_WRITE_IN;\r
+ ct_fifo_read <= tx_allow_qtx and not ram_afull and not ct_fifo_empty;\r
+ \r
+ last_ct_fifo_read <= ct_fifo_read when rising_edge(CLK_200);\r
+ last_ct_fifo_empty <= ct_fifo_empty when rising_edge(CLK_200);\r
+ \r
+ save_sop <= '1' when (TX_PACKET_NUMBER_IN = c_H0) else '0';\r
+ save_eop <= '1' when (TX_PACKET_NUMBER_IN = c_F3) else '0';\r
+\r
+----------------------------------------------------------------------\r
+-- RAM\r
+----------------------------------------------------------------------\r
+\r
+\r
+ THE_RAM_WR_PROC : process(CLK_200, RESET_IN)\r
+ begin\r
+ if RESET_IN = '1' then\r
+ ram_write <= '0';\r
+ elsif rising_edge(CLK_200) then\r
+ ram_write <= last_ct_fifo_read and not last_ct_fifo_empty;\r
+ end if;\r
+ end process;\r
+\r
+--RAM\r
+ THE_RAM_PROC : process(CLK_200)\r
+ begin\r
+ if rising_edge(CLK_200) then\r
+ if ram_write = '1' then\r
+ ram((to_integer(ram_write_addr))) <= tx_data_200;\r
+ end if;\r
+ next_ram_dout <= ram(to_integer(ram_read_addr));\r
+ ram_dout <= next_ram_dout;\r
+ end if;\r
+ end process;\r
+\r
+--RAM read pointer\r
+ THE_READ_CNT : process(CLK_200, RESET_IN)\r
+ begin\r
+ if RESET_IN = '1' then\r
+ ram_read_addr <= (others => '0');\r
+ elsif rising_edge(CLK_200) then\r
+ if tx_allow_qtx = '0' then\r
+ ram_read_addr <= (others => '0');\r
+ elsif load_read_pointer_i = '1' then\r
+ ram_read_addr <= unsigned(restart_position_i);\r
+ elsif ram_read = '1' then\r
+ ram_read_addr <= ram_read_addr + to_unsigned(1,1);\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+--RAM write pointer\r
+ THE_WRITE_CNT : process(CLK_200, RESET_IN)\r
+ begin\r
+ if RESET_IN = '1' then\r
+ ram_write_addr <= (others => '0');\r
+ elsif rising_edge(CLK_200) then\r
+ if tx_allow_qtx = '0' then\r
+ ram_write_addr <= (others => '0');\r
+ elsif ram_write = '1' then\r
+ ram_write_addr <= ram_write_addr + to_unsigned(1,1);\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+\r
+--RAM fill level counter\r
+ THE_FILL_CNT : process(CLK_200, RESET_IN)\r
+ begin\r
+ if RESET_IN = '1' then\r
+ ram_fill_level <= (others => '0');\r
+ elsif rising_edge(CLK_200) then\r
+ if tx_allow_qtx = '0' then\r
+ ram_fill_level <= (others => '0');\r
+ else\r
+ ram_fill_level <= ram_write_addr - ram_read_addr;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+\r
+--RAM empty\r
+-- ram_empty <= not or_all(std_logic_vector(ram_write_addr) xor std_logic_vector(ram_read_addr)) and not RESET_IN;\r
+ ram_empty <= '1' when (ram_write_addr = ram_read_addr) or RESET_IN = '1' else '0';\r
+ ram_afull <= '1' when ram_fill_level >= 4 else '0';\r
+\r
+\r
+\r
+----------------------------------------------------------------------\r
+-- TX control state machine\r
+----------------------------------------------------------------------\r
+\r
+ THE_DATA_CONTROL_FSM : process(CLK_200, RESET_IN)\r
+ begin\r
+ if rising_edge(CLK_200) then\r
+ TX_K_OUT <= '0';\r
+ debug_sending_dlm <= '0';\r
+ case current_state is\r
+ when SEND_IDLE_L =>\r
+ TX_DATA_OUT <= K_IDLE;\r
+ TX_K_OUT <= '1';\r
+ current_state <= SEND_IDLE_H;\r
+\r
+ when SEND_IDLE_H =>\r
+ if rx_allow_qtx = '1' then\r
+ TX_DATA_OUT <= D_IDLE1;\r
+ else\r
+ TX_DATA_OUT <= D_IDLE0;\r
+ end if;\r
+\r
+ when SEND_DATA_L =>\r
+ TX_DATA_OUT <= ram_dout(7 downto 0);\r
+ load_sop <= ram_dout(16);\r
+ load_eop <= ram_dout(17);\r
+ current_state <= SEND_DATA_H;\r
+\r
+ when SEND_DATA_H =>\r
+ TX_DATA_OUT <= ram_dout(15 downto 8);\r
+\r
+ when SEND_CHKSUM_L =>\r
+ TX_DATA_OUT <= K_EOP;\r
+ TX_K_OUT <= '1';\r
+ load_sop <= '0';\r
+ load_eop <= '0';\r
+ current_state <= SEND_CHKSUM_H;\r
+\r
+ when SEND_CHKSUM_H =>\r
+ TX_DATA_OUT <= crc_q;\r
+\r
+ when SEND_START_L =>\r
+ TX_DATA_OUT <= K_BGN;\r
+ TX_K_OUT <= '1';\r
+ current_state <= SEND_START_H;\r
+\r
+ when SEND_START_H =>\r
+ TX_DATA_OUT <= std_logic_vector(ram_read_addr);\r
+\r
+ when SEND_REQUEST_L =>\r
+ TX_DATA_OUT <= K_REQ;\r
+ TX_K_OUT <= '1';\r
+ current_state <= SEND_REQUEST_H;\r
+\r
+ when SEND_DLM_L =>\r
+ TX_DATA_OUT <= K_DLM;\r
+ TX_K_OUT <= '1';\r
+ current_state <= SEND_DLM_H;\r
+ debug_sending_dlm <= '1';\r
+ send_dlm_word_S <= SEND_DLM_WORD; --PL!\r
+ \r
+ when SEND_DLM_H =>\r
+ TX_DATA_OUT <= send_dlm_word_S; --SEND_DLM_WORD;\r
debug_sending_dlm <= '1';\r
- send_dlm_word_S <= SEND_DLM_WORD; --PL!
-
- when SEND_DLM_H =>
- TX_DATA_OUT <= send_dlm_word_S; --SEND_DLM_WORD;
- debug_sending_dlm <= '1';
-
- when SEND_REQUEST_H =>
- TX_DATA_OUT <= request_position_i;
-
- when SEND_RESET =>
- TX_DATA_OUT <= K_RST;
- TX_K_OUT <= '1';
- if send_link_reset_qtx = '0' then
- current_state <= SEND_IDLE_L;
- end if;
-
- when others =>
- current_state <= SEND_IDLE_L;
- end case;
-
- if current_state = SEND_START_H or current_state = SEND_IDLE_H or
- current_state = SEND_DATA_H or current_state = SEND_DLM_H or
+ \r
+ when SEND_REQUEST_H =>\r
+ TX_DATA_OUT <= request_position_i;\r
+\r
+ when SEND_RESET =>\r
+ TX_DATA_OUT <= K_RST;\r
+ TX_K_OUT <= '1';\r
+ if send_link_reset_qtx = '0' then\r
+ current_state <= SEND_IDLE_L;\r
+ end if;\r
+\r
+ when others =>\r
+ current_state <= SEND_IDLE_L;\r
+ end case;\r
+\r
+ if current_state = SEND_START_H or current_state = SEND_IDLE_H or\r
+ current_state = SEND_DATA_H or current_state = SEND_DLM_H or\r
current_state = SEND_REQUEST_H or current_state = SEND_CHKSUM_H\r
then\r
- link_phase_S <= c_PHASE_L;
- if tx_allow_qtx = '0' then
- current_state <= SEND_IDLE_L;
- elsif send_link_reset_qtx = '1' then
- current_state <= SEND_RESET;
- elsif make_request_i = '1' then
- current_state <= SEND_REQUEST_L;
- elsif make_restart_i = '1' then
- current_state <= SEND_START_L;
- -- elsif send_dlm_i = '1' then
- elsif (TX_DLM_PREVIEW_IN='1') then --PL!
- current_state <= SEND_DLM_L;
- elsif ram_empty = '0' then
- current_state <= SEND_DATA_L;
- else
- current_state <= SEND_IDLE_L;
- end if;
+ link_phase_S <= c_PHASE_L; \r
+ if tx_allow_qtx = '0' then\r
+ current_state <= SEND_IDLE_L;\r
+ elsif send_link_reset_qtx = '1' then\r
+ current_state <= SEND_RESET;\r
+ elsif make_request_i = '1' then\r
+ current_state <= SEND_REQUEST_L;\r
+ elsif make_restart_i = '1' then\r
+ current_state <= SEND_START_L;\r
+ -- elsif send_dlm_i = '1' then\r
+ elsif (TX_DLM_PREVIEW_IN='1') then --PL!\r
+ current_state <= SEND_DLM_L;\r
+ elsif ram_empty = '0' then\r
+ current_state <= SEND_DATA_L;\r
+ else\r
+ current_state <= SEND_IDLE_L;\r
+ end if;\r
else\r
- link_phase_S <= c_PHASE_H;
- end if;
- end if;
+ link_phase_S <= c_PHASE_H;\r
+ end if;\r
+ end if;\r
--------------------------\r
--async because of oreg.--\r
---------------------------
- if (current_state = SEND_START_H or current_state = SEND_IDLE_H or current_state = SEND_DATA_H or
+--------------------------\r
+ if (current_state = SEND_START_H or current_state = SEND_IDLE_H or current_state = SEND_DATA_H or\r
current_state = SEND_DLM_H or current_state = SEND_REQUEST_H or current_state = SEND_CHKSUM_H) and\r
- ram_empty = '0' and tx_allow_qtx = '1' and send_link_reset_qtx = '0' and make_request_i = '0' and make_restart_i = '0' and send_dlm_i = '0' then
- ram_read <= '1';
- else
- ram_read <= '0';
- end if;
+ ram_empty = '0' and tx_allow_qtx = '1' and send_link_reset_qtx = '0' and make_request_i = '0' and make_restart_i = '0' and send_dlm_i = '0' then\r
+ ram_read <= '1';\r
+ else \r
+ ram_read <= '0';\r
+ end if;\r
\r
- if RESET_IN = '1' then
- ram_read <= '0';
- end if;
-end process;
-\r
-LINK_PHASE_OUT <= link_phase_S;
-----------------------------------------------------------------------
---
-----------------------------------------------------------------------
-
-tx_allow_qtx <= TX_ALLOW_IN when rising_edge(CLK_200);
-rx_allow_qtx <= RX_ALLOW_IN when rising_edge(CLK_200);
-
-send_link_reset_qtx <= SEND_LINK_RESET_IN when rising_edge(CLK_200);
-tx_allow_q <= tx_allow_qtx when rising_edge(CLK_100);
-
- THE_RETRANSMIT_PULSE_SYNC_1 : pulse_sync
- port map(
- CLK_A_IN => CLK_100,
- RESET_A_IN => RESET_IN,
- PULSE_A_IN => REQUEST_RETRANSMIT_IN,
- CLK_B_IN => CLK_200,
- RESET_B_IN => RESET_IN,
- PULSE_B_OUT => request_retransmit_i
- );
-
- THE_RETRANSMIT_PULSE_SYNC_2 : pulse_sync
- port map(
- CLK_A_IN => CLK_100,
- RESET_A_IN => RESET_IN,
- PULSE_A_IN => START_RETRANSMIT_IN,
- CLK_B_IN => CLK_200,
- RESET_B_IN => RESET_IN,
- PULSE_B_OUT => start_retransmit_i
- );
-
--- THE_RETRANSMIT_PULSE_SYNC_3 : pulse_sync
--- port map(
--- CLK_A_IN => CLK_100,
--- RESET_A_IN => RESET_IN,
--- PULSE_A_IN => SEND_DLM,
--- CLK_B_IN => CLK_200,
--- RESET_B_IN => RESET_IN,
--- PULSE_B_OUT => SEND_DLM
--- );
--- SEND_DLM <= SEND_DLM;
-
- THE_POSITION_REG : process(CLK_100)
- begin
- if rising_edge(CLK_100) then
- if REQUEST_RETRANSMIT_IN = '1' then
- request_position_q <= REQUEST_POSITION_IN;
- end if;
- if START_RETRANSMIT_IN = '1' then
- restart_position_q <= START_POSITION_IN;
- end if;
- end if;
- end process;
-
-
---Store Request Retransmit position
- THE_STORE_REQUEST_PROC : process(CLK_200, RESET_IN)
- begin
- if RESET_IN = '1' then
- make_request_i <= '0';
- request_position_i <= (others => '0');
- elsif rising_edge(CLK_200) then
- if tx_allow_qtx = '0' then
- make_request_i <= '0';
- request_position_i <= (others => '0');
- elsif request_retransmit_i = '1' then
- make_request_i <= '1';
- request_position_i <= request_position_q;
- elsif current_state = SEND_REQUEST_L then
- make_request_i <= '0';
- elsif current_state = SEND_REQUEST_H then
- request_position_i <= (others => '0');
- end if;
- end if;
- end process;
-
-
---Store Restart position
- THE_STORE_RESTART_PROC : process(CLK_200, RESET_IN)
- begin
- if RESET_IN = '1' then
- make_restart_i <= '0';
- restart_position_i <= (others => '0');
- elsif rising_edge(CLK_200) then
- if tx_allow_qtx = '0' then
- make_restart_i <= '0';
- restart_position_i <= (others => '0');
- elsif start_retransmit_i = '1' then
- make_restart_i <= '1';
- restart_position_i <= restart_position_q;
- elsif current_state = SEND_START_L then
- make_restart_i <= '0';
- elsif current_state = SEND_START_H then
- restart_position_i <= (others => '0');
- end if;
- end if;
- end process;
-
---Store DLM position
- THE_STORE_DLM_PROC : process(CLK_200, RESET_IN)
- begin
- if RESET_IN = '1' then
- send_dlm_i <= '0';
- elsif rising_edge(CLK_200) then
- if tx_allow_qtx = '0' then
- send_dlm_i <= '0';
- elsif SEND_DLM = '1' then
- send_dlm_i <= '1';
--- elsif current_state = SEND_DLM_L then -- PL!
- else
- send_dlm_i <= '0';
- end if;
- end if;
- end process;
-
- load_read_pointer_i <= '1' when current_state = SEND_START_L else '0';
-
- -- gk 05.10.10
- crc_reset <= '1' when ((RESET_IN = '1') or (current_state = SEND_CHKSUM_H) or (current_state = SEND_START_H)) else '0';
- crc_en <= '1' when ((current_state = SEND_DATA_L) or (current_state = SEND_DATA_H)) else '0';
- crc_data <= ram_dout(15 downto 8) when (current_state = SEND_DATA_H) else ram_dout(7 downto 0);
-
- -- gk 05.10.10
- CRC_CALC : trb_net_CRC8
- port map(
- CLK => CLK_200,
- RESET => crc_reset,
- CLK_EN => crc_en,
- DATA_IN => crc_data,
- CRC_OUT => crc_q,
- CRC_match => open
- );
-
-
-----------------------------------------------------------------------
--- Debug
-----------------------------------------------------------------------
- DEBUG_OUT(0) <= ram_read;
- DEBUG_OUT(1) <= ct_fifo_write;
- DEBUG_OUT(2) <= ct_fifo_read;
- DEBUG_OUT(3) <= tx_allow_qtx;
- DEBUG_OUT(4) <= ram_empty;
- DEBUG_OUT(5) <= ram_afull;
- DEBUG_OUT(6) <= debug_sending_dlm when rising_edge(CLK_200);
- DEBUG_OUT(31 downto 7) <= (others => '0');
-
- process(CLK_100)
- begin
- if rising_edge(CLK_100) then
- STAT_REG_OUT(7 downto 0) <= std_logic_vector(ram_fill_level);
- STAT_REG_OUT(15 downto 8) <= std_logic_vector(ram_read_addr);
- STAT_REG_OUT(16) <= ram_afull;
- STAT_REG_OUT(17) <= ram_empty;
- STAT_REG_OUT(18) <= tx_allow_qtx;
- STAT_REG_OUT(19) <= TX_ALLOW_IN;
- STAT_REG_OUT(20) <= make_restart_i;
- STAT_REG_OUT(21) <= make_request_i;
- STAT_REG_OUT(22) <= load_eop;
- STAT_REG_OUT(31 downto 23) <= (others => '0');
- end if;
- end process;
-
-
-
-
+ if RESET_IN = '1' then\r
+ ram_read <= '0';\r
+ end if;\r
+end process;\r
+\r
+LINK_PHASE_OUT <= link_phase_S;\r
+----------------------------------------------------------------------\r
+--\r
+----------------------------------------------------------------------\r
+\r
+tx_allow_qtx <= TX_ALLOW_IN when rising_edge(CLK_200);\r
+rx_allow_qtx <= RX_ALLOW_IN when rising_edge(CLK_200);\r
+\r
+send_link_reset_qtx <= SEND_LINK_RESET_IN when rising_edge(CLK_200);\r
+tx_allow_q <= tx_allow_qtx when rising_edge(CLK_100);\r
+\r
+ THE_RETRANSMIT_PULSE_SYNC_1 : pulse_sync\r
+ port map(\r
+ CLK_A_IN => CLK_100,\r
+ RESET_A_IN => RESET_IN,\r
+ PULSE_A_IN => REQUEST_RETRANSMIT_IN,\r
+ CLK_B_IN => CLK_200,\r
+ RESET_B_IN => RESET_IN,\r
+ PULSE_B_OUT => request_retransmit_i\r
+ );\r
+\r
+ THE_RETRANSMIT_PULSE_SYNC_2 : pulse_sync\r
+ port map(\r
+ CLK_A_IN => CLK_100,\r
+ RESET_A_IN => RESET_IN,\r
+ PULSE_A_IN => START_RETRANSMIT_IN,\r
+ CLK_B_IN => CLK_200,\r
+ RESET_B_IN => RESET_IN,\r
+ PULSE_B_OUT => start_retransmit_i\r
+ );\r
+\r
+-- THE_RETRANSMIT_PULSE_SYNC_3 : pulse_sync\r
+-- port map(\r
+-- CLK_A_IN => CLK_100,\r
+-- RESET_A_IN => RESET_IN,\r
+-- PULSE_A_IN => SEND_DLM,\r
+-- CLK_B_IN => CLK_200,\r
+-- RESET_B_IN => RESET_IN,\r
+-- PULSE_B_OUT => SEND_DLM\r
+-- ); \r
+-- SEND_DLM <= SEND_DLM;\r
+ \r
+ THE_POSITION_REG : process(CLK_100)\r
+ begin\r
+ if rising_edge(CLK_100) then\r
+ if REQUEST_RETRANSMIT_IN = '1' then\r
+ request_position_q <= REQUEST_POSITION_IN;\r
+ end if;\r
+ if START_RETRANSMIT_IN = '1' then\r
+ restart_position_q <= START_POSITION_IN;\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+\r
+--Store Request Retransmit position\r
+ THE_STORE_REQUEST_PROC : process(CLK_200, RESET_IN)\r
+ begin\r
+ if RESET_IN = '1' then\r
+ make_request_i <= '0';\r
+ request_position_i <= (others => '0');\r
+ elsif rising_edge(CLK_200) then\r
+ if tx_allow_qtx = '0' then\r
+ make_request_i <= '0';\r
+ request_position_i <= (others => '0');\r
+ elsif request_retransmit_i = '1' then\r
+ make_request_i <= '1';\r
+ request_position_i <= request_position_q;\r
+ elsif current_state = SEND_REQUEST_L then\r
+ make_request_i <= '0';\r
+ elsif current_state = SEND_REQUEST_H then\r
+ request_position_i <= (others => '0');\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+\r
+--Store Restart position\r
+ THE_STORE_RESTART_PROC : process(CLK_200, RESET_IN)\r
+ begin\r
+ if RESET_IN = '1' then\r
+ make_restart_i <= '0';\r
+ restart_position_i <= (others => '0');\r
+ elsif rising_edge(CLK_200) then\r
+ if tx_allow_qtx = '0' then\r
+ make_restart_i <= '0';\r
+ restart_position_i <= (others => '0');\r
+ elsif start_retransmit_i = '1' then\r
+ make_restart_i <= '1';\r
+ restart_position_i <= restart_position_q;\r
+ elsif current_state = SEND_START_L then\r
+ make_restart_i <= '0';\r
+ elsif current_state = SEND_START_H then\r
+ restart_position_i <= (others => '0');\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+--Store DLM position\r
+ THE_STORE_DLM_PROC : process(CLK_200, RESET_IN)\r
+ begin\r
+ if RESET_IN = '1' then\r
+ send_dlm_i <= '0';\r
+ elsif rising_edge(CLK_200) then\r
+ if tx_allow_qtx = '0' then\r
+ send_dlm_i <= '0';\r
+ elsif SEND_DLM = '1' then\r
+ send_dlm_i <= '1';\r
+-- elsif current_state = SEND_DLM_L then -- PL!\r
+ else\r
+ send_dlm_i <= '0';\r
+ end if;\r
+ end if;\r
+ end process; \r
+ \r
+ load_read_pointer_i <= '1' when current_state = SEND_START_L else '0';\r
+\r
+ -- gk 05.10.10\r
+ crc_reset <= '1' when ((RESET_IN = '1') or (current_state = SEND_CHKSUM_H) or (current_state = SEND_START_H)) else '0';\r
+ crc_en <= '1' when ((current_state = SEND_DATA_L) or (current_state = SEND_DATA_H)) else '0';\r
+ crc_data <= ram_dout(15 downto 8) when (current_state = SEND_DATA_H) else ram_dout(7 downto 0);\r
+\r
+ -- gk 05.10.10\r
+ CRC_CALC : trb_net_CRC8\r
+ port map(\r
+ CLK => CLK_200,\r
+ RESET => crc_reset,\r
+ CLK_EN => crc_en,\r
+ DATA_IN => crc_data,\r
+ CRC_OUT => crc_q,\r
+ CRC_match => open\r
+ );\r
+\r
+\r
+----------------------------------------------------------------------\r
+-- Debug\r
+----------------------------------------------------------------------\r
+ DEBUG_OUT(0) <= ram_read;\r
+ DEBUG_OUT(1) <= ct_fifo_write;\r
+ DEBUG_OUT(2) <= ct_fifo_read;\r
+ DEBUG_OUT(3) <= tx_allow_qtx;\r
+ DEBUG_OUT(4) <= ram_empty;\r
+ DEBUG_OUT(5) <= ram_afull;\r
+ DEBUG_OUT(6) <= debug_sending_dlm when rising_edge(CLK_200);\r
+ DEBUG_OUT(31 downto 7) <= (others => '0');\r
+\r
+ process(CLK_100)\r
+ begin\r
+ if rising_edge(CLK_100) then\r
+ STAT_REG_OUT(7 downto 0) <= std_logic_vector(ram_fill_level);\r
+ STAT_REG_OUT(15 downto 8) <= std_logic_vector(ram_read_addr);\r
+ STAT_REG_OUT(16) <= ram_afull;\r
+ STAT_REG_OUT(17) <= ram_empty;\r
+ STAT_REG_OUT(18) <= tx_allow_qtx;\r
+ STAT_REG_OUT(19) <= TX_ALLOW_IN;\r
+ STAT_REG_OUT(20) <= make_restart_i;\r
+ STAT_REG_OUT(21) <= make_request_i;\r
+ STAT_REG_OUT(22) <= load_eop;\r
+ STAT_REG_OUT(31 downto 23) <= (others => '0');\r
+ end if;\r
+ end process;\r
+\r
+\r
+\r
+\r
end architecture;
\ No newline at end of file
----------------
--- TOP LEVEL --
----------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_sodahub is
- generic(
- SYNC_MODE : integer range 0 to 1 := c_YES; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_NO;
- CLOCK_FREQUENCY : integer := 100;
- NUM_INTERFACES : integer := 6 + 1 -- This is the number of SERDES's in use: 1 copper trb-upstream + 6 to ADDONboard
- );
- port(
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
-
- --serdes I/O - connect as you like, no real use
- SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
-
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0);
- --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
- --others yet undefined
- --Connection to AddOn
- LED_LINKOK : out std_logic_vector(6 downto 1);
- LED_RX : out std_logic_vector(6 downto 1);
- LED_TX : out std_logic_vector(6 downto 1);
- SFP_MOD0 : in std_logic_vector(6 downto 1);
- SFP_TXDIS : out std_logic_vector(6 downto 1);
- SFP_LOS : in std_logic_vector(6 downto 1);
- SFP_MOD1 : inout std_logic_vector(6 downto 1); --H!
- SFP_MOD2 : inout std_logic_vector(6 downto 1); --H!
- --SFP_RATESEL : out std_logic_vector(6 downto 1);
- --SFP_TXFAULT : in std_logic_vector(6 downto 1);
-
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
-
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
-
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-end entity trb3_periph_sodahub;
-
-
-architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 2; --0; H!
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
-
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa
-
- --Clock / Reset
- -- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
--- signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
- -- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal downlink_clear : std_logic;
- signal downlink_reset : std_logic;
- signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
- signal clk_100_osc : std_logic;
--- signal clk_raw_internal : std_logic;
- signal clk_200_osc : std_logic;
-
- signal rxup_half_clk : std_logic;
- signal rxup_full_clk : std_logic;
- signal txup_half_clk : std_logic;
- signal txup_full_clk : std_logic;
- signal rx_cdr_lol_S : std_logic;
-
- signal rxdn_half_clk : t_HUB_BIT;
- signal rxdn_full_clk : t_HUB_BIT;
- signal txdn_half_clk : t_HUB_BIT;
- signal txdn_full_clk : t_HUB_BIT;
-
--- signal clk_tdc : std_logic;
- signal time_counter, time_counter2 : unsigned(31 downto 0);
- --Media Interface
- signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');
- signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');
- signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0');
- signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0');
- signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');
- signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0');
- signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');
- signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');
- signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');
- signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0');
- signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');
- signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
- --media interface
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
- signal sci1_nack : std_logic;
-
- signal sci2_ack : std_logic;
- signal sci2_nack : std_logic;
- signal sci2_write : std_logic;
- signal sci2_read : std_logic;
- signal sci2_data_in : std_logic_vector(7 downto 0);
- signal sci2_data_out : std_logic_vector(7 downto 0);
- signal sci2_addr : std_logic_vector(8 downto 0);
-
- signal sfp_mod0_B : t_QUAD_BIT := (others => '0');
- signal sfp_los_B : t_QUAD_BIT := (others => '0');
- signal sfp_txdis_B : t_QUAD_BIT := (others => '0');
-
-
- --SODA
- signal make_reset : std_logic;
-
- --SODA uplink
- signal txup_dlm_i : std_logic;
- signal rxup_dlm_i : std_logic;
- signal txup_dlm_word : std_logic_vector(7 downto 0);
- signal rxup_dlm_word : std_logic_vector(7 downto 0);
- signal txup_dlm_preview_S : std_logic; --PL!
- signal uplink_phase_S : std_logic; --PL!
- signal uplink_ready_S : std_logic; --PL!
- signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
-
- --SODA downlink
- signal txdn_dlm_i : t_HUB_BIT;
- signal rxdn_dlm_i : t_HUB_BIT;
- signal txdn_dlm_word : t_HUB_BYTE;
- signal rxdn_dlm_word : t_HUB_BYTE;
- signal txdn_dlm_preview_S : t_HUB_BIT; --PL!
- signal dnlink_phase_S : t_HUB_BIT; --PL!
-
- -- SODA slow controll
- signal soda_ack : std_logic;
--- signal soda_nack : std_logic;
- signal soda_write : std_logic;
- signal soda_read : std_logic;
- signal soda_data_in : std_logic_vector(31 downto 0);
- signal soda_data_out : std_logic_vector(31 downto 0);
- signal soda_addr : std_logic_vector(3 downto 0);
- signal soda_leds : std_logic_vector(3 downto 0);
-
- signal link_debug_in_S : std_logic_vector(31 downto 0);
- signal general_reset_i : std_logic := '1';
-
- signal soda_counter_i : unsigned(3 downto 0);
-
-
- attribute syn_keep of soda_counter_i : signal is true;
- -- fix signal names for constraining
- attribute syn_preserve of clk_100_osc : signal is true;
- attribute syn_keep of clk_100_osc : signal is true;
--- attribute syn_preserve of clk_raw_internal : signal is true;
--- attribute syn_keep of clk_raw_internal : signal is true;
--- attribute syn_preserve of clk_soda_i : signal is true;
--- attribute syn_keep of clk_soda_i : signal is true;
- attribute syn_preserve of txup_dlm_i : signal is true;
- attribute syn_keep of txup_dlm_i : signal is true;
- attribute syn_preserve of rxup_dlm_i : signal is true;
- attribute syn_keep of rxup_dlm_i : signal is true;
- attribute syn_preserve of txdn_dlm_i : signal is true;
- attribute syn_keep of txdn_dlm_i : signal is true;
- attribute syn_preserve of rxdn_dlm_i : signal is true;
- attribute syn_keep of rxdn_dlm_i : signal is true;
-
-
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
-
- TEST_LINE <= (others => '0'); -- otherwise it is floating
- LED_RX <= (others => '0'); -- otherwise it is floating
- LED_TX <= (others => '0'); -- otherwise it is floating
- LED_LINKOK <= (others => '0'); -- otherwise it is floating
-
- GSR_N <= pll_lock;
-\r
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => rxup_half_clk, --clk_100_osc, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => GSR_N, --pll_lock, -- master PLL lock signal (async) !PL 14082014
- RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
--- process(clk_100_osc)
--- begin
--- if rising_edge(clk_100_osc) then
--- general_reset_i <= not SFP_LOS(1);
--- end if;
--- end process;
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
---gen_200_PLL : if USE_125_MHZ = c_NO generate
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_osc,
- CLKOK => clk_200_osc,
- LOCK => pll_lock
- );
---end generate;
-
---gen_125 : if USE_125_MHZ = c_YES generate
--- clk_100_osc <= CLK_GPLL_LEFT;
--- clk_raw_internal <= CLK_GPLL_LEFT;
---end generate;
-
---gen_sync_clocks : if SYNC_MODE = c_YES generate
--- clk_soda_i <= rxup_full_clk;
---end generate;
-
---gen_local_clocks : if SYNC_MODE = c_NO generate
--- clk_soda_i <= clk_raw_internal;
---end generate;
-
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)
- )
- port map(
- CLK => rxup_half_clk, --clk_100_osc, --clk_sys_i,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_READ_ENABLE_OUT(1) => sci1_read,
- BUS_READ_ENABLE_OUT(2) => sci2_read,
- BUS_READ_ENABLE_OUT(3) => soda_read,
-
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_WRITE_ENABLE_OUT(1) => sci1_write,
- BUS_WRITE_ENABLE_OUT(2) => sci2_write,
- BUS_WRITE_ENABLE_OUT(3) => soda_write,
-
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
- BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,
- BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
- BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,
-
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
- BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,
- BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
- BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,
- BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
-
- BUS_TIMEOUT_OUT(0) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_TIMEOUT_OUT(3) => open,
-
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
- BUS_DATA_IN(1*32+31 downto 1*32+8) => (others => '0'),
- BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
- BUS_DATA_IN(2*32+31 downto 2*32+8) => (others => '0'),
- BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
-
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_DATAREADY_IN(1) => sci1_ack,
- BUS_DATAREADY_IN(2) => sci2_ack,
- BUS_DATAREADY_IN(3) => soda_ack,
-
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_WRITE_ACK_IN(1) => sci1_ack,
- BUS_WRITE_ACK_IN(2) => sci2_ack,
- BUS_WRITE_ACK_IN(3) => soda_ack,
-
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_NO_MORE_DATA_IN(3) => '0',
-
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => sci2_nack,
- BUS_UNKNOWN_ADDR_IN(3) => '0',
-
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
- port map(
- CLK_IN => rxup_half_clk, --clk_100_osc,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-
-
-
----------------------------------------------------------------------------
--- The synchronous interface for Soda tests
----------------------------------------------------------------------------
-
-THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up
- generic map(
- SERDES_NUM => 0, --number of serdes in quad
- IS_SYNC_SLAVE => c_YES
- )
- port map(
- OSCCLK => clk_200_osc,
- SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_sync_down.vhd
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection for TrbNet data -> not used a.t.m.
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
- RX_HALF_CLK_OUT => rxup_half_clk,
- RX_FULL_CLK_OUT => rxup_full_clk,
- TX_HALF_CLK_OUT => txup_half_clk,
+---------------\r
+-- TOP LEVEL --\r
+---------------\r
+\r
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb_net16_hub_func.all;\r
+use work.trb3_components.all; \r
+use work.soda_components.all;\r
+use work.med_sync_define.all;\r
+use work.version.all;\r
+\r
+entity trb3_periph_sodahub is\r
+ generic(\r
+ SYNC_MODE : integer range 0 to 1 := c_YES; --use the RX clock for internal logic and transmission. Should be NO for soda tests!\r
+ USE_125_MHZ : integer := c_NO;\r
+ CLOCK_FREQUENCY : integer := 100;\r
+ NUM_INTERFACES : integer := 6 + 1 -- This is the number of SERDES's in use: 1 copper trb-upstream + 6 to ADDONboard\r
+ );\r
+ port(\r
+ --Clocks \r
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz\r
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA\r
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!\r
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!\r
+\r
+\r
+ --serdes I/O - connect as you like, no real use\r
+ SERDES_ADDON_TX : out std_logic_vector(15 downto 0);\r
+ SERDES_ADDON_RX : in std_logic_vector(15 downto 0);\r
+\r
+ --Inter-FPGA Communication\r
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);\r
+ --Bit 0/1 input, serial link RX active\r
+ --Bit 2/3 output, serial link TX active\r
+ --others yet undefined\r
+ --Connection to AddOn\r
+ LED_LINKOK : out std_logic_vector(6 downto 1);\r
+ LED_RX : out std_logic_vector(6 downto 1);\r
+ LED_TX : out std_logic_vector(6 downto 1);\r
+ SFP_MOD0 : in std_logic_vector(6 downto 1);\r
+ SFP_TXDIS : out std_logic_vector(6 downto 1);\r
+ SFP_LOS : in std_logic_vector(6 downto 1);\r
+ SFP_MOD1 : inout std_logic_vector(6 downto 1); --H!\r
+ SFP_MOD2 : inout std_logic_vector(6 downto 1); --H!\r
+ --SFP_RATESEL : out std_logic_vector(6 downto 1);\r
+ --SFP_TXFAULT : in std_logic_vector(6 downto 1);\r
+\r
+ --Flash ROM & Reboot\r
+ FLASH_CLK : out std_logic;\r
+ FLASH_CS : out std_logic;\r
+ FLASH_DIN : out std_logic;\r
+ FLASH_DOUT : in std_logic;\r
+ PROGRAMN : out std_logic; --reboot FPGA\r
+\r
+ --Misc\r
+ TEMPSENS : inout std_logic; --Temperature Sensor\r
+ CODE_LINE : in std_logic_vector(1 downto 0);\r
+ LED_GREEN : out std_logic;\r
+ LED_ORANGE : out std_logic;\r
+ LED_RED : out std_logic;\r
+ LED_YELLOW : out std_logic;\r
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads\r
+\r
+ --Test Connectors\r
+ TEST_LINE : out std_logic_vector(15 downto 0)\r
+ );\r
+ \r
+ attribute syn_useioff : boolean;\r
+ --no IO-FF for LEDs relaxes timing constraints\r
+ attribute syn_useioff of SFP_LOS : signal is false;\r
+ attribute syn_useioff of SFP_TXDIS : signal is false;\r
+ attribute syn_useioff of SFP_MOD0 : signal is false;\r
+ attribute syn_useioff of LED_RX : signal is false;\r
+ attribute syn_useioff of LED_TX : signal is false;\r
+ attribute syn_useioff of LED_LINKOK : signal is false;\r
+\r
+\r
+ end entity trb3_periph_sodahub;\r
+\r
+\r
+architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is\r
+ --Constants\r
+ constant REGIO_NUM_STAT_REGS : integer := 2; --0; H!\r
+ constant REGIO_NUM_CTRL_REGS : integer := 2;\r
+\r
+\r
+ constant USE_200_MHZ : integer := 1 - USE_125_MHZ; -- if USE_125_MHZ=c_NO then USE_200_MHZ=c_YES and ViceVersa\r
+\r
+ --Clock / Reset\r
+ -- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL\r
+-- signal clk_soda_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL\r
+ -- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL\r
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.\r
+ signal clear_i : std_logic;\r
+ signal reset_i : std_logic;\r
+ signal downlink_clear : std_logic;\r
+ signal downlink_reset : std_logic;\r
+ signal GSR_N : std_logic;\r
+ attribute syn_keep of GSR_N : signal is true;\r
+ attribute syn_preserve of GSR_N : signal is true;\r
+ signal clk_100_osc : std_logic;\r
+-- signal clk_raw_internal : std_logic;\r
+ signal clk_200_osc : std_logic;\r
+\r
+ signal rxup_half_clk : std_logic;\r
+ signal rxup_full_clk : std_logic;\r
+ signal txup_half_clk : std_logic;\r
+ signal txup_full_clk : std_logic;\r
+ signal rx_cdr_lol_S : std_logic;\r
+\r
+ signal rxdn_half_clk : t_HUB_BIT;\r
+ signal rxdn_full_clk : t_HUB_BIT;\r
+ signal txdn_half_clk : t_HUB_BIT;\r
+ signal txdn_full_clk : t_HUB_BIT;\r
+\r
+-- signal clk_tdc : std_logic;\r
+ signal time_counter, time_counter2 : unsigned(31 downto 0);\r
+ --Media Interface\r
+ signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
+ signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
+ signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0');\r
+ signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0) := (others => '0');\r
+ signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
+ signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0');\r
+ signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
+ signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
+ signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0) := (others => '0');\r
+ signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0) := (others => '0');\r
+ signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
+ signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0) := (others => '0');\r
+\r
+ --Slow Control channel\r
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);\r
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);\r
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);\r
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);\r
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);\r
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);\r
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);\r
+\r
+ --RegIO\r
+ signal my_address : std_logic_vector (15 downto 0);\r
+ signal regio_addr_out : std_logic_vector (15 downto 0);\r
+ signal regio_read_enable_out : std_logic;\r
+ signal regio_write_enable_out : std_logic;\r
+ signal regio_data_out : std_logic_vector (31 downto 0);\r
+ signal regio_data_in : std_logic_vector (31 downto 0);\r
+ signal regio_dataready_in : std_logic;\r
+ signal regio_no_more_data_in : std_logic;\r
+ signal regio_write_ack_in : std_logic;\r
+ signal regio_unknown_addr_in : std_logic;\r
+ signal regio_timeout_out : std_logic;\r
+\r
+ --Timer\r
+ signal global_time : std_logic_vector(31 downto 0);\r
+ signal local_time : std_logic_vector(7 downto 0);\r
+ signal time_since_last_trg : std_logic_vector(31 downto 0);\r
+ signal timer_ticks : std_logic_vector(1 downto 0);\r
+\r
+ --Flash\r
+ signal spimem_read_en : std_logic;\r
+ signal spimem_write_en : std_logic;\r
+ signal spimem_data_in : std_logic_vector(31 downto 0);\r
+ signal spimem_addr : std_logic_vector(8 downto 0);\r
+ signal spimem_data_out : std_logic_vector(31 downto 0);\r
+ signal spimem_dataready_out : std_logic;\r
+ signal spimem_no_more_data_out : std_logic;\r
+ signal spimem_unknown_addr_out : std_logic;\r
+ signal spimem_write_ack_out : std_logic;\r
+\r
+ --media interface\r
+ signal sci1_ack : std_logic;\r
+ signal sci1_write : std_logic;\r
+ signal sci1_read : std_logic;\r
+ signal sci1_data_in : std_logic_vector(7 downto 0);\r
+ signal sci1_data_out : std_logic_vector(7 downto 0);\r
+ signal sci1_addr : std_logic_vector(8 downto 0); \r
+ signal sci1_nack : std_logic;\r
+ \r
+ signal sci2_ack : std_logic;\r
+ signal sci2_nack : std_logic;\r
+ signal sci2_write : std_logic;\r
+ signal sci2_read : std_logic;\r
+ signal sci2_data_in : std_logic_vector(7 downto 0);\r
+ signal sci2_data_out : std_logic_vector(7 downto 0);\r
+ signal sci2_addr : std_logic_vector(8 downto 0); \r
+\r
+ signal sfp_mod0_B : t_QUAD_BIT := (others => '0');\r
+ signal sfp_los_B : t_QUAD_BIT := (others => '0');\r
+ signal sfp_txdis_B : t_QUAD_BIT := (others => '0');\r
+\r
+\r
+ --SODA\r
+ signal make_reset : std_logic;\r
+\r
+ --SODA uplink\r
+ signal txup_dlm_i : std_logic;\r
+ signal rxup_dlm_i : std_logic;\r
+ signal txup_dlm_word : std_logic_vector(7 downto 0);\r
+ signal rxup_dlm_word : std_logic_vector(7 downto 0);\r
+ signal txup_dlm_preview_S : std_logic; --PL!\r
+ signal uplink_phase_S : std_logic; --PL!\r
+ signal uplink_ready_S : std_logic; --PL!\r
+ signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1'); \r
+\r
+ --SODA downlink\r
+ signal txdn_dlm_i : t_HUB_BIT;\r
+ signal rxdn_dlm_i : t_HUB_BIT;\r
+ signal txdn_dlm_word : t_HUB_BYTE;\r
+ signal rxdn_dlm_word : t_HUB_BYTE;\r
+ signal txdn_dlm_preview_S : t_HUB_BIT; --PL!\r
+ signal dnlink_phase_S : t_HUB_BIT; --PL!\r
+\r
+ -- SODA slow controll\r
+ signal soda_ack : std_logic;\r
+-- signal soda_nack : std_logic;\r
+ signal soda_write : std_logic;\r
+ signal soda_read : std_logic;\r
+ signal soda_data_in : std_logic_vector(31 downto 0);\r
+ signal soda_data_out : std_logic_vector(31 downto 0);\r
+ signal soda_addr : std_logic_vector(3 downto 0); \r
+ signal soda_leds : std_logic_vector(3 downto 0); \r
+\r
+ signal link_debug_in_S : std_logic_vector(31 downto 0);\r
+ signal general_reset_i : std_logic := '1';\r
+ \r
+ signal soda_counter_i : unsigned(3 downto 0);\r
+ \r
+\r
+ attribute syn_keep of soda_counter_i : signal is true;\r
+ -- fix signal names for constraining\r
+ attribute syn_preserve of clk_100_osc : signal is true;\r
+ attribute syn_keep of clk_100_osc : signal is true;\r
+-- attribute syn_preserve of clk_raw_internal : signal is true;\r
+-- attribute syn_keep of clk_raw_internal : signal is true;\r
+-- attribute syn_preserve of clk_soda_i : signal is true;\r
+-- attribute syn_keep of clk_soda_i : signal is true;\r
+ attribute syn_preserve of txup_dlm_i : signal is true;\r
+ attribute syn_keep of txup_dlm_i : signal is true;\r
+ attribute syn_preserve of rxup_dlm_i : signal is true;\r
+ attribute syn_keep of rxup_dlm_i : signal is true;\r
+ attribute syn_preserve of txdn_dlm_i : signal is true;\r
+ attribute syn_keep of txdn_dlm_i : signal is true;\r
+ attribute syn_preserve of rxdn_dlm_i : signal is true;\r
+ attribute syn_keep of rxdn_dlm_i : signal is true;\r
+\r
+ \r
+begin\r
+---------------------------------------------------------------------------\r
+-- Reset Generation\r
+---------------------------------------------------------------------------\r
+\r
+\r
+ TEST_LINE <= (others => '0'); -- otherwise it is floating\r
+-- LED_RX <= (others => '0'); -- otherwise it is floating\r
+-- LED_TX <= (others => '0'); -- otherwise it is floating\r
+-- LED_LINKOK <= (others => '0'); -- otherwise it is floating\r
+ \r
+ GSR_N <= pll_lock;\r
+\r
+\r
+ THE_RESET_HANDLER : trb_net_reset_handler\r
+ generic map(\r
+ RESET_DELAY => x"FEEE"\r
+ )\r
+ port map(\r
+ CLEAR_IN => '0', -- reset input (high active, async)\r
+ CLEAR_N_IN => '1', -- reset input (low active, async)\r
+ CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!\r
+ SYSCLK_IN => rxup_half_clk, --clk_100_osc, -- PLL/DLL remastered clock\r
+ PLL_LOCKED_IN => GSR_N, --pll_lock, -- master PLL lock signal (async) !PL 14082014\r
+ RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel\r
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)\r
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!\r
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)\r
+ DEBUG_OUT => open\r
+ ); \r
+\r
+-- process(clk_100_osc) \r
+-- begin\r
+-- if rising_edge(clk_100_osc) then\r
+-- general_reset_i <= not SFP_LOS(1);\r
+-- end if;\r
+-- end process;\r
+ \r
+---------------------------------------------------------------------------\r
+-- Clock Handling\r
+---------------------------------------------------------------------------\r
+--gen_200_PLL : if USE_125_MHZ = c_NO generate\r
+ THE_MAIN_PLL : pll_in200_out100\r
+ port map(\r
+ CLK => CLK_GPLL_RIGHT,\r
+ CLKOP => clk_100_osc,\r
+ CLKOK => clk_200_osc,\r
+ LOCK => pll_lock\r
+ );\r
+--end generate; \r
+\r
+--gen_125 : if USE_125_MHZ = c_YES generate\r
+-- clk_100_osc <= CLK_GPLL_LEFT;\r
+-- clk_raw_internal <= CLK_GPLL_LEFT;\r
+--end generate; \r
+\r
+--gen_sync_clocks : if SYNC_MODE = c_YES generate\r
+-- clk_soda_i <= rxup_full_clk;\r
+--end generate;\r
+\r
+--gen_local_clocks : if SYNC_MODE = c_NO generate\r
+-- clk_soda_i <= clk_raw_internal;\r
+--end generate;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Bus Handler\r
+---------------------------------------------------------------------------\r
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler\r
+ generic map(\r
+ PORT_NUMBER => 4,\r
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),\r
+ PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)\r
+ )\r
+ port map(\r
+ CLK => rxup_half_clk, --clk_100_osc, --clk_sys_i,\r
+ RESET => reset_i,\r
+\r
+ DAT_ADDR_IN => regio_addr_out,\r
+ DAT_DATA_IN => regio_data_out,\r
+ DAT_DATA_OUT => regio_data_in,\r
+ DAT_READ_ENABLE_IN => regio_read_enable_out,\r
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,\r
+ DAT_TIMEOUT_IN => regio_timeout_out,\r
+ DAT_DATAREADY_OUT => regio_dataready_in,\r
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,\r
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,\r
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,\r
+\r
+ BUS_READ_ENABLE_OUT(0) => spimem_read_en,\r
+ BUS_READ_ENABLE_OUT(1) => sci1_read,\r
+ BUS_READ_ENABLE_OUT(2) => sci2_read,\r
+ BUS_READ_ENABLE_OUT(3) => soda_read,\r
+\r
+ BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,\r
+ BUS_WRITE_ENABLE_OUT(1) => sci1_write,\r
+ BUS_WRITE_ENABLE_OUT(2) => sci2_write,\r
+ BUS_WRITE_ENABLE_OUT(3) => soda_write,\r
+\r
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,\r
+ BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,\r
+ BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,\r
+ BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,\r
+ BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,\r
+ BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,\r
+ \r
+ BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,\r
+ BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,\r
+ BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,\r
+ BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,\r
+ BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,\r
+ BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,\r
+ BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,\r
+ BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,\r
+ \r
+ BUS_TIMEOUT_OUT(0) => open,\r
+ BUS_TIMEOUT_OUT(1) => open,\r
+ BUS_TIMEOUT_OUT(2) => open,\r
+ BUS_TIMEOUT_OUT(3) => open,\r
+\r
+ BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,\r
+ BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,\r
+ BUS_DATA_IN(1*32+31 downto 1*32+8) => (others => '0'),\r
+ BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,\r
+ BUS_DATA_IN(2*32+31 downto 2*32+8) => (others => '0'),\r
+ BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,\r
+\r
+ BUS_DATAREADY_IN(0) => spimem_dataready_out,\r
+ BUS_DATAREADY_IN(1) => sci1_ack,\r
+ BUS_DATAREADY_IN(2) => sci2_ack,\r
+ BUS_DATAREADY_IN(3) => soda_ack,\r
+\r
+ BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,\r
+ BUS_WRITE_ACK_IN(1) => sci1_ack,\r
+ BUS_WRITE_ACK_IN(2) => sci2_ack,\r
+ BUS_WRITE_ACK_IN(3) => soda_ack,\r
+\r
+ BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,\r
+ BUS_NO_MORE_DATA_IN(1) => '0',\r
+ BUS_NO_MORE_DATA_IN(2) => '0',\r
+ BUS_NO_MORE_DATA_IN(3) => '0',\r
+ \r
+ BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,\r
+ BUS_UNKNOWN_ADDR_IN(1) => '0',\r
+ BUS_UNKNOWN_ADDR_IN(2) => sci2_nack,\r
+ BUS_UNKNOWN_ADDR_IN(3) => '0',\r
+\r
+ STAT_DEBUG => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- SPI / Flash\r
+---------------------------------------------------------------------------\r
+\r
+THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch\r
+ port map(\r
+ CLK_IN => rxup_half_clk, --clk_100_osc,\r
+ RESET_IN => reset_i,\r
+ \r
+ BUS_ADDR_IN => spimem_addr,\r
+ BUS_READ_IN => spimem_read_en,\r
+ BUS_WRITE_IN => spimem_write_en,\r
+ BUS_DATAREADY_OUT => spimem_dataready_out,\r
+ BUS_WRITE_ACK_OUT => spimem_write_ack_out,\r
+ BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,\r
+ BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,\r
+ BUS_DATA_IN => spimem_data_in,\r
+ BUS_DATA_OUT => spimem_data_out,\r
+ \r
+ DO_REBOOT_IN => common_ctrl_reg(15), \r
+ PROGRAMN => PROGRAMN,\r
+ \r
+ SPI_CS_OUT => FLASH_CS,\r
+ SPI_SCK_OUT => FLASH_CLK,\r
+ SPI_SDO_OUT => FLASH_DIN,\r
+ SPI_SDI_IN => FLASH_DOUT\r
+ );\r
+\r
+ \r
+\r
+---------------------------------------------------------------------------\r
+-- The synchronous interface for Soda tests\r
+--------------------------------------------------------------------------- \r
+\r
+THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up\r
+ generic map(\r
+ SERDES_NUM => 0, --number of serdes in quad\r
+ IS_SYNC_SLAVE => c_YES\r
+ )\r
+ port map(\r
+ OSCCLK => clk_200_osc,\r
+ SYSCLK => rxup_half_clk, --clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_sync_down.vhd\r
+ RESET => reset_i,\r
+ CLEAR => clear_i,\r
+ --Internal Connection for TrbNet data -> not used a.t.m.\r
+ MED_DATA_IN => med_data_out(15 downto 0),\r
+ MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),\r
+ MED_DATAREADY_IN => med_dataready_out(0),\r
+ MED_READ_OUT => med_read_in(0),\r
+ MED_DATA_OUT => med_data_in(15 downto 0),\r
+ MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),\r
+ MED_DATAREADY_OUT => med_dataready_in(0),\r
+ MED_READ_IN => med_read_out(0),\r
+ RX_HALF_CLK_OUT => rxup_half_clk,\r
+ RX_FULL_CLK_OUT => rxup_full_clk,\r
+ TX_HALF_CLK_OUT => txup_half_clk,\r
TX_FULL_CLK_OUT => txup_full_clk,\r
- RX_CDR_LOL_OUT => rx_cdr_lol_S, -- !PL 14082014
-
- RX_DLM => rxup_dlm_i,
- RX_DLM_WORD => rxup_dlm_word,
- TX_DLM => txup_dlm_i,
- TX_DLM_WORD => txup_dlm_word,
- TX_DLM_PREVIEW_IN => txup_dlm_preview_S, --PL!
- LINK_PHASE_OUT => uplink_phase_S, --PL!
- LINK_READY_OUT => uplink_ready_S, --PL!
- --SFP Connection -- PL!: these are for SIM-only !?! Makes no difference how they are connected; The ip-wizzard does the actual connecting
- SD_RXD_P_IN => SERDES_ADDON_RX(4),
- SD_RXD_N_IN => SERDES_ADDON_RX(5),
- SD_TXD_P_OUT => SERDES_ADDON_TX(4),
- SD_TXD_N_OUT => SERDES_ADDON_TX(5),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => SFP_MOD0(3), -- = A3, was 1 = B0
- SD_LOS_IN => SFP_LOS(3),
- SD_TXDIS_OUT => sfp_txdis_S(3), --SFP_TXDIS(3), this signal is now used to release downlinks
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- SCI_NACK => sci1_nack,
- -- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
-
- SFP_TXDIS <= sfp_txdis_S;
-
----------------------------------------------------------------------------
--- The Soda Central
----------------------------------------------------------------------------
-
- A_SODA_HUB : soda_hub
- port map(
- SYSCLK => rxup_half_clk,
- SODACLK => rxup_full_clk,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
-
- -- SINGLE DUBPLEX UP-LINK TO THE TOP
- RXUP_DLM_WORD_IN => rxup_dlm_word,
- RXUP_DLM_IN => rxup_dlm_i,
- TXUP_DLM_OUT => txup_dlm_i,
- TXUP_DLM_WORD_OUT => txup_dlm_word,
- TXUP_DLM_PREVIEW_OUT => txup_dlm_preview_S,
- UPLINK_PHASE_IN => uplink_phase_S,
- -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM
- RXDN_DLM_WORD_IN => rxdn_dlm_word,
- RXDN_DLM_IN => rxdn_dlm_i,
- TXDN_DLM_OUT => txdn_dlm_i,
- TXDN_DLM_WORD_OUT => txdn_dlm_word,
- TXDN_DLM_PREVIEW_OUT => txdn_dlm_preview_S,
- DNLINK_PHASE_IN => dnlink_phase_S,
-
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,
- LEDS_OUT => soda_leds,
- LINK_DEBUG_IN => link_debug_in_S
- );
-
-
- downlink_reset <= '1' when (reset_i = '1' or uplink_ready_S = '0') else '0';
- downlink_clear <= '1' when (clear_i = '1' or uplink_ready_S = '0') else '0';
-
-
- THE_HUB_SYNC_DOWNLINK : med_ecp3_sfp_4_sync_down
- generic map(
- SERDES_NUM => 0, --number of serdes in quad
- IS_SYNC_SLAVE => c_NO
- )
- port map(
- OSC_CLK => clk_200_osc,
- TX_DATACLK => rxup_full_clk,
- SYSCLK => clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd
- RESET => downlink_reset,
- CLEAR => downlink_clear,
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
- LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
- ---------------------------------------------------------------------------------------------------------------------------------------------------------
--- MED_DATA_IN(0*16+15 downto 0*16) => med_data_out(1*16+15 downto 1*16),
- MED_DATA_IN(0) => med_data_out(1*16+15 downto 1*16),
- MED_DATA_IN(1) => med_data_out(6*16+15 downto 6*16),
- MED_DATA_IN(2) => med_data_out(4*16+15 downto 4*16),
- MED_DATA_IN(3) => med_data_out(2*16+15 downto 2*16),
-
--- MED_PACKET_NUM_IN(0*3+2 downto 0*3) => med_packet_num_out(1*3+2 downto 1*3),
- MED_PACKET_NUM_IN(0) => med_packet_num_out(1*3+2 downto 1*3),
- MED_PACKET_NUM_IN(1) => med_packet_num_out(6*3+2 downto 6*3),
- MED_PACKET_NUM_IN(2) => med_packet_num_out(2*3+2 downto 2*3),
- MED_PACKET_NUM_IN(3) => med_packet_num_out(4*3+2 downto 4*3),
-
- MED_DATAREADY_IN(0) => med_dataready_out(1),
- MED_DATAREADY_IN(1) => med_dataready_out(6),
- MED_DATAREADY_IN(2) => med_dataready_out(2),
- MED_DATAREADY_IN(3) => med_dataready_out(4),
-
- MED_READ_OUT(0) => med_read_in(1),
- MED_READ_OUT(1) => med_read_in(6),
- MED_READ_OUT(2) => med_read_in(2),
- MED_READ_OUT(3) => med_read_in(4),
-
--- MED_DATA_OUT(0*16+15 downto 0*16) => med_data_in(1*16+15 downto 1*16),
- MED_DATA_OUT(0) => med_data_in(1*16+15 downto 1*16),
- MED_DATA_OUT(1) => med_data_in(6*16+15 downto 6*16),
- MED_DATA_OUT(2) => med_data_in(2*16+15 downto 2*16),
- MED_DATA_OUT(3) => med_data_in(4*16+15 downto 4*16),
-
--- MED_PACKET_NUM_OUT(0*3+2 downto 0*3) => med_packet_num_in(1*3+2 downto 1*3),
- MED_PACKET_NUM_OUT(0) => med_packet_num_in(1*3+2 downto 1*3),
- MED_PACKET_NUM_OUT(1) => med_packet_num_in(6*3+2 downto 6*3),
- MED_PACKET_NUM_OUT(2) => med_packet_num_in(2*3+2 downto 2*3),
- MED_PACKET_NUM_OUT(3) => med_packet_num_in(4*3+2 downto 4*3),
-
- MED_DATAREADY_OUT(0) => med_dataready_in(1),
- MED_DATAREADY_OUT(1) => med_dataready_in(6),
- MED_DATAREADY_OUT(2) => med_dataready_in(2),
- MED_DATAREADY_OUT(3) => med_dataready_in(4),
-
- MED_READ_IN(0) => med_read_out(1),
- MED_READ_IN(1) => med_read_out(6),
- MED_READ_IN(2) => med_read_out(2),
- MED_READ_IN(3) => med_read_out(4),
-
- RX_HALF_CLK_OUT(0) => rxdn_half_clk(0),
- RX_HALF_CLK_OUT(1) => rxdn_half_clk(1),
- RX_HALF_CLK_OUT(2) => rxdn_half_clk(2),
- RX_HALF_CLK_OUT(3) => rxdn_half_clk(3),
-
- RX_FULL_CLK_OUT(0) => rxdn_full_clk(0), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(1) => rxdn_full_clk(1), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(2) => rxdn_full_clk(2), -- needed for sync replies i.e. calibration
- RX_FULL_CLK_OUT(3) => rxdn_full_clk(3), -- needed for sync replies i.e. calibration
-
- TX_HALF_CLK_OUT(0) => txdn_half_clk(0),
- TX_HALF_CLK_OUT(1) => txdn_half_clk(1),
- TX_HALF_CLK_OUT(2) => txdn_half_clk(2),
- TX_HALF_CLK_OUT(3) => txdn_half_clk(3),
-
- TX_FULL_CLK_OUT(0) => txdn_full_clk(0),
- TX_FULL_CLK_OUT(1) => txdn_full_clk(1),
- TX_FULL_CLK_OUT(2) => txdn_full_clk(2),
- TX_FULL_CLK_OUT(3) => txdn_full_clk(3),
-
- RX_DLM(0) => rxdn_dlm_i(0),
- RX_DLM(1) => rxdn_dlm_i(1),
- RX_DLM(2) => rxdn_dlm_i(2),
- RX_DLM(3) => rxdn_dlm_i(3),
-
- RX_DLM_WORD(0) => rxdn_dlm_word(0),
- RX_DLM_WORD(1) => rxdn_dlm_word(1),
- RX_DLM_WORD(2) => rxdn_dlm_word(2),
- RX_DLM_WORD(3) => rxdn_dlm_word(3),
-
- TX_DLM(0) => txdn_dlm_i(0),
- TX_DLM(1) => txdn_dlm_i(1),
- TX_DLM(2) => txdn_dlm_i(2),
- TX_DLM(3) => txdn_dlm_i(3),
-
- TX_DLM_WORD(0) => txdn_dlm_word(0),
- TX_DLM_WORD(1) => txdn_dlm_word(1),
- TX_DLM_WORD(2) => txdn_dlm_word(2),
- TX_DLM_WORD(3) => txdn_dlm_word(3),
-
- TX_DLM_PREVIEW_IN(0) => txdn_dlm_preview_S(0), --PL!
- TX_DLM_PREVIEW_IN(1) => txdn_dlm_preview_S(1), --PL!
- TX_DLM_PREVIEW_IN(2) => txdn_dlm_preview_S(2), --PL!
- TX_DLM_PREVIEW_IN(3) => txdn_dlm_preview_S(3), --PL!
-
- LINK_PHASE_OUT(0) => dnlink_phase_S(0), --PL!
- LINK_PHASE_OUT(1) => dnlink_phase_S(1), --PL!
- LINK_PHASE_OUT(2) => dnlink_phase_S(2), --PL!
- LINK_PHASE_OUT(3) => dnlink_phase_S(3), --PL!
-
- --SFP Connection
- SD_RXD_P_IN(0) => SERDES_ADDON_RX(0), -- B0
- SD_RXD_P_IN(1) => SERDES_ADDON_RX(1),
- SD_RXD_P_IN(2) => SERDES_ADDON_RX(10), -- B1
- SD_RXD_P_IN(3) => SERDES_ADDON_RX(11),
- SD_RXD_N_IN(0) => SERDES_ADDON_RX(2), -- B2
- SD_RXD_N_IN(1) => SERDES_ADDON_RX(3),
- SD_RXD_N_IN(2) => SERDES_ADDON_RX(6), -- B3
- SD_RXD_N_IN(3) => SERDES_ADDON_RX(7),
- SD_TXD_P_OUT(0) => SERDES_ADDON_TX(0), -- B0
- SD_TXD_P_OUT(1) => SERDES_ADDON_TX(1),
- SD_TXD_P_OUT(2) => SERDES_ADDON_TX(10), -- B1
- SD_TXD_P_OUT(3) => SERDES_ADDON_TX(11),
- SD_TXD_N_OUT(0) => SERDES_ADDON_TX(2), -- B2
- SD_TXD_N_OUT(1) => SERDES_ADDON_TX(3),
- SD_TXD_N_OUT(2) => SERDES_ADDON_TX(6), -- B3
- SD_TXD_N_OUT(3) => SERDES_ADDON_TX(7),
- SD_REFCLK_P_IN => (others => '0'),
- SD_REFCLK_N_IN => ('0','0','0','0'),
- SD_PRSNT_N_IN(0) => SFP_MOD0(1),
- SD_PRSNT_N_IN(1) => SFP_MOD0(6),
- SD_PRSNT_N_IN(2) => SFP_MOD0(2),
- SD_PRSNT_N_IN(3) => SFP_MOD0(4),
- SD_LOS_IN(0) => SFP_LOS(1),
- SD_LOS_IN(1) => SFP_LOS(6),
- SD_LOS_IN(2) => SFP_LOS(2),
- SD_LOS_IN(3) => SFP_LOS(4),
- SD_TXDIS_OUT(0) => sfp_txdis_S(1),
- SD_TXDIS_OUT(1) => sfp_txdis_S(6),
- SD_TXDIS_OUT(2) => sfp_txdis_S(2),
- SD_TXDIS_OUT(3) => sfp_txdis_S(4),
-
- SCI_DATA_IN => sci2_data_in,
- SCI_DATA_OUT => sci2_data_out,
- SCI_ADDR => sci2_addr,
- SCI_READ => sci2_read,
- SCI_WRITE => sci2_write,
- SCI_ACK => sci2_ack,
- SCI_NACK => sci2_nack,
-
- --Status and control port
- STAT_OP(0) => med_stat_op(1*16+15 downto 1*16),
- STAT_OP(1) => med_stat_op(6*16+15 downto 6*16),
- STAT_OP(2) => med_stat_op(2*16+15 downto 2*16),
- STAT_OP(3) => med_stat_op(4*16+15 downto 4*16),
-
- CTRL_OP(0) => med_ctrl_op(1*16+15 downto 1*16),
- CTRL_OP(1) => med_ctrl_op(6*16+15 downto 6*16),
- CTRL_OP(2) => med_ctrl_op(2*16+15 downto 2*16),
- CTRL_OP(3) => med_ctrl_op(4*16+15 downto 4*16),
-
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
-
-
----------------------------------------------------------------------------
--- TRB-Hub
----------------------------------------------------------------------------
- med_stat_op(3*16+15 downto 3*16) <= x"0007"; -- !PL telling the hub that this port is inactive 08192014
+ RX_CDR_LOL_OUT => rx_cdr_lol_S, -- !PL 14082014 \r
+\r
+ RX_DLM => rxup_dlm_i,\r
+ RX_DLM_WORD => rxup_dlm_word,\r
+ TX_DLM => txup_dlm_i,\r
+ TX_DLM_WORD => txup_dlm_word,\r
+ TX_DLM_PREVIEW_IN => txup_dlm_preview_S, --PL!\r
+ LINK_PHASE_OUT => uplink_phase_S, --PL!\r
+ LINK_READY_OUT => uplink_ready_S, --PL!\r
+ --SFP Connection -- PL!: these are for SIM-only !?! Makes no difference how they are connected; The ip-wizzard does the actual connecting\r
+ SD_RXD_P_IN => SERDES_ADDON_RX(4),\r
+ SD_RXD_N_IN => SERDES_ADDON_RX(5),\r
+ SD_TXD_P_OUT => SERDES_ADDON_TX(4),\r
+ SD_TXD_N_OUT => SERDES_ADDON_TX(5),\r
+ SD_REFCLK_P_IN => '0',\r
+ SD_REFCLK_N_IN => '0',\r
+ SD_PRSNT_N_IN => SFP_MOD0(3), -- = A3, was 1 = B0\r
+ SD_LOS_IN => SFP_LOS(3),\r
+ SD_TXDIS_OUT => sfp_txdis_S(3), --SFP_TXDIS(3), this signal is now used to release downlinks\r
+\r
+ SCI_DATA_IN => sci1_data_in,\r
+ SCI_DATA_OUT => sci1_data_out,\r
+ SCI_ADDR => sci1_addr,\r
+ SCI_READ => sci1_read,\r
+ SCI_WRITE => sci1_write,\r
+ SCI_ACK => sci1_ack, \r
+ SCI_NACK => sci1_nack,\r
+ -- Status and control port\r
+ STAT_OP => med_stat_op(15 downto 0),\r
+ CTRL_OP => med_ctrl_op(15 downto 0),\r
+ STAT_DEBUG => open,\r
+ CTRL_DEBUG => (others => '0')\r
+ ); \r
+\r
+ SFP_TXDIS <= sfp_txdis_S;\r
+ \r
+---------------------------------------------------------------------------\r
+-- The Soda Central \r
+--------------------------------------------------------------------------- \r
+\r
+ A_SODA_HUB : soda_hub\r
+ port map(\r
+ SYSCLK => rxup_half_clk,\r
+ SODACLK => rxup_full_clk,\r
+ RESET => reset_i,\r
+ CLEAR => clear_i,\r
+ CLK_EN => '1',\r
+\r
+ -- SINGLE DUBPLEX UP-LINK TO THE TOP\r
+ RXUP_DLM_WORD_IN => rxup_dlm_word,\r
+ RXUP_DLM_IN => rxup_dlm_i,\r
+ TXUP_DLM_OUT => txup_dlm_i, \r
+ TXUP_DLM_WORD_OUT => txup_dlm_word,\r
+ TXUP_DLM_PREVIEW_OUT => txup_dlm_preview_S,\r
+ UPLINK_PHASE_IN => uplink_phase_S,\r
+ -- MULTIPLE DUPLEX DOWN-LINKS TO THE BOTTOM\r
+ RXDN_DLM_WORD_IN => rxdn_dlm_word,\r
+ RXDN_DLM_IN => rxdn_dlm_i,\r
+ TXDN_DLM_OUT => txdn_dlm_i, \r
+ TXDN_DLM_WORD_OUT => txdn_dlm_word,\r
+ TXDN_DLM_PREVIEW_OUT => txdn_dlm_preview_S,\r
+ DNLINK_PHASE_IN => dnlink_phase_S, \r
+\r
+ SODA_DATA_IN => soda_data_in,\r
+ SODA_DATA_OUT => soda_data_out,\r
+ SODA_ADDR_IN => soda_addr,\r
+ SODA_READ_IN => soda_read,\r
+ SODA_WRITE_IN => soda_write,\r
+ SODA_ACK_OUT => soda_ack,\r
+ LEDS_OUT => soda_leds,\r
+ LINK_DEBUG_IN => link_debug_in_S\r
+ );\r
+\r
+\r
+ downlink_reset <= '1' when (reset_i = '1' or uplink_ready_S = '0') else '0';\r
+ downlink_clear <= '1' when (clear_i = '1' or uplink_ready_S = '0') else '0';\r
+\r
+ \r
+ THE_HUB_SYNC_DOWNLINK : med_ecp3_sfp_4_sync_down\r
+ generic map(\r
+ SERDES_NUM => 0, --number of serdes in quad\r
+ IS_SYNC_SLAVE => c_NO\r
+ )\r
+ port map(\r
+ OSC_CLK => clk_200_osc,\r
+ TX_DATACLK => rxup_full_clk,\r
+ SYSCLK => rxup_half_clk, --clk_100_osc, -- rx_half_clk is selectively used inside med_ecp3_sfp_4_sync_down.vhd\r
+ RESET => downlink_reset,\r
+ CLEAR => downlink_clear,\r
+ ---------------------------------------------------------------------------------------------------------------------------------------------------------\r
+ LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.\r
+ ---------------------------------------------------------------------------------------------------------------------------------------------------------\r
+-- MED_DATA_IN(0*16+15 downto 0*16) => med_data_out(1*16+15 downto 1*16),\r
+ MED_DATA_IN(0) => med_data_out(1*16+15 downto 1*16),\r
+ MED_DATA_IN(1) => med_data_out(6*16+15 downto 6*16),\r
+ MED_DATA_IN(2) => med_data_out(4*16+15 downto 4*16),\r
+ MED_DATA_IN(3) => med_data_out(2*16+15 downto 2*16),\r
+\r
+-- MED_PACKET_NUM_IN(0*3+2 downto 0*3) => med_packet_num_out(1*3+2 downto 1*3),\r
+ MED_PACKET_NUM_IN(0) => med_packet_num_out(1*3+2 downto 1*3),\r
+ MED_PACKET_NUM_IN(1) => med_packet_num_out(6*3+2 downto 6*3),\r
+ MED_PACKET_NUM_IN(2) => med_packet_num_out(2*3+2 downto 2*3),\r
+ MED_PACKET_NUM_IN(3) => med_packet_num_out(4*3+2 downto 4*3),\r
+\r
+ MED_DATAREADY_IN(0) => med_dataready_out(1),\r
+ MED_DATAREADY_IN(1) => med_dataready_out(6),\r
+ MED_DATAREADY_IN(2) => med_dataready_out(2),\r
+ MED_DATAREADY_IN(3) => med_dataready_out(4),\r
+\r
+ MED_READ_OUT(0) => med_read_in(1),\r
+ MED_READ_OUT(1) => med_read_in(6),\r
+ MED_READ_OUT(2) => med_read_in(2),\r
+ MED_READ_OUT(3) => med_read_in(4),\r
+\r
+-- MED_DATA_OUT(0*16+15 downto 0*16) => med_data_in(1*16+15 downto 1*16),\r
+ MED_DATA_OUT(0) => med_data_in(1*16+15 downto 1*16),\r
+ MED_DATA_OUT(1) => med_data_in(6*16+15 downto 6*16),\r
+ MED_DATA_OUT(2) => med_data_in(2*16+15 downto 2*16),\r
+ MED_DATA_OUT(3) => med_data_in(4*16+15 downto 4*16),\r
+\r
+-- MED_PACKET_NUM_OUT(0*3+2 downto 0*3) => med_packet_num_in(1*3+2 downto 1*3),\r
+ MED_PACKET_NUM_OUT(0) => med_packet_num_in(1*3+2 downto 1*3),\r
+ MED_PACKET_NUM_OUT(1) => med_packet_num_in(6*3+2 downto 6*3),\r
+ MED_PACKET_NUM_OUT(2) => med_packet_num_in(2*3+2 downto 2*3),\r
+ MED_PACKET_NUM_OUT(3) => med_packet_num_in(4*3+2 downto 4*3),\r
+\r
+ MED_DATAREADY_OUT(0) => med_dataready_in(1),\r
+ MED_DATAREADY_OUT(1) => med_dataready_in(6),\r
+ MED_DATAREADY_OUT(2) => med_dataready_in(2),\r
+ MED_DATAREADY_OUT(3) => med_dataready_in(4),\r
+\r
+ MED_READ_IN(0) => med_read_out(1),\r
+ MED_READ_IN(1) => med_read_out(6),\r
+ MED_READ_IN(2) => med_read_out(2),\r
+ MED_READ_IN(3) => med_read_out(4),\r
+\r
+ RX_HALF_CLK_OUT(0) => rxdn_half_clk(0),\r
+ RX_HALF_CLK_OUT(1) => rxdn_half_clk(1),\r
+ RX_HALF_CLK_OUT(2) => rxdn_half_clk(2),\r
+ RX_HALF_CLK_OUT(3) => rxdn_half_clk(3),\r
+\r
+ RX_FULL_CLK_OUT(0) => rxdn_full_clk(0), -- needed for sync replies i.e. calibration\r
+ RX_FULL_CLK_OUT(1) => rxdn_full_clk(1), -- needed for sync replies i.e. calibration\r
+ RX_FULL_CLK_OUT(2) => rxdn_full_clk(2), -- needed for sync replies i.e. calibration\r
+ RX_FULL_CLK_OUT(3) => rxdn_full_clk(3), -- needed for sync replies i.e. calibration\r
+\r
+ TX_HALF_CLK_OUT(0) => txdn_half_clk(0),\r
+ TX_HALF_CLK_OUT(1) => txdn_half_clk(1),\r
+ TX_HALF_CLK_OUT(2) => txdn_half_clk(2),\r
+ TX_HALF_CLK_OUT(3) => txdn_half_clk(3),\r
+\r
+ TX_FULL_CLK_OUT(0) => txdn_full_clk(0),\r
+ TX_FULL_CLK_OUT(1) => txdn_full_clk(1),\r
+ TX_FULL_CLK_OUT(2) => txdn_full_clk(2),\r
+ TX_FULL_CLK_OUT(3) => txdn_full_clk(3),\r
+\r
+ RX_DLM(0) => rxdn_dlm_i(0),\r
+ RX_DLM(1) => rxdn_dlm_i(1),\r
+ RX_DLM(2) => rxdn_dlm_i(2),\r
+ RX_DLM(3) => rxdn_dlm_i(3),\r
+ \r
+ RX_DLM_WORD(0) => rxdn_dlm_word(0),\r
+ RX_DLM_WORD(1) => rxdn_dlm_word(1),\r
+ RX_DLM_WORD(2) => rxdn_dlm_word(2),\r
+ RX_DLM_WORD(3) => rxdn_dlm_word(3),\r
+ \r
+ TX_DLM(0) => txdn_dlm_i(0),\r
+ TX_DLM(1) => txdn_dlm_i(1),\r
+ TX_DLM(2) => txdn_dlm_i(2),\r
+ TX_DLM(3) => txdn_dlm_i(3),\r
+ \r
+ TX_DLM_WORD(0) => txdn_dlm_word(0),\r
+ TX_DLM_WORD(1) => txdn_dlm_word(1),\r
+ TX_DLM_WORD(2) => txdn_dlm_word(2),\r
+ TX_DLM_WORD(3) => txdn_dlm_word(3),\r
+\r
+ TX_DLM_PREVIEW_IN(0) => txdn_dlm_preview_S(0), --PL!\r
+ TX_DLM_PREVIEW_IN(1) => txdn_dlm_preview_S(1), --PL!\r
+ TX_DLM_PREVIEW_IN(2) => txdn_dlm_preview_S(2), --PL!\r
+ TX_DLM_PREVIEW_IN(3) => txdn_dlm_preview_S(3), --PL!\r
+\r
+ LINK_PHASE_OUT(0) => dnlink_phase_S(0), --PL!\r
+ LINK_PHASE_OUT(1) => dnlink_phase_S(1), --PL!\r
+ LINK_PHASE_OUT(2) => dnlink_phase_S(2), --PL!\r
+ LINK_PHASE_OUT(3) => dnlink_phase_S(3), --PL!\r
+\r
+ --SFP Connection\r
+ SD_RXD_P_IN(0) => SERDES_ADDON_RX(0), -- B0\r
+ SD_RXD_P_IN(1) => SERDES_ADDON_RX(1),\r
+ SD_RXD_P_IN(2) => SERDES_ADDON_RX(10), -- B1\r
+ SD_RXD_P_IN(3) => SERDES_ADDON_RX(11), \r
+ SD_RXD_N_IN(0) => SERDES_ADDON_RX(2), -- B2\r
+ SD_RXD_N_IN(1) => SERDES_ADDON_RX(3),\r
+ SD_RXD_N_IN(2) => SERDES_ADDON_RX(6), -- B3\r
+ SD_RXD_N_IN(3) => SERDES_ADDON_RX(7),\r
+ SD_TXD_P_OUT(0) => SERDES_ADDON_TX(0), -- B0\r
+ SD_TXD_P_OUT(1) => SERDES_ADDON_TX(1),\r
+ SD_TXD_P_OUT(2) => SERDES_ADDON_TX(10), -- B1\r
+ SD_TXD_P_OUT(3) => SERDES_ADDON_TX(11),\r
+ SD_TXD_N_OUT(0) => SERDES_ADDON_TX(2), -- B2\r
+ SD_TXD_N_OUT(1) => SERDES_ADDON_TX(3),\r
+ SD_TXD_N_OUT(2) => SERDES_ADDON_TX(6), -- B3\r
+ SD_TXD_N_OUT(3) => SERDES_ADDON_TX(7),\r
+ SD_REFCLK_P_IN => (others => '0'),\r
+ SD_REFCLK_N_IN => ('0','0','0','0'),\r
+ SD_PRSNT_N_IN(0) => SFP_MOD0(1),\r
+ SD_PRSNT_N_IN(1) => SFP_MOD0(6),\r
+ SD_PRSNT_N_IN(2) => SFP_MOD0(2),\r
+ SD_PRSNT_N_IN(3) => SFP_MOD0(4),\r
+ SD_LOS_IN(0) => SFP_LOS(1),\r
+ SD_LOS_IN(1) => SFP_LOS(6),\r
+ SD_LOS_IN(2) => SFP_LOS(2),\r
+ SD_LOS_IN(3) => SFP_LOS(4),\r
+ SD_TXDIS_OUT(0) => sfp_txdis_S(1),\r
+ SD_TXDIS_OUT(1) => sfp_txdis_S(6),\r
+ SD_TXDIS_OUT(2) => sfp_txdis_S(2),\r
+ SD_TXDIS_OUT(3) => sfp_txdis_S(4),\r
+\r
+ SCI_DATA_IN => sci2_data_in,\r
+ SCI_DATA_OUT => sci2_data_out,\r
+ SCI_ADDR => sci2_addr,\r
+ SCI_READ => sci2_read,\r
+ SCI_WRITE => sci2_write,\r
+ SCI_ACK => sci2_ack, \r
+ SCI_NACK => sci2_nack,\r
+\r
+ --Status and control port\r
+ STAT_OP(0) => med_stat_op(1*16+15 downto 1*16),\r
+ STAT_OP(1) => med_stat_op(6*16+15 downto 6*16),\r
+ STAT_OP(2) => med_stat_op(2*16+15 downto 2*16),\r
+ STAT_OP(3) => med_stat_op(4*16+15 downto 4*16),\r
+\r
+ CTRL_OP(0) => med_ctrl_op(1*16+15 downto 1*16),\r
+ CTRL_OP(1) => med_ctrl_op(6*16+15 downto 6*16),\r
+ CTRL_OP(2) => med_ctrl_op(2*16+15 downto 2*16),\r
+ CTRL_OP(3) => med_ctrl_op(4*16+15 downto 4*16),\r
+\r
+ STAT_DEBUG => open,\r
+ CTRL_DEBUG => (others => '0')\r
+ );\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- TRB-Hub\r
+---------------------------------------------------------------------------\r
+ med_stat_op(3*16+15 downto 3*16) <= x"0007"; -- !PL telling the hub that this port is inactive 08192014\r
med_stat_op(5*16+15 downto 5*16) <= x"0007"; -- !PL telling the hub that this port is inactive 08192014\r
-
- TRB_HUB : trb_net16_hub_base
- generic map (
- HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES),
- IBUF_SECURE_MODE => c_YES,
- MII_NUMBER => 7,
- MII_IS_UPLINK => (0 => 1, others => 0),
- MII_IS_DOWNLINK => (0 => 0, others => 1),
- MII_IS_UPLINK_ONLY => (0 => 1, others => 0),
- INT_NUMBER => 0,
- -- INT_CHANNELS => (0,1,3,3,3,3,3,3),
- USE_ONEWIRE => c_YES,
- COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
- HARDWARE_VERSION => x"91003200",
- INIT_ENDPOINT_ID => x"0000",
- INIT_ADDRESS => x"F357",
- USE_VAR_ENDPOINT_ID => c_YES,
- BROADCAST_SPECIAL_ADDR => x"45",
- CLOCK_FREQUENCY => CLOCK_FREQUENCY
- )
- port map (
- CLK => rxup_half_clk, --clk_100_osc,
- RESET => reset_i,
- CLK_EN => '1',
-
- --Media interfacces
- MED_DATAREADY_OUT(7*1-1 downto 0) => med_dataready_out,
- MED_DATA_OUT(7*16-1 downto 0) => med_data_out,
- MED_PACKET_NUM_OUT(7*3-1 downto 0) => med_packet_num_out,
- MED_READ_IN(7*1-1 downto 0) => med_read_in,
- MED_DATAREADY_IN(7*1-1 downto 0) => med_dataready_in,
- MED_DATA_IN(7*16-1 downto 0) => med_data_in,
- MED_PACKET_NUM_IN(7*3-1 downto 0) => med_packet_num_in,
- MED_READ_OUT(7*1-1 downto 0) => med_read_out,
- MED_STAT_OP(7*16-1 downto 0) => med_stat_op,
- MED_CTRL_OP(7*16-1 downto 0) => med_ctrl_op,
-
- COMMON_STAT_REGS => common_stat_reg,
- COMMON_CTRL_REGS => common_ctrl_reg,
- MY_ADDRESS_OUT => my_address,
- --REGIO INTERFACE
- REGIO_ADDR_OUT => regio_addr_out,
- REGIO_READ_ENABLE_OUT => regio_read_enable_out,
- REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
- REGIO_DATA_OUT => regio_data_out,
- REGIO_DATA_IN => regio_data_in,
- REGIO_DATAREADY_IN => regio_dataready_in,
- REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
- REGIO_WRITE_ACK_IN => regio_write_ack_in,
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- REGIO_TIMEOUT_OUT => regio_timeout_out,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
- ONEWIRE => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
- --Status ports (for debugging)
- MPLEX_CTRL => (others => '0'),
- CTRL_DEBUG => (others => '0'),
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
- LED_ORANGE <= SFP_LOS(1); --med_stat_op(8);
- LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10);
- LED_GREEN <= med_stat_op(12); --tx_pll_lol
- LED_RED <= med_stat_op(11); --rx_cdr_lol
--- LED_ORANGE <= '1'; --med_stat_op(8);
--- LED_YELLOW <= '0'; --med_stat_op(10);
--- LED_GREEN <= '0'; --med_stat_op(9);
--- LED_RED <= '1'; --med_stat_op(6);
-
----------------------------------------------------------------------------
--- DEBUG
----------------------------------------------------------------------------
- link_debug_in_S(31 downto 16) <= med_stat_op(15 downto 0);
- link_debug_in_S(15 downto 0) <= (3 => pll_lock, others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
--- clock_counter_proc : process(rxup_half_clk, --)
--- begin
--- if rising_edge(rxup_half_clk, --) then
--- time_counter <= time_counter + 1;
--- end if;
--- end process;
-
--- process(rxup_full_clk) --clk_soda_i)
--- begin
--- if rising_edge(rxup_full_clk) then
--- soda_counter_i <= soda_counter_i+1;
--- end if;
--- end process;
-
-
+\r
+ TRB_HUB : trb_net16_hub_base\r
+ generic map (\r
+ HUB_USED_CHANNELS => (c_YES,c_YES,c_NO,c_YES),\r
+ IBUF_SECURE_MODE => c_YES,\r
+ MII_NUMBER => 7,\r
+ MII_IS_UPLINK => (0 => 1, others => 0),\r
+ MII_IS_DOWNLINK => (0 => 0, others => 1),\r
+ MII_IS_UPLINK_ONLY => (0 => 1, others => 0),\r
+ INT_NUMBER => 0,\r
+ -- INT_CHANNELS => (0,1,3,3,3,3,3,3),\r
+ USE_ONEWIRE => c_YES,\r
+ COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),\r
+ HARDWARE_VERSION => x"91003200",\r
+ INIT_ENDPOINT_ID => x"0000",\r
+ INIT_ADDRESS => x"F357",\r
+ USE_VAR_ENDPOINT_ID => c_YES,\r
+ BROADCAST_SPECIAL_ADDR => x"45",\r
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY\r
+ )\r
+ port map (\r
+ CLK => rxup_half_clk, --clk_100_osc,\r
+ RESET => reset_i,\r
+ CLK_EN => '1',\r
+\r
+ --Media interfacces\r
+ MED_DATAREADY_OUT(7*1-1 downto 0) => med_dataready_out,\r
+ MED_DATA_OUT(7*16-1 downto 0) => med_data_out,\r
+ MED_PACKET_NUM_OUT(7*3-1 downto 0) => med_packet_num_out,\r
+ MED_READ_IN(7*1-1 downto 0) => med_read_in,\r
+ MED_DATAREADY_IN(7*1-1 downto 0) => med_dataready_in,\r
+ MED_DATA_IN(7*16-1 downto 0) => med_data_in,\r
+ MED_PACKET_NUM_IN(7*3-1 downto 0) => med_packet_num_in,\r
+ MED_READ_OUT(7*1-1 downto 0) => med_read_out,\r
+ MED_STAT_OP(7*16-1 downto 0) => med_stat_op,\r
+ MED_CTRL_OP(7*16-1 downto 0) => med_ctrl_op,\r
+\r
+ COMMON_STAT_REGS => common_stat_reg,\r
+ COMMON_CTRL_REGS => common_ctrl_reg,\r
+ MY_ADDRESS_OUT => my_address,\r
+ --REGIO INTERFACE\r
+ REGIO_ADDR_OUT => regio_addr_out,\r
+ REGIO_READ_ENABLE_OUT => regio_read_enable_out,\r
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,\r
+ REGIO_DATA_OUT => regio_data_out,\r
+ REGIO_DATA_IN => regio_data_in,\r
+ REGIO_DATAREADY_IN => regio_dataready_in,\r
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,\r
+ REGIO_WRITE_ACK_IN => regio_write_ack_in,\r
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,\r
+ REGIO_TIMEOUT_OUT => regio_timeout_out,\r
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,\r
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),\r
+ ONEWIRE => TEMPSENS,\r
+ ONEWIRE_MONITOR_OUT => open,\r
+ --Status ports (for debugging)\r
+ MPLEX_CTRL => (others => '0'),\r
+ CTRL_DEBUG => (others => '0'),\r
+ STAT_DEBUG => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- LED\r
+---------------------------------------------------------------------------\r
+ LED_ORANGE <= SFP_LOS(1); --med_stat_op(8);\r
+ LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10);\r
+ LED_GREEN <= med_stat_op(12); --tx_pll_lol\r
+ LED_RED <= med_stat_op(11); --rx_cdr_lol\r
+ \r
+ LED_RX(1) <= med_stat_op(8);\r
+ LED_RX(2) <= med_stat_op(10);\r
+ LED_RX(3) <= med_stat_op(9);\r
+ LED_RX(4) <= med_stat_op(6);\r
+\r
+---------------------------------------------------------------------------\r
+-- DEBUG\r
+--------------------------------------------------------------------------- \r
+ link_debug_in_S(31 downto 16) <= med_stat_op(15 downto 0);\r
+ link_debug_in_S(15 downto 0) <= (3 => pll_lock, others => '0');\r
+---------------------------------------------------------------------------\r
+-- Test Circuits\r
+---------------------------------------------------------------------------\r
+-- clock_counter_proc : process(rxup_half_clk, --)\r
+-- begin\r
+-- if rising_edge(rxup_half_clk, --) then\r
+-- time_counter <= time_counter + 1;\r
+-- end if;\r
+-- end process;\r
+\r
+-- process(rxup_full_clk) --clk_soda_i) \r
+-- begin\r
+-- if rising_edge(rxup_full_clk) then\r
+-- soda_counter_i <= soda_counter_i+1;\r
+-- end if;\r
+-- end process;\r
+\r
+\r
end trb3_periph_sodahub_arch;
\ No newline at end of file
-rvl_alias "rxup_full_clk" "rxup_full_clk";
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-BLOCK JTAGPATHS ;
-#################################################################
-# Basic Settings
-#################################################################
-# SYSCONFIG MCCLK_FREQ = 2.5;
-# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;
-# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;
-#################################################################
-# Clock I/O
-#################################################################
-LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;
-LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;
-LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???
-LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;
-#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";
-#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";
-#LOCATE COMP "PCSA_REFCLKN" SITE "AC18";
-#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";
-#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!
-DEFINE PORT GROUP "CLK_group" "*CLK*" ;
-IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;
-#################################################################
-# To central FPGA
-#################################################################
-LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;
-LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;
-LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;
-LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;
-LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;
-LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;
-LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;
-LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;
-LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;
-LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;
-LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;
-LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;
-DEFINE PORT GROUP "FPGA_group" "FPGA*" ;
-IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-LOCATE COMP "TEST_LINE[0]" SITE "A5" ;
-LOCATE COMP "TEST_LINE[1]" SITE "A6" ;
-LOCATE COMP "TEST_LINE[2]" SITE "G8" ;
-LOCATE COMP "TEST_LINE[3]" SITE "F9" ;
-LOCATE COMP "TEST_LINE[4]" SITE "D9" ;
-LOCATE COMP "TEST_LINE[5]" SITE "D10" ;
-LOCATE COMP "TEST_LINE[6]" SITE "F10" ;
-LOCATE COMP "TEST_LINE[7]" SITE "E10" ;
-LOCATE COMP "TEST_LINE[8]" SITE "A8" ;
-LOCATE COMP "TEST_LINE[9]" SITE "B8" ;
-LOCATE COMP "TEST_LINE[10]" SITE "G10" ;
-LOCATE COMP "TEST_LINE[11]" SITE "G9" ;
-LOCATE COMP "TEST_LINE[12]" SITE "C9" ;
-LOCATE COMP "TEST_LINE[13]" SITE "C10" ;
-LOCATE COMP "TEST_LINE[14]" SITE "H10" ;
-LOCATE COMP "TEST_LINE[15]" SITE "H11" ;
-DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
-IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;
-#################################################################
-# Connection to AddOn
-#################################################################
-LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1
-LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3
-LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5
-LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7
-#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9
-#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11
-#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13
-LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15
-LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17
-#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19
-LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21
-LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23
-LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25
-LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27
-#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29
-#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31
-#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33
-LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35
-LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2
-#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2
-LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2
-LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4
-LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6
-LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8
-#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10
-#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12
-#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3
-LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3
-LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18
-#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20
-LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22
-LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24
-LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26
-LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28
-#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30
-#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32
-#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34
-LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36
-LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38
-#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40
-LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169
-LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171
-LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173
-LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175
-#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177
-#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179
-#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181
-LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183
-LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185
-#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187
-LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170
-LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172
-LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174
-LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176
-#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178
-#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180
-#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182
-LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184
-LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186
-#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188
-DEFINE PORT GROUP "SFP_group" "SFP*" ;
-IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#################################################################
-# Additional Lines to AddOn
-#################################################################
-#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3
-#all lines are input only
-#line 4/5 go to PLL input
-#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194
-#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196
-#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198
-#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200
-#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69
-#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71
-#################################################################
-# Flash ROM and Reboot
-#################################################################
-LOCATE COMP "FLASH_CLK" SITE "B12" ;
-LOCATE COMP "FLASH_CS" SITE "E11" ;
-LOCATE COMP "FLASH_DIN" SITE "E12" ;
-LOCATE COMP "FLASH_DOUT" SITE "A12" ;
-DEFINE PORT GROUP "FLASH_group" "FLASH*" ;
-IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;
-LOCATE COMP "PROGRAMN" SITE "B11" ;
-IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#################################################################
-# Misc
-#################################################################
-LOCATE COMP "TEMPSENS" SITE "A13" ;
-IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;
-#coding of FPGA number
-LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;
-LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;
-IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;
-#terminated differential pair to pads
-LOCATE COMP "SUPPL" SITE "C14" ;
-#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;
-#################################################################
-# LED
-#################################################################
-LOCATE COMP "LED_GREEN" SITE "F12" ;
-LOCATE COMP "LED_ORANGE" SITE "G13" ;
-LOCATE COMP "LED_RED" SITE "A15" ;
-LOCATE COMP "LED_YELLOW" SITE "A16" ;
-DEFINE PORT GROUP "LED_group" "LED*" ;
-IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-#################################################################
-#GSR_NET NET "GSR_N";
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
-
-MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;
+rvl_alias "rxup_full_clk" "rxup_full_clk";\r
+BLOCK RESETPATHS ;\r
+BLOCK ASYNCPATHS ;\r
+BLOCK RD_DURING_WR_PATHS ;\r
+BLOCK JTAGPATHS ;\r
+#################################################################\r
+# Basic Settings\r
+#################################################################\r
+SYSCONFIG MCCLK_FREQ = 20;\r
+# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;\r
+# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz;\r
+# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz;\r
+#################################################################\r
+# Clock I/O\r
+#################################################################\r
+LOCATE COMP "CLK_PCLK_RIGHT" SITE "U20" ;\r
+LOCATE COMP "CLK_PCLK_LEFT" SITE "M4" ;\r
+LOCATE COMP "CLK_GPLL_RIGHT" SITE "W1" ;# NOTE: This is not a clock input; it's a FB input !! WHY???\r
+LOCATE COMP "CLK_GPLL_LEFT" SITE "U25" ;\r
+#LOCATE COMP "CLK_SERDES_INT_RIGHT" SITE "AC18";\r
+#LOCATE COMP "PCSA_REFCLKP" SITE "AC17";\r
+#LOCATE COMP "PCSA_REFCLKN" SITE "AC18";\r
+#LOCATE COMP "CLK_SERDES_INT_LEFT" SITE "AC10";\r
+#LOCATE COMP "gen_200_PLL.THE_MAIN_PLL/PLLInst_0" SITE "PLL_R79C5" ; PL!\r
+DEFINE PORT GROUP "CLK_group" "*CLK*" ;\r
+IOBUF GROUP "CLK_group" IO_TYPE=LVDS25 ;\r
+#################################################################\r
+# To central FPGA\r
+#################################################################\r
+LOCATE COMP "FPGA5_COMM[0]" SITE "AD4" ;\r
+LOCATE COMP "FPGA5_COMM[1]" SITE "AE3" ;\r
+LOCATE COMP "FPGA5_COMM[2]" SITE "AA7" ;\r
+LOCATE COMP "FPGA5_COMM[3]" SITE "AB7" ;\r
+LOCATE COMP "FPGA5_COMM[4]" SITE "AD3" ;\r
+LOCATE COMP "FPGA5_COMM[5]" SITE "AC4" ;\r
+LOCATE COMP "FPGA5_COMM[6]" SITE "AE2" ;\r
+LOCATE COMP "FPGA5_COMM[7]" SITE "AF3" ;\r
+LOCATE COMP "FPGA5_COMM[8]" SITE "AE4" ;\r
+LOCATE COMP "FPGA5_COMM[9]" SITE "AF4" ;\r
+LOCATE COMP "FPGA5_COMM[10]" SITE "V10" ;\r
+LOCATE COMP "FPGA5_COMM[11]" SITE "W10" ;\r
+DEFINE PORT GROUP "FPGA_group" "FPGA*" ;\r
+IOBUF GROUP "FPGA_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+LOCATE COMP "TEST_LINE[0]" SITE "A5" ;\r
+LOCATE COMP "TEST_LINE[1]" SITE "A6" ;\r
+LOCATE COMP "TEST_LINE[2]" SITE "G8" ;\r
+LOCATE COMP "TEST_LINE[3]" SITE "F9" ;\r
+LOCATE COMP "TEST_LINE[4]" SITE "D9" ;\r
+LOCATE COMP "TEST_LINE[5]" SITE "D10" ;\r
+LOCATE COMP "TEST_LINE[6]" SITE "F10" ;\r
+LOCATE COMP "TEST_LINE[7]" SITE "E10" ;\r
+LOCATE COMP "TEST_LINE[8]" SITE "A8" ;\r
+LOCATE COMP "TEST_LINE[9]" SITE "B8" ;\r
+LOCATE COMP "TEST_LINE[10]" SITE "G10" ;\r
+LOCATE COMP "TEST_LINE[11]" SITE "G9" ;\r
+LOCATE COMP "TEST_LINE[12]" SITE "C9" ;\r
+LOCATE COMP "TEST_LINE[13]" SITE "C10" ;\r
+LOCATE COMP "TEST_LINE[14]" SITE "H10" ;\r
+LOCATE COMP "TEST_LINE[15]" SITE "H11" ;\r
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;\r
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12 ;\r
+#################################################################\r
+# Connection to AddOn\r
+#################################################################\r
+LOCATE COMP "LED_LINKOK[1]" SITE "P1" ;#DQLL0_0 #1\r
+LOCATE COMP "LED_RX[1]" SITE "P2" ;#DQLL0_1 #3\r
+LOCATE COMP "LED_TX[1]" SITE "T2" ;#DQLL0_2 #5\r
+LOCATE COMP "SFP_MOD0[1]" SITE "U3" ;#DQLL0_3 #7\r
+#LOCATE COMP "SFP_MOD1_1" SITE "R1"; #DQLL0_4 #9\r
+#LOCATE COMP "SFP_MOD2_1" SITE "R2"; #DQLL0_5 #11\r
+#LOCATE COMP "SFP_RATESEL_1" SITE "N3"; #DQSLL0_T #13\r
+LOCATE COMP "SFP_TXDIS[1]" SITE "P3" ;#DQSLL0_C #15\r
+LOCATE COMP "SFP_LOS[1]" SITE "P5" ;#DQLL0_6 #17\r
+#LOCATE COMP "SFP_TXFAULT_1" SITE "P6"; #DQLL0_7 #19\r
+LOCATE COMP "LED_LINKOK[2]" SITE "N5" ;#DQLL0_8 #21\r
+LOCATE COMP "LED_RX[2]" SITE "N6" ;#DQLL0_9 #23\r
+LOCATE COMP "LED_TX[2]" SITE "AC2" ;#DQLL2_0 #25\r
+LOCATE COMP "SFP_MOD0[2]" SITE "AC3" ;#DQLL2_1 #27\r
+#LOCATE COMP "SFP_MOD1_2" SITE "AB1"; #DQLL2_2 #29\r
+#LOCATE COMP "SFP_MOD2_2" SITE "AC1"; #DQLL2_3 #31\r
+#LOCATE COMP "SFP_RATESEL_2" SITE "AA1"; #DQLL2_4 #33\r
+LOCATE COMP "SFP_TXDIS[2]" SITE "AA2" ;#DQLL2_5 #35\r
+LOCATE COMP "SFP_LOS[2]" SITE "W7" ;#DQLL2_T #37 #should be DQSLL2\r
+#LOCATE COMP "SFP_TXFAULT_2" SITE "W6"; #DQLL2_C #39 #should be DQSLL2\r
+LOCATE COMP "LED_LINKOK[3]" SITE "AD1" ;#DQLL3_0 #2\r
+LOCATE COMP "LED_RX[3]" SITE "AD2" ;#DQLL3_1 #4\r
+LOCATE COMP "LED_TX[3]" SITE "AB5" ;#DQLL3_2 #6\r
+LOCATE COMP "SFP_MOD0[3]" SITE "AB6" ;#DQLL3_3 #8\r
+#LOCATE COMP "SFP_MOD1_3" SITE "AB3"; #DQLL3_4 #10\r
+#LOCATE COMP "SFP_MOD2_3" SITE "AB4"; #DQLL3_5 #12\r
+#LOCATE COMP "SFP_RATESEL_3" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3\r
+LOCATE COMP "SFP_TXDIS[3]" SITE "Y7" ;#DQLL3_C #16 #should be DQSLL3\r
+LOCATE COMP "SFP_LOS[3]" SITE "AA3" ;#DQLL3_6 #18\r
+#LOCATE COMP "SFP_TXFAULT_3" SITE "AA4"; #DQLL3_7 #20\r
+LOCATE COMP "LED_LINKOK[4]" SITE "W8" ;#DQLL3_8 #22\r
+LOCATE COMP "LED_RX[4]" SITE "W9" ;#DQLL3_9 #24\r
+LOCATE COMP "LED_TX[4]" SITE "V1" ;#DQLL1_0 #26\r
+LOCATE COMP "SFP_MOD0[4]" SITE "U2" ;#DQLL1_1 #28\r
+#LOCATE COMP "SFP_MOD1_4" SITE "T1"; #DQLL1_2 #30\r
+#LOCATE COMP "SFP_MOD2_4" SITE "U1"; #DQLL1_3 #32\r
+#LOCATE COMP "SFP_RATESEL_4" SITE "P4"; #DQLL1_4 #34\r
+LOCATE COMP "SFP_TXDIS[4]" SITE "R3" ;#DQLL1_5 #36\r
+LOCATE COMP "SFP_LOS[4]" SITE "T3" ;#DQSLL1_T #38\r
+#LOCATE COMP "SFP_TXFAULT_4" SITE "R4"; #DQSLL1_C #40\r
+LOCATE COMP "LED_LINKOK[5]" SITE "W23" ;#DQLR1_0 #169\r
+LOCATE COMP "LED_RX[5]" SITE "W22" ;#DQLR1_1 #171\r
+LOCATE COMP "LED_TX[5]" SITE "AA25" ;#DQLR1_2 #173\r
+LOCATE COMP "SFP_MOD0[5]" SITE "Y24" ;#DQLR1_3 #175\r
+#LOCATE COMP "SFP_MOD1_5" SITE "AA26"; #DQLR1_4 #177\r
+#LOCATE COMP "SFP_MOD2_5" SITE "AB26"; #DQLR1_5 #179\r
+#LOCATE COMP "SFP_RATESEL_5" SITE "W21"; #DQSLR1_T #181\r
+LOCATE COMP "SFP_TXDIS[5]" SITE "W20" ;#DQSLR1_C #183\r
+LOCATE COMP "SFP_LOS[5]" SITE "AA24" ;#DQLR1_6 #185\r
+#LOCATE COMP "SFP_TXFAULT_5" SITE "AA23"; #DQLR1_7 #187\r
+LOCATE COMP "LED_LINKOK[6]" SITE "R25" ;#DQLR2_0 #170\r
+LOCATE COMP "LED_RX[6]" SITE "R26" ;#DQLR2_1 #172\r
+LOCATE COMP "LED_TX[6]" SITE "T25" ;#DQLR2_2 #174\r
+LOCATE COMP "SFP_MOD0[6]" SITE "T24" ;#DQLR2_3 #176\r
+#LOCATE COMP "SFP_MOD1_6" SITE "T26"; #DQLR2_4 #178\r
+#LOCATE COMP "SFP_MOD2_6" SITE "U26"; #DQLR2_5 #180\r
+#LOCATE COMP "SFP_RATESEL_6" SITE "V21"; #DQSLR2_T #182\r
+LOCATE COMP "SFP_TXDIS[6]" SITE "V22" ;#DQSLR2_C #184\r
+LOCATE COMP "SFP_LOS[6]" SITE "U24" ;#DQLR2_6 #186\r
+#LOCATE COMP "SFP_TXFAULT_6" SITE "V24"; #DQLR2_7 #188\r
+DEFINE PORT GROUP "SFP_group" "SFP*" ;\r
+IOBUF GROUP "SFP_group" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+#################################################################\r
+# Additional Lines to AddOn\r
+#################################################################\r
+#Lines 0/1 are terminated with 100 Ohm, pads available on 0-3\r
+#all lines are input only\r
+#line 4/5 go to PLL input\r
+#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194\r
+#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196\r
+#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198\r
+#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200\r
+#LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69\r
+#LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 \r
+#################################################################\r
+# Flash ROM and Reboot\r
+#################################################################\r
+LOCATE COMP "FLASH_CLK" SITE "B12" ;\r
+LOCATE COMP "FLASH_CS" SITE "E11" ;\r
+LOCATE COMP "FLASH_DIN" SITE "E12" ;\r
+LOCATE COMP "FLASH_DOUT" SITE "A12" ;\r
+DEFINE PORT GROUP "FLASH_group" "FLASH*" ;\r
+IOBUF GROUP "FLASH_group" IO_TYPE=LVCMOS25 PULLMODE=NONE ;\r
+LOCATE COMP "PROGRAMN" SITE "B11" ;\r
+IOBUF PORT "PROGRAMN" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
+#################################################################\r
+# Misc\r
+#################################################################\r
+LOCATE COMP "TEMPSENS" SITE "A13" ;\r
+IOBUF PORT "TEMPSENS" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8 ;\r
+#coding of FPGA number\r
+LOCATE COMP "CODE_LINE[1]" SITE "AA20" ;\r
+LOCATE COMP "CODE_LINE[0]" SITE "Y21" ;\r
+IOBUF PORT "CODE_LINE[1]" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+IOBUF PORT "CODE_LINE[0]" IO_TYPE=LVCMOS25 PULLMODE=UP ;\r
+#terminated differential pair to pads\r
+LOCATE COMP "SUPPL" SITE "C14" ;\r
+#IOBUF PORT "SUPPL" IO_TYPE=LVDS25 ;\r
+#################################################################\r
+# LED\r
+#################################################################\r
+LOCATE COMP "LED_GREEN" SITE "F12" ;\r
+LOCATE COMP "LED_ORANGE" SITE "G13" ;\r
+LOCATE COMP "LED_RED" SITE "A15" ;\r
+LOCATE COMP "LED_YELLOW" SITE "A16" ;\r
+DEFINE PORT GROUP "LED_group" "LED*" ;\r
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12 ;\r
+\r
+\r
+#################################################################\r
+#GSR_NET NET "GSR_N"; \r
+#################################################################\r
+# Locate Serdes and media interfaces\r
+#################################################################\r
+LOCATE COMP "THE_HUB_SYNC_UPLINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;\r
+LOCATE COMP "THE_HUB_SYNC_DOWNLINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;\r
+\r
+MULTICYCLE FROM CELL "THE_RESET_HANDLER/rese*" 20.000000 ns ;\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/SCI_DATA_OUT*" 20.000000 ns ;\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;\r
+MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/sci*" 20.000000 ns ;\r
#MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/wa_pos*" 20.000000 ns ; # to debug only\r
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
-MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;
-#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only
-#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;
-MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;
-MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;
-
-## IOBUF ALLPORTS ;
-USE PRIMARY NET "clk_200_osc" ;
-USE PRIMARY NET "clk_100_osc" ;
-USE PRIMARY NET "rxup_full_clk" ;
-FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
-FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-FREQUENCY NET "rxup_full_clk" 100.000000 MHz ;
+MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/SCI_DATA_OUT*" 20.000000 ns ;\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;\r
+MULTICYCLE FROM CELL "THE_HUB_SYNC_DOWNLINK/sci*" 20.000000 ns ;\r
+#MULTICYCLE TO CELL "THE_HUB_SYNC_DOWNLINK/wa_pos*" 20.000000 ns ; # to debug only\r
+#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns;\r
+MULTICYCLE FROM CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_pos*" 20.000000 ns ;\r
+MULTICYCLE TO CELL "THE_HUB_SYNC_UPLINK/PROC_SCI_CTRL.wa_position[0]" 20.000000 ns ;\r
+\r
+BLOCK PATH FROM CLKNET "clk_100_osc_c" TO CLKNET "THE_HUB_SYNC_DOWNLINK/sci_write_i" ;\r
+BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_read_*";\r
+BLOCK PATH TO CLKNET "THE_HUB_SYNC_UPLINK/sci_write_*";\r
+\r
+#UGROUP "SPIlogic" BBOX 20 20\r
+# BLKNAME THE_SPI_RELOAD;\r
+#LOCATE UGROUP "SPIlogic" SITE "R10C150D" ;\r
+\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[0]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[1]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[2]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk_c[3]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[0]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[1]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[2]";\r
+PROHIBIT PRIMARY NET "THE_HUB_SYNC_DOWNLINK/rx_full_clk[3]";\r
+\r
+## IOBUF ALLPORTS ;\r
+USE PRIMARY NET "clk_200_osc" ;\r
+USE PRIMARY NET "clk_100_osc" ;\r
+USE PRIMARY NET "rxup_full_clk" ;\r
+FREQUENCY NET "clk_200_osc" 200.000000 MHz ;\r
+FREQUENCY NET "clk_100_osc" 100.000000 MHz ;\r
+FREQUENCY NET "rxup_full_clk" 200.000000 MHz ;\r
jspc29 / soda.git / commitdiff