FPGAboard_staplfilename=jcb_trb_009.stapl
FPGAboard_staplfilename_delay1=jcb_trb_008.stapl
FPGAboard_addonortrb=trb
-FPGAtrbnetAddr=0xf013
+FPGAtrbnetAddr=0xf308
- CONFperiod_trbnetAddr=0xc001
- CONFoffspillcounter_trbnetAddr=0xc002
- CONFwaitstart_trbnetAddr=0xc007
- CONFtriginitseq_trbnetAddr=0xc003
- CONFtrigmapsstart_trbnetAddr=0xc00b
- CONFtrigmapsreset_trbnetAddr=0xc00a
- CONFtrigrunjtag_trbnetAddr=0xc00f
- CONFtrigwriteonce_trbnetAddr=0xc014
- ;gui_defaults is a comma-separated list of the following strings representing buttons in the gui:
- ;'h_prog_fpga','h_start_trbnetd','h_period_0_15s','h_period_1s','h_period_10s', 'h_no_period'
+ CONFwaitstart_trbnetAddr=0xb007
+ CONFtriginitseq_trbnetAddr=0xb003
+ CONFtrigmapsstart_trbnetAddr=0xb00b
+ CONFtrigmapsreset_trbnetAddr=0xb00a
+ CONFtrigrunjtag_trbnetAddr=0xb00f
+ CONFtrigwriteonce_trbnetAddr=0xb014
+ ;guiBM_NP_defaults is a comma-separated list of the following strings representing buttons in the gui:
+ ;'h_prog_fpga','h_start_trbnetd','h_period_0_15s', 'h_waitbeforestart_6us', 'h_waitbeforestart_1ms' ,
+ ;'h_waitbeforestart_1s', 'h_trigger_init_sequence', 'h_maps_reset', 'h_run_jtag', 'h_write_once',
+ ;'h_maps_start'
;be aware that h_prog_fpga doesn't wait until the optical link is up on the Trb
- gui_defaults=h_period_0_15s
guiBM_NP_defaults=h_waitbeforestart_6us
-FPGAtrbnetAddr=0xf013
+FPGAtrbnetAddr=0xf308
- RAMtrbnetAddr=0xb000
- CMDreg_trbnetAddr=0xb120
- RAMbase_trbnetAddr=0xb121
- DATAreg_trbnetAddr=0xb122
- STATUS2RAM3BBASEADDRREGtrbnetAddr=0xb163
- STATUS2RAM3BtrbnetAddr=0xb170
- CONFsignals_trbnetAddr=0xc006
- CONFresetafterfirstwrite_trbnetAddr=0xc011
- CONFresetbeforeinit_trbnetAddr=0xc010
- CONFtrigmapsstart_trbnetAddr=0xc00e
- CONFtrigmapsreset_trbnetAddr=0xc00d
- CONFtrigrunjtag_trbnetAddr=0xc00f
- CONFtrigwriteonce_trbnetAddr=0xc014
- CONFtriginitseq_trbnetAddr=0xc00c
+ RAMtrbnetAddr=0xa000
+ CMDreg_trbnetAddr=0xa120
+ RAMbase_trbnetAddr=0xa121
+ DATAreg_trbnetAddr=0xa122
+ STATUS2RAM3BBASEADDRREGtrbnetAddr=0xa163
+ STATUS2RAM3BtrbnetAddr=0xa170
+ CONFsignals_trbnetAddr=0xb020
+ CONFresetafterfirstwrite_trbnetAddr=0xb011
+ CONFresetbeforeinit_trbnetAddr=0xb010
+ CONFtrigmapsstart_trbnetAddr=0xb00e
+ CONFtrigmapsreset_trbnetAddr=0xb00d
+ CONFtrigrunjtag_trbnetAddr=0xb00f
+ CONFtrigwriteonce_trbnetAddr=0xb014
+ CONFtriginitseq_trbnetAddr=0xb00c
chainnr=0
- DEBUGram1baddr=0xb147
- DEBUGram1bdata=0xb148
- DEBUGram1caddr=0xb149
- DEBUGram1cdata=0xb14a
- DEBUGram1crun=0xb14b
- ;CONFperiod_trbnetAddr=0xc001
- ;CONFoffspillcounter_trbnetAddr=0xc002
- ;CONFwaitstart_trbnetAddr=0xc007
+ DEBUGram1baddr=0xa147
+ DEBUGram1bdata=0xa148
+ DEBUGram1caddr=0xa149
+ DEBUGram1cdata=0xa14a
+ DEBUGram1crun=0xa14b
+ ;CONFwaitstart_trbnetAddr=0xb007
FPGAboard_hostname=trb126
;FPGAboard_staplfilename=jcb_trb_007.stapl
FPGAboard_staplfilename=jcb_trb_009.stapl