add monitoring and SPI to KEL connectors on backplane master

diff --git a/backplanemaster/trb3sc_master.lpf b/backplanemaster/trb3sc_master.lpf
index bc891a128cb95a0582e0535c5cd281fc4acd80e6..1e62b563e4f2bd6b09702cba43743496fe962054 100644 (file)
--- a/backplanemaster/trb3sc_master.lpf
+++ b/backplanemaster/trb3sc_master.lpf
@@ -19,161 +19,3 @@ LOCATE UGROUP        "THE_MEDIA_INT_MIXED/media_interface_group" REGION "MEDIA_B
 LOCATE UGROUP        "THE_MEDIA_4_DOWN2/media_interface_group" REGION "MEDIA_C" ;
 LOCATE UGROUP        "gen_PCSD.THE_MEDIA_PCSD/media_interface_group" REGION "MEDIA_D" ;
 
-
-
-#MULTICYCLE TO CELL   "THE_MEDIA_4_DOW*/sci*" 20 ns;
-#MULTICYCLE FROM CELL "THE_MEDIA_4_DOW*/sci*" 20 ns;
-#MULTICYCLE TO CELL   "THE_MEDIA_4_DOW*/PROC_SCI_CTRL.wa*" 20 ns;
-BLOCK PATH TO   CLKNET "THE_MEDIA_4_DOW*/sci_write_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOW*/sci_write_i";
-BLOCK PATH TO   CLKNET "THE_MEDIA_4_DOW*/sci_read_i";
-BLOCK PATH FROM CLKNET "THE_MEDIA_4_DOW*/sci_read_i";
-MULTICYCLE TO CLKNET    "THE_MEDIA_4_DOW*/sci_read_i" 15 ns; 
-MULTICYCLE FROM CLKNET  "THE_MEDIA_4_DOW*/sci_read_i" 15 ns; 
-MULTICYCLE TO CLKNET    "THE_MEDIA_4_DOW*/sci_write_i" 15 ns; 
-MULTICYCLE FROM CLKNET  "THE_MEDIA_4_DOW*/sci_write_i" 15 ns; 
-
-
-#MULTICYCLE TO CELL   "THE_MEDIA_INTERFACE/sci*" 20 ns;
-#MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/sci*" 20 ns;
-#MULTICYCLE TO CELL   "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.wa*" 20 ns;
-#BLOCK PATH TO   CLKNET "THE_MEDIA_INTERFACE/sci_write_i";
-#BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_write_i";
-#BLOCK PATH TO   CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
-#BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/sci_read_i";
-#MULTICYCLE TO CLKNET    "THE_MEDIA_INTERFACE/sci_read_i" 15 ns; 
-#MULTICYCLE FROM CLKNET  "THE_MEDIA_INTERFACE/sci_read_i" 15 ns; 
-#MULTICYCLE TO CLKNET    "THE_MEDIA_INTERFACE/sci_write_i" 15 ns; 
-#MULTICYCLE FROM CLKNET  "THE_MEDIA_INTERFACE/sci_write_i" 15 ns; 
-#
-#
-#MULTICYCLE TO CELL   "gen_PCSD.THE_MEDIA_PCSD/sci*" 20 ns;
-#MULTICYCLE FROM CELL "gen_PCSD.THE_MEDIA_PCSD/sci*" 20 ns;
-#MULTICYCLE TO CELL   "gen_PCSD.THE_MEDIA_PCSD/PROC_SCI_CTRL.wa*" 20 ns;
-#BLOCK PATH TO   CLKNET "gen_PCSD.THE_MEDIA_PCSD/sci_write_i";
-#BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_PCSD/sci_write_i";
-#BLOCK PATH TO   CLKNET "gen_PCSD.THE_MEDIA_PCSD/sci_read_i";
-#BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_PCSD/sci_read_i";
-#MULTICYCLE TO CLKNET    "gen_PCSD.THE_MEDIA_PCSD/sci_read_i" 15 ns; 
-#MULTICYCLE FROM CLKNET  "gen_PCSD.THE_MEDIA_PCSD/sci_read_i" 15 ns; 
-#MULTICYCLE TO CLKNET    "gen_PCSD.THE_MEDIA_PCSD/sci_write_i" 15 ns; 
-#MULTICYCLE FROM CLKNET  "gen_PCSD.THE_MEDIA_PCSD/sci_write_i" 15 ns; 
-#
-#MULTICYCLE TO ASIC  "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns;
-#MAXDELAY   TO ASIC  "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns;
-
-# 
-# #GbE Part
-# UGROUP "tsmac"
-#    BLKNAME GBE/imp_gen.MAC
-#    BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES
-#    BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SGMII_GBE_PCS
-#    BLKNAME GBE/rx_enable_gen.FRAME_RECEIVER
-#    BLKNAME GBE/FRAME_TRANSMITTER;
-# UGROUP "controllers" 
-#   BLKNAME GBE/main_gen.MAIN_CONTROL
-#   BLKNAME GBE/rx_enable_gen.RECEIVE_CONTROLLER
-#   BLKNAME GBE/transmit_gen.TRANSMIT_CONTROLLER;
-# UGROUP "gbe_rx_tx" 
-#    BLKNAME GBE/FRAME_CONSTRUCTOR
-#    BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/MB_IP_CONFIG
-#    BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/THE_IP_CONFIGURATOR
-#    BLKNAME GBE/setup_imp_gen.SETUP;  
-# 
-# #REGION "GBE_REGION" "R20C65D" 36 42 DEVSIZE;
-# #REGION "MED0" "R81C30D" 34 40 DEVSIZE;
-# #LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ;
-# #REGION "GBE_MAIN_REGION" "R50C64C" 65 64 DEVSIZE;
-# #LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ;
-# #LOCATE UGROUP "gbe_rx_tx" REGION "GBE_MAIN_REGION" ;
-# 
-# UGROUP "sd_tx_to_pcs" 
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[0]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[1]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[2]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[3]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[4]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[5]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[6]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[7]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q;
-# UGROUP "sd_rx_to_pcs" 
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[0]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[1]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[2]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[3]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[4]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[5]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[6]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[7]
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q
-#   BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q;
-# UGROUP "pcs_tx_to_mac" 
-#   BLKNAME GBE/pcs_tx_en_q
-#   BLKNAME GBE/pcs_tx_en_qq
-#   BLKNAME GBE/pcs_tx_er_q
-#   BLKNAME GBE/pcs_tx_er_qq
-#   BLKNAME GBE/pcs_txd_q[0]
-#   BLKNAME GBE/pcs_txd_q[1]
-#   BLKNAME GBE/pcs_txd_q[2]
-#   BLKNAME GBE/pcs_txd_q[3]
-#   BLKNAME GBE/pcs_txd_q[4]
-#   BLKNAME GBE/pcs_txd_q[5]
-#   BLKNAME GBE/pcs_txd_q[6]
-#   BLKNAME GBE/pcs_txd_q[7]
-#   BLKNAME GBE/pcs_txd_qq[0]
-#   BLKNAME GBE/pcs_txd_qq[1]
-#   BLKNAME GBE/pcs_txd_qq[2]
-#   BLKNAME GBE/pcs_txd_qq[3]
-#   BLKNAME GBE/pcs_txd_qq[4]
-#   BLKNAME GBE/pcs_txd_qq[5]
-#   BLKNAME GBE/pcs_txd_qq[6]
-#   BLKNAME GBE/pcs_txd_qq[7];
-# UGROUP "pcs_rx_to_mac" 
-#   BLKNAME GBE/pcs_rx_en_q
-#   BLKNAME GBE/pcs_rx_en_qq
-#   BLKNAME GBE/pcs_rx_er_q
-#   BLKNAME GBE/pcs_rx_er_qq
-#   BLKNAME GBE/pcs_rxd_q[0]
-#   BLKNAME GBE/pcs_rxd_q[1]
-#   BLKNAME GBE/pcs_rxd_q[2]
-#   BLKNAME GBE/pcs_rxd_q[3]
-#   BLKNAME GBE/pcs_rxd_q[4]
-#   BLKNAME GBE/pcs_rxd_q[5]
-#   BLKNAME GBE/pcs_rxd_q[6]
-#   BLKNAME GBE/pcs_rxd_q[7]
-#   BLKNAME GBE/pcs_rxd_qq[0]
-#   BLKNAME GBE/pcs_rxd_qq[1]
-#   BLKNAME GBE/pcs_rxd_qq[2]
-#   BLKNAME GBE/pcs_rxd_qq[3]
-#   BLKNAME GBE/pcs_rxd_qq[4]
-#   BLKNAME GBE/pcs_rxd_qq[5]
-#   BLKNAME GBE/pcs_rxd_qq[6]
-#   BLKNAME GBE/pcs_rxd_qq[7];
-# 
-# UGROUP "GBE_SERDES_group" BBOX 10 67 
-#    BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES;
-# LOCATE UGROUP "GBE_SERDES_group" SITE "R105C17D" ;
-# 
-# MAXDELAY NET "GBE/pcs_rx_e?_q" 1.500000 nS ;
-# MAXDELAY NET "GBE/pcs_rxd_q[?]" 1.500000 nS ;
-# 
-# DEFINE PORT GROUP "RX_GRP" "GBE/pcs_rx_en_q"
-#                      "GBE/pcs_rx_er_q"
-#                      "GBE/pcs_rxd_q*";
-# INPUT_SETUP GROUP "RX_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "GBE/serdes_rx_clk_c" ;                   
-# 
-# PRIORITIZE NET "GBE/pcs_rx_en_q" 100 ;
-# PRIORITIZE NET "GBE/pcs_rx_er_q" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[1]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[2]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[3]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[4]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[5]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[6]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[7]" 100 ;
-# PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ;
-# PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ;

diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd
index bf03c216207ebe861dc3a93a0f095e07a04e0011..cab6cb4a246a46f9b4a0c0555272da0b9c13ab22 100644 (file)
--- a/backplanemaster/trb3sc_master.vhd
+++ b/backplanemaster/trb3sc_master.vhd
@@ -26,12 +26,20 @@ entity trb3sc_master is
 --     SPARE_IN             : in    std_logic_vector( 1 downto 0);  
     BACK_LVDS            : inout std_logic_vector( 1 downto 0);
     BACK_3V3             : inout std_logic_vector( 3 downto 0);
+    
+    --KEL connector
+    INP                  : in    std_logic_vector(95 downto 64);
+    DAC_OUT_SDO          : out   std_logic_vector(6 downto 5);
+    DAC_OUT_SCK          : out   std_logic_vector(6 downto 5);
+    DAC_OUT_CS           : out   std_logic_vector(6 downto 5);
+    DAC_IN_SDI           : in    std_logic_vector(6 downto 5);    
+    
 
     --Lines to slaves
-    BACK_MASTER_READY    : out std_logic_vector(8 downto 0);
-    BACK_SLAVE_READY     : in  std_logic_vector(8 downto 0);
-    BACK_TRIG1           : in  std_logic_vector(8 downto 0);
-    BACK_TRIG2           : in  std_logic_vector(8 downto 0);
+    BACK_MASTER_READY    : out   std_logic_vector(8 downto 0);
+    BACK_SLAVE_READY     : in    std_logic_vector(8 downto 0);
+    BACK_TRIG1           : in    std_logic_vector(8 downto 0);
+    BACK_TRIG2           : in    std_logic_vector(8 downto 0);
     
     --LED
     LED_GREEN            : out   std_logic;
@@ -170,7 +178,8 @@ architecture trb3sc_arch of trb3sc_master is
   signal external_reset_delayed : std_logic_vector(4 downto 0);
   
   signal trig_gen_out_i   : std_logic_vector(3 downto 0);
-  signal monitor_inputs_i : std_logic_vector(17 downto 0);
+  signal monitor_inputs_i : std_logic_vector(18+4+32-1 downto 0);
+  signal trigger_inputs_i : std_logic_vector(18+4+32-1 downto 0);
   
   signal backplane_rx_present, backplane_tx_present : std_logic_vector(8 downto 0);
   
@@ -398,6 +407,7 @@ gen_ready_signals : for i in 0 to 8 generate
    BACK_MASTER_READY(i) <= backplane_tx_present(i) or SFP_LOS(1);
    
    monitor_inputs_i(i*2+1 downto i*2) <= BACK_TRIG2(i) & BACK_TRIG1(i);
+   trigger_inputs_i(i*2+1 downto i*2) <= BACK_TRIG2(i) & BACK_TRIG1(i);
 end generate;   
 
 ---------------------------------------------------------------------------
@@ -744,9 +754,9 @@ end generate;
       ADC_MISO    => ADC_DOUT,
       ADC_CLK     => ADC_CLK,
       --Trigger & Monitor 
-      MONITOR_INPUTS(17 downto 0) =>  monitor_inputs_i,
-      MONITOR_INPUTS(21 downto 18) => trig_gen_out_i,
-      TRIG_GEN_INPUTS  => monitor_inputs_i,
+      MONITOR_INPUTS =>  monitor_inputs_i,
+--       MONITOR_INPUTS(21 downto 18) => trig_gen_out_i,
+      TRIG_GEN_INPUTS  => trigger_inputs_i,
       TRIG_GEN_OUTPUTS => trig_gen_out_i,      
       --SED
       SED_ERROR_OUT => sed_error_i,
@@ -759,7 +769,19 @@ end generate;
       BUS_MASTER_ACTIVE => bus_master_active,        
       DEBUG_OUT  => open
       );      
-      
+
+monitor_inputs_i(21 downto 18) <= trig_gen_out_i;
+monitor_inputs_i(53 downto 22) <= INP(95 downto 64);
+
+trigger_inputs_i(21 downto 18) <= (others => '0');
+trigger_inputs_i(53 downto 22) <= INP(95 downto 64);
+
+  spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5);
+  DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4);
+  DAC_OUT_CS(6 downto 5)  <= spi_cs(5 downto 4);
+  DAC_OUT_SDO(6 downto 5) <= spi_mosi(5 downto 4);
+
+
 do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe;
 
 ---------------------------------------------------------------------------