# Word count by `grep -v '^#' abstract.txt | wc -w`
-# Currently 91 (maximum allowed: 100)
+# Currently 92 (maximum allowed: 100)
The TRB3 features four FPGA-based TDCs with <20ps RMS time precision
between two channels and 256+4 channels in total. One central FPGA
at CERN (CBM), in Juelich and Mainz with an FPGA-based discriminator
board (PaDiWa), a charge-to-width FEE board with high dynamic range,
read-out of the n-XYTER ASIC and software for data unpacking and TDC
-calibration. We conclude with an outlook on future developments.
+calibration in ROOT. We conclude with an outlook on future
+developments.
# Word count by `grep -v '^#' summary.txt | wc -w`
-# Currently 500 (maximum allowed: 500)
+# Currently 496 (maximum allowed: 500)
The 4+1 FPGA board "TRB3" can serve various applications in
experimental particle physics and beyond due to its general-purpose
Usually, in each of the four peripheral FPGAs a tapped delay line TDC
is implemented with <20ps RMS time precision between two channels
providing 64 channels plus one reference channel. The TDCs are used
-for leading edge measurements, for example from time of flight
-experiments, or by using the TDC channels in pairs, one can
-additionally extract the width of the digital pulse. The central FPGA
-serves as a flexible central trigger system and manages slow control
-and read-out of the peripheral FPGAs over a single gigabit Ethernet
-connection. The project provides a comfortable, robust and modular
-software environment, ranging from low-level register access to the
-FPGA firmwares on the command line to high-level control web2.0
-technologies. This is complemented by comprehensive specifications and
-documentation.
+for leading edge measurements or by using the TDC channels in pairs,
+one can additionally extract the width of the digital pulse. The
+central FPGA serves as a flexible central trigger system and manages
+slow control and read-out of the peripheral FPGAs over a single
+gigabit Ethernet connection. The project provides a comfortable,
+robust and modular software environment, ranging from low-level
+register access to the FPGA firmwares on the command line to
+high-level control via web2.0 technologies. This is complemented by
+comprehensive specifications and documentation.
To convert the analog signals from the detector to digital pulses
suitable for the TDC, the front-end electronics board PaDiWa was
different detectors and FEEs at CERN (CBM), in Juelich and Mainz with
up to 2400 channels, of which results are shown.
-Furthermore, the TRB3 can be used as an infrastructure to read-out
+Furthermore, the TRB3 can be used as an infrastructure to read out
specialized integrated solutions using the peripheral FPGAs, for
example to provide a timing reference, transport the acquired data to
the eventbuilder and slow control configuration of the chip. This was
realized for the n-XYTER ASIC. Additionally, the platform enables
every user group to profit from common software developments, such as
-an unpacker for the TDC datastream including the necessary calibration
-of the delay lines.
+a ROOT unpacker for the TDC datastream including the necessary
+calibration of the delay lines.
Finally, we present planned extensions of the platform: The detection
of leading and trailing edge in a single TDC channel, which doubles
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