entity trb_net16_api_base is
generic (
- API_TYPE : integer range 0 to 1 := c_API_PASSIVE;
- FIFO_TO_INT_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
+ API_TYPE : integer range 0 to 1 := c_API_ACTIVE;
+ FIFO_TO_INT_DEPTH : integer range 0 to 6 := 0;--std_FIFO_DEPTH;
FIFO_TO_APL_DEPTH : integer range 1 to 6 := 1;--std_FIFO_DEPTH;
FORCE_REPLY : integer range 0 to 1 := std_FORCE_REPLY;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
- SECURE_MODE_TO_APL: integer range 0 to 1 := c_YES;
+ SECURE_MODE_TO_APL: integer range 0 to 1 := c_NO;
SECURE_MODE_TO_INT: integer range 0 to 1 := c_YES;
APL_WRITE_4_PACKETS:integer range 0 to 1 := c_NO;
BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF"
sbuf_to_apl_free, INT_SLAVE_DATA_IN, INT_SLAVE_PACKET_NUM_IN, APL_MY_ADDRESS_IN,
reg_APL_DATAREADY_OUT, slave_running, fifo_to_apl_read_before, throw_away,state_to_int )
begin
- next_INT_SLAVE_READ_OUT <= not fifo_to_apl_full;
+ reg_INT_SLAVE_READ_OUT <= not fifo_to_apl_full;
fifo_to_apl_write <= reg_INT_SLAVE_READ_OUT and INT_SLAVE_DATAREADY_IN;
fifo_to_apl_read <= '0';
next_APL_DATAREADY_OUT <= '0';
state_to_apl <= sa_INACTIVE;
state_to_int <= IDLE;
end if;
- reg_INT_SLAVE_READ_OUT <= '0';
+ --reg_INT_SLAVE_READ_OUT <= '0';
send_trm_wrong_addr <= '0';
sequence_counter <= (others => '0');
fifo_was_not_empty <= '0';
else
state_to_apl <= next_state_to_apl;
state_to_int <= next_state_to_int;
- reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT;
+ --reg_INT_SLAVE_READ_OUT <= next_INT_SLAVE_READ_OUT;
send_trm_wrong_addr <= next_send_trm_wrong_addr;
sequence_counter <= next_sequence_counter;
fifo_was_not_empty <= next_fifo_was_not_empty;
API_TYPE : integer range 0 to 1 := c_API_PASSIVE;
IBUF_DEPTH : integer range 0 to 6 := 6;--c_FIFO_BRAM;
FIFO_TO_INT_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL;
- FIFO_TO_APL_DEPTH : integer range 0 to 6 := 6;--c_FIFO_SMALL;
+ FIFO_TO_APL_DEPTH : integer range 0 to 6 := 0;--c_FIFO_SMALL;
SBUF_VERSION : integer range 0 to 1 := c_SBUF_FULL;
MUX_SECURE_MODE : integer range 0 to 1 := c_NON_SECURE_MODE;
IBUF_SECURE_MODE : integer range 0 to 1 := c_SECURE_MODE;
- API_SECURE_MODE_TO_APL : integer range 0 to 1 := c_SECURE_MODE;
+ API_SECURE_MODE_TO_APL : integer range 0 to 1 := c_NON_SECURE_MODE;
API_SECURE_MODE_TO_INT : integer range 0 to 1 := c_SECURE_MODE;
OBUF_DATA_COUNT_WIDTH : integer range 0 to 7 := std_DATA_COUNT_WIDTH;
- INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ INIT_CAN_SEND_DATA : integer range 0 to 1 := c_NO;
REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;
DAT_CHANNEL : integer range 0 to 3 := c_SLOW_CTRL_CHANNEL
);
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;
INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
);
IBUF_SECURE_MODE => IBUF_SECURE_MODE,
SBUF_VERSION => SBUF_VERSION,
USE_ACKNOWLEDGE => cfg_USE_ACKNOWLEDGE(DAT_CHANNEL),
+ USE_CHECKSUM => USE_CHECKSUM,
INIT_CAN_SEND_DATA => INIT_CAN_SEND_DATA,
REPLY_CAN_SEND_DATA => REPLY_CAN_SEND_DATA
)
HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_SMALL;
HUB_CTRL_REG_ADDR_WIDTH : integer range 1 to 7 := 4;
HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ USE_CHECKSUM : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES);
IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
IOBUF: trb_net16_iobuf
generic map (
IBUF_DEPTH => calc_depth(i,MII_IBUF_DEPTH, API_FIFO_TO_APL_DEPTH, MII_NUMBER, API_NUMBER, c_MUX_WIDTH, HUB_CTRL_DEPTH),
+ USE_CHECKSUM => USE_CHECKSUM(k),
IBUF_SECURE_MODE => IBUF_SECURE_MODE
)
port map (
DEPTH : integer range 0 to 7 := c_FIFO_BRAM;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
SECURE_MODE : integer range 0 to 1 := c_YES
--use sbuf in med_to_api direction?
end entity;
architecture trb_net16_ibuf_arch of trb_net16_ibuf is
-
+ component trb_net_CRC is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(15 downto 0);
+ CRC_OUT : out std_logic_vector(15 downto 0);
+ CRC_match : out std_logic
+ );
+ end component;
component trb_net16_fifo is
generic (
DEPTH : integer := 4;
signal next_rec_buffer_size_out, current_rec_buffer_size_out: std_logic_vector(3 downto 0);
+ signal CRC_RESET, CRC_enable : std_logic;
+ signal CRC_match : std_logic;
+
signal last_fifo_read : std_logic;
signal throw_away : std_logic;
signal fifo_read_before : std_logic;
current_fifo_packet_type <= fifo_data_out(3 downto 0) when (fifo_packet_num_out = "00")
else saved_fifo_packet_type;
+ gen_crc : if USE_CHECKSUM = 1 generate
+ CRC_gen : trb_net_CRC
+ port map(
+ CLK => CLK,
+ RESET => CRC_RESET,
+ CLK_EN => CRC_enable,
+ DATA_IN => fifo_data_out,
+ CRC_OUT => open,
+ CRC_match => CRC_match
+ );
+ process(last_fifo_read, fifo_packet_num_out, current_fifo_packet_type)
+ begin
+ CRC_enable <= last_fifo_read and or_all(fifo_packet_num_out);
+ if current_fifo_packet_type = TYPE_TRM or (current_fifo_packet_type = TYPE_EOB) then
+ CRC_enable <= '0';
+ end if;
+ if current_fifo_packet_type = TYPE_EOB and fifo_packet_num_out = "11" then
+ CRC_enable <= '1';
+ end if;
+ end process;
+ end generate;
+
+ gen_no_crc : if USE_CHECKSUM = 0 generate
+ CRC_match <= '1';
+ end generate;
+
+
------------------------
--control incoming data
------------------------
end generate;
- process(fifo_data_out, fifo_packet_num_out, sbuf_init_free,
+ process(fifo_data_out, fifo_packet_num_out, sbuf_init_free, RESET,
fifo_empty, sbuf_reply_free, last_fifo_read, current_fifo_packet_type,
- fifo_read_before, INT_INIT_READ_IN, INT_REPLY_READ_IN)
+ fifo_read_before, INT_INIT_READ_IN, INT_REPLY_READ_IN, CRC_match)
begin
tmp_INT_DATA_OUT <= fifo_data_out;
tmp_INT_PACKET_NUM_OUT <= fifo_packet_num_out;
got_eob_init_out <= '0';
got_eob_reply_out <= '0';
throw_away <= '0';
-
-
+ CRC_RESET <= RESET;
+ if USE_CHECKSUM = 1 then
+ if current_fifo_packet_type = TYPE_TRM and fifo_packet_num_out = "10" then
+ tmp_INT_DATA_OUT(3) <= fifo_data_out(3) or not CRC_match;
+ CRC_RESET <= '1';
+ end if;
+ end if;
fifo_read <= not fifo_empty and not (fifo_read_before and not
((sbuf_init_free and not current_fifo_packet_type(3))
or (sbuf_reply_free and current_fifo_packet_type(3))
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
OBUF_DATA_COUNT_WIDTH : integer range 2 to 7 := std_DATA_COUNT_WIDTH;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
INIT_CAN_SEND_DATA : integer range 0 to 1 := c_YES;
REPLY_CAN_SEND_DATA : integer range 0 to 1 := c_YES
generic (
DATA_COUNT_WIDTH : integer := 5;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION
);
port(
DEPTH : integer range 0 to 7 := c_FIFO_BRAM;
USE_VENDOR_CORES : integer range 0 to 1 := c_YES;
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION;
SECURE_MODE : integer range 0 to 1 := c_YES
--use sbuf in med_to_api direction?
DEPTH => IBUF_DEPTH,
USE_VENDOR_CORES => USE_VENDOR_CORES,
USE_ACKNOWLEDGE => USE_ACKNOWLEDGE,
+ USE_CHECKSUM => USE_CHECKSUM,
SBUF_VERSION => SBUF_VERSION,
SECURE_MODE => IBUF_SECURE_MODE
)
generic map (
DATA_COUNT_WIDTH => OBUF_DATA_COUNT_WIDTH,
USE_ACKNOWLEDGE => USE_ACKNOWLEDGE,
+ USE_CHECKSUM => USE_CHECKSUM,
SBUF_VERSION => SBUF_VERSION
)
port map (
generic map (
DATA_COUNT_WIDTH => OBUF_DATA_COUNT_WIDTH,
USE_ACKNOWLEDGE => USE_ACKNOWLEDGE,
+ USE_CHECKSUM => USE_CHECKSUM,
SBUF_VERSION => SBUF_VERSION
)
port map (
if rising_edge(CLK) then
buf_STAT_OP(15) <= '0';
reset_packet_num <= '0';
- if fifo_valid_read_a = '1' then
- if fifo_dout_a(7 downto 0) = x"7F" then
+ if fifo_wr_en_a = '1' then
+ if fifo_din_a(7 downto 0) = x"7F" then
resync_counter <= resync_counter + 1;
else
resync_counter <= "00";
entity trb_net16_obuf is
generic (
USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE;
+ USE_CHECKSUM : integer range 0 to 1 := c_YES;
DATA_COUNT_WIDTH : integer range 1 to 7 := std_DATA_COUNT_WIDTH;
-- max used buffer size is 2**DATA_COUNT_WIDTH.
SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION
);
end component;
+ component trb_net_CRC is
+ port(
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ DATA_IN : in std_logic_vector(15 downto 0);
+ CRC_OUT : out std_logic_vector(15 downto 0);
+ CRC_match : out std_logic
+ );
+ end component;
+
signal current_output_data_buffer : STD_LOGIC_VECTOR (15 downto 0);
signal current_output_num_buffer : STD_LOGIC_VECTOR (1 downto 0);
signal current_ACK_word, current_EOB_word, current_DATA_word, current_NOP_word :
signal CURRENT_DATA_COUNT : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0);
-- signal max_DATA_COUNT, next_max_DATA_COUNT : STD_LOGIC_VECTOR (15 downto 0);
signal max_DATA_COUNT_minus_one, next_max_DATA_COUNT_minus_one : STD_LOGIC_VECTOR (DATA_COUNT_WIDTH-1 downto 0);
- signal TRANSMITTED_BUFFERS, next_TRANSMITTED_BUFFERS : STD_LOGIC_VECTOR (1 downto 0);
+ signal TRANSMITTED_BUFFERS : STD_LOGIC_VECTOR (1 downto 0);
signal increase_TRANSMITTED_BUFFERS, decrease_TRANSMITTED_BUFFERS : STD_LOGIC;
signal SEND_BUFFER_SIZE_IN : STD_LOGIC_VECTOR (3 downto 0);
type sending_state_t is (idle, sending_ack, sending_eob);
signal next_sending_state, sending_state : sending_state_t;
- signal sending_state_bits : std_logic;
+-- signal sending_state_bits : std_logic;
signal reset_DATA_COUNT : std_logic;
signal increase_DATA_COUNT : std_logic;
+
+ signal CRC_RESET, CRC_enable : std_logic;
+ signal CRC : std_logic_vector(15 downto 0);
begin
-- gen_sbuf : if SECURE_MODE = 1 generate
SBUF: trb_net16_sbuf
CURRENT_DATA_COUNT <= (others => '0');
max_DATA_COUNT_minus_one <= (others => '0');
next_max_DATA_COUNT_minus_one <= (others => '0');
- next_TRANSMITTED_BUFFERS <= (others => '0');
end generate;
- GENERATE_WORDS : process(transfer_counter, SEND_BUFFER_SIZE_IN, INT_DATA_IN, CURRENT_DATA_COUNT)
+ GENERATE_WORDS : process(transfer_counter, SEND_BUFFER_SIZE_IN, INT_DATA_IN,
+ CURRENT_DATA_COUNT, CRC)
begin
current_NOP_word <= (others => '0');
current_ACK_word <= (others => '0');
current_ACK_word(3 downto 0) <= SEND_BUFFER_SIZE_IN;
current_EOB_word(DATA_COUNT_WIDTH-1 downto 0) <= CURRENT_DATA_COUNT;
end if;
+ if transfer_counter = "11" then
+ current_EOB_word <= CRC;
+ end if;
if transfer_counter = "00" then
current_NOP_word(2 downto 0) <= TYPE_ILLEGAL;
current_ACK_word(2 downto 0) <= TYPE_ACK;
end if;
end process;
+
+
+ gen_crc : if USE_CHECKSUM = 1 generate
+ CRC_gen : trb_net_CRC
+ port map(
+ CLK => CLK,
+ RESET => CRC_RESET,
+ CLK_EN => CRC_enable,
+ DATA_IN => INT_DATA_IN,
+ CRC_OUT => CRC,
+ CRC_match => open
+ );
+ end generate;
+ gen_no_crc : if USE_CHECKSUM = 0 generate
+ CRC <= (others => '0');
+ end generate;
+
+
--since we count only 64Bit packets, each counter is updated on the last packet
--the EOB and ACK flags must be available when the last packet is sent.
--full buffers (despite the sbuf) can only occur on the last packet.
COMB_NEXT_TRANSFER : process(comb_dataready, transfer_counter, current_NOP_word,
CURRENT_DATA_COUNT, reg_SEND_ACK_IN, INT_DATAREADY_IN, INT_DATA_IN,
reg_INT_READ_OUT, saved_packet_type, sending_state,
- current_DATA_word, send_ACK, send_EOB, sbuf_free,
- current_ACK_word, current_EOB_word,
+ current_DATA_word, send_ACK, send_EOB, sbuf_free, RESET,
+ current_ACK_word, current_EOB_word, INT_PACKET_NUM_IN,
TRANSMITTED_BUFFERS, send_DATA, comb_next_read)
begin
next_SEND_ACK_IN <= send_ACK;
comb_dataready <= '0';
next_sending_state <= sending_state;
+ CRC_enable <= reg_INT_READ_OUT and INT_DATAREADY_IN and or_all(INT_PACKET_NUM_IN);
+ CRC_RESET <= RESET;
+ --only data words are CRC'ed
if (reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1') then
--can only happen if idle or sending_data
if transfer_counter = "11" then
if saved_packet_type = TYPE_TRM then -- or saved_packet_type = TYPE_EOB
reset_DATA_COUNT <= '1';
+ CRC_RESET <= '1';
increase_TRANSMITTED_BUFFERS <= '1';
if TRANSMITTED_BUFFERS(0) = '1' then
next_INT_READ_OUT <= '0';
comb_dataready <= '1';
if (transfer_counter = "11") then
next_sending_state <= idle;
+ CRC_RESET <= '1';
reset_DATA_COUNT <= '1';
increase_TRANSMITTED_BUFFERS <= '1';
end if;
process(CLK)
begin
if rising_edge(CLK) then
- if RESET = '1' then
- max_DATA_COUNT_minus_one <= (others => '0');
- max_DATA_COUNT_minus_one(0) <= '1';
- else
- case REC_BUFFER_SIZE_IN is
- when "-010" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(3, DATA_COUNT_WIDTH);
- when "-011" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(7, DATA_COUNT_WIDTH);
- when "-11-" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(127, DATA_COUNT_WIDTH);
- when others => max_DATA_COUNT_minus_one <= conv_std_logic_vector(1, DATA_COUNT_WIDTH);
- end case;
- end if;
+ case REC_BUFFER_SIZE_IN is
+ when "-010" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(3, DATA_COUNT_WIDTH);
+ when "-011" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(7, DATA_COUNT_WIDTH);
+ when "-11-" => max_DATA_COUNT_minus_one <= conv_std_logic_vector(127, DATA_COUNT_WIDTH);
+ when others => max_DATA_COUNT_minus_one <= conv_std_logic_vector(1, DATA_COUNT_WIDTH);
+ end case;
end if;
end process;
generic (
REGISTER_WIDTH : integer range 32 to 32 := 32;
ADDRESS_WIDTH : integer range 8 to 16 := 16;
- NUM_STAT_REGS : integer range 0 to 6 := 3; --log2 of number of status registers
- NUM_CTRL_REGS : integer range 0 to 6 := 3; --log2 of number of ctrl registers
+ NUM_STAT_REGS : integer range 0 to 6 := 2; --log2 of number of status registers
+ NUM_CTRL_REGS : integer range 0 to 6 := 2; --log2 of number of ctrl registers
--standard values for output registers
INIT_CTRL_REGS : std_logic_vector(2**(3)*32-1 downto 0) :=
(others => '0');
end component;
type fsm_state_t is (IDLE, HEADER_RECV, REG_READ, REG_WRITE, ONE_READ, ONE_WRITE, SEND_REPLY_SHORT_TRANSFER,
- MEM_READ, MEM_WRITE, DAT_START_READ, DAT_READ, SEND_REPLY_DATA_finish, ADDRESS_ACK, ADDRESS_RECV,
- ROM_READ);
+ MEM_READ, MEM_WRITE, DAT_START_READ, DAT_READ, SEND_REPLY_DATA_finish, ADDRESS_ACK, ADDRESS_RECV);
signal current_state, next_state : fsm_state_t;
signal HDR_F1, HDR_F2, HDR_F3 : std_logic_vector(15 downto 0);
signal next_HDR_F1, next_HDR_F2, next_HDR_F3 : std_logic_vector(15 downto 0);
signal ADR_DATA_OUT : std_logic_vector(15 downto 0);
signal ADR_READ_IN : std_logic;
signal ADR_DATAREADY_OUT : std_logic;
- signal RAM_DATA_IN, RAM_DATA_OUT : std_logic_vector(15 downto 0);
signal ADR_PACKET_NUM_OUT : std_logic_vector(1 downto 0);
- signal RAM_ADDR_IN : std_logic_vector(2 downto 0);
- signal RAM_WR_IN : std_logic;
signal ADR_REJECTED : std_logic;
signal next_API_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);
signal buf_API_ERROR_PATTERN_OUT : std_logic_vector(31 downto 0);
ADR_READ_OUT, ADR_DATAREADY_OUT, ADR_DATA_OUT, ADR_PACKET_NUM_OUT,
buf_rom_read_addr, ADR_SEND_OUT, rom_read_dout, COMMON_STAT_REG_IN, buf_COMMON_CTRL_REG_OUT
)
- variable regnum : integer range 0 to 63;
- begin
+ variable regnum_STAT : integer range 0 to 2**NUM_STAT_REGS-1;
+ variable regnum_CTRL : integer range 0 to 2**NUM_CTRL_REGS-1;
+ variable regnum_cSTAT : integer range 0 to std_COMSTATREG-1;
+ variable regnum_cCTRL : integer range 0 to std_COMCTRLREG-1;
+ begin
next_state <= current_state;
next_HDR_F1 <= HDR_F1;
next_HDR_F2 <= HDR_F2;
next_DAT_WRITE_ENABLE_OUT <= '0';
rom_read_addr <= buf_rom_read_addr;
- regnum := conv_integer(address(NUM_STAT_REGS-1 downto 0));
+ regnum_STAT := conv_integer(address(NUM_STAT_REGS-1 downto 0));
+ regnum_CTRL := conv_integer(address(NUM_CTRL_REGS-1 downto 0));
+ regnum_cSTAT := conv_integer(address(std_COMneededwidth-1 downto 0));
+ regnum_cCTRL := conv_integer(address(std_COMneededwidth-1 downto 0));
+
case current_state is
when IDLE =>
next_API_DATA_OUT <= rom_read_dout;
rom_read_addr <= address(1 downto 0) & '0';
elsif address(7 downto 6) = "10" then
- next_API_DATA_OUT <= REGISTERS_IN(regnum*REGISTER_WIDTH+31 downto regnum*REGISTER_WIDTH+16);
+ next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*REGISTER_WIDTH+31 downto regnum_STAT*REGISTER_WIDTH+16);
elsif address(7 downto 6) = "11" then
- next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum*REGISTER_WIDTH+31 downto regnum*REGISTER_WIDTH+16);
+ next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*REGISTER_WIDTH+31 downto regnum_CTRL*REGISTER_WIDTH+16);
elsif address(5) = '0' then
- next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum*REGISTER_WIDTH+31 downto regnum*REGISTER_WIDTH+16);
+ next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*REGISTER_WIDTH+31 downto regnum_cSTAT*REGISTER_WIDTH+16);
else --if address(5) = '1' then
- next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum*REGISTER_WIDTH+31 downto regnum*REGISTER_WIDTH+16);
+ next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*REGISTER_WIDTH+31 downto regnum_cCTRL*REGISTER_WIDTH+16);
end if;
elsif buf_API_PACKET_NUM_OUT = "10" then
next_API_PACKET_NUM_OUT <= "11";
if address(7 downto 6) = "01" then
next_API_DATA_OUT <= rom_read_dout;
elsif address(7 downto 6) = "10" then
- next_API_DATA_OUT <= REGISTERS_IN(regnum*REGISTER_WIDTH+15 downto regnum*REGISTER_WIDTH);
+ next_API_DATA_OUT <= REGISTERS_IN(regnum_STAT*REGISTER_WIDTH+15 downto regnum_STAT*REGISTER_WIDTH);
elsif address(7 downto 6) = "11" then
- next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum*REGISTER_WIDTH+15 downto regnum*REGISTER_WIDTH);
+ next_API_DATA_OUT <= buf_REGISTERS_OUT(regnum_CTRL*REGISTER_WIDTH+15 downto regnum_CTRL*REGISTER_WIDTH);
elsif address(5) = '0' then
- next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum*REGISTER_WIDTH+15 downto regnum*REGISTER_WIDTH);
+ next_API_DATA_OUT <= COMMON_STAT_REG_IN(regnum_cSTAT*REGISTER_WIDTH+15 downto regnum_cSTAT*REGISTER_WIDTH);
else --if address(5) = '1' then
- next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum*REGISTER_WIDTH+15 downto regnum*REGISTER_WIDTH);
+ next_API_DATA_OUT <= buf_COMMON_CTRL_REG_OUT(regnum_cCTRL*REGISTER_WIDTH+15 downto regnum_cCTRL*REGISTER_WIDTH);
end if;
next_state <= SEND_REPLY_DATA_finish;
end if;
DAT_WRITE_ENABLE_OUT <= buf_DAT_WRITE_ENABLE_OUT;
DAT_ADDR_OUT <= buf_DAT_ADDR_OUT;
REGISTERS_OUT <= buf_REGISTERS_OUT;
+ COMMON_CTRL_REG_OUT <= buf_COMMON_CTRL_REG_OUT;
-STAT(2 downto 0) <= state_bits;
+ STAT(2 downto 0) <= state_bits;
STAT(4 downto 3) <= next_API_PACKET_NUM_OUT;
STAT(5) <= next_API_DATAREADY_OUT;
STAT(14 downto 6) <= next_API_DATA_OUT(8 downto 0);
entity trb_net_rom_16x8 is
generic(
- INIT0 : std_logic_vector(15 downto 0) := x"0000";
- INIT1 : std_logic_vector(15 downto 0) := x"0000";
- INIT2 : std_logic_vector(15 downto 0) := x"0000";
- INIT3 : std_logic_vector(15 downto 0) := x"0000";
- INIT4 : std_logic_vector(15 downto 0) := x"0000";
- INIT5 : std_logic_vector(15 downto 0) := x"0000";
- INIT6 : std_logic_vector(15 downto 0) := x"0000";
- INIT7 : std_logic_vector(15 downto 0) := x"0000"
+ INIT0 : std_logic_vector(15 downto 0) := x"12A0";
+ INIT1 : std_logic_vector(15 downto 0) := x"23b1";
+ INIT2 : std_logic_vector(15 downto 0) := x"34c2";
+ INIT3 : std_logic_vector(15 downto 0) := x"49d3";
+ INIT4 : std_logic_vector(15 downto 0) := x"56e5";
+ INIT5 : std_logic_vector(15 downto 0) := x"67d5";
+ INIT6 : std_logic_vector(15 downto 0) := x"7818";
+ INIT7 : std_logic_vector(15 downto 0) := x"8927"
);
port(
CLK : in std_logic;
jspc29 / trbnet.git / commitdiff