-const char trbnet_version[] = "$Revision: 2.65 $";
+const char trbnet_version[] = "$Revision: 2.66 $";
#include <stdlib.h>
#include <signal.h>
}
-static int ports_locked = 0;
+static int master_lock = 0;
-static int lockPorts()
+static int lockPorts(int masterLock)
{
struct sembuf sops = {
0, /* sem_num: We only use one track */
SEM_UNDO /* sem_flg: remove lock if process gets killed */
};
- if (ports_locked == 1) return 0;
+ if ((master_lock == 1) && (masterLock == 0)) return 0;
/* Wait for semaphore and lock it */
if (semop(semid, &sops, 1) == -1) {
/* Get FifoToggleBit-Status, needed by read32_from_FPGA ... */
fifoToggleBit = readPC() & FIFO_TOGGLE_BIT;
+
+ if (masterLock != 0) master_lock = 1;
- ports_locked = 1;
return 0;
}
-static int unlockPorts()
+static int unlockPorts(int masterLock)
{
struct sembuf sops = {
0, /* sem_num: We only use one track */
SEM_UNDO /* */
};
- if (ports_locked == 0) return 0;
+ if ((master_lock == 1) && (masterLock == 0)) return 0;
/* Release semaphore */
if (semop(semid, &sops, 1) == -1) {
/* Unblock Signals */
sigprocmask(SIG_SETMASK, &blockSetOld, NULL);
-
- ports_locked = 0;
+
+ if (masterLock != 0) master_lock = 0;
+
return 0;
}
close(memfd);
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* Set output enabled if not done yet */
if ((*GPIOB_OE_OFFSET != GPIOB_OE_PINS) ||
setbitsPC(0x30000);
clrbitsPC(0x30000);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
return 0;
}
fprintf(stderr, "Flushing FIFO of channel# %d\n", channel);
}
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
fifo_flush(channel);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
return 0;
}
trb_errno = TRB_NONE;
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* Init transfer */
if (trb_init_transfer(3) == -1) {
- unlockPorts();
+ unlockPorts(0);
return -1;
}
status = trb_fifo_read(3, FIFO_MODE_REG_READ, data, dsize);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
if ((status > 0) && (status % 2 != 0)) {
trb_errno = TRB_INVALID_PKG_NUMBER;
}
length = length | (option == 0 ? 0x8000 : 0x0000);
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* Init transfer */
if (trb_init_transfer(3) == -1) {
- unlockPorts();
+ unlockPorts(0);
return -1;
}
status = trb_fifo_read(3, FIFO_MODE_REG_READ_MEM, data, dsize);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
if (status == -1) return status;
trb_errno = TRB_NONE;
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* Init transfer */
if (trb_init_transfer(3) == -1) {
- unlockPorts();
+ unlockPorts(0);
return -1;
}
status = trb_fifo_read(3, FIFO_MODE_REG_WRITE, NULL, 0);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
return status;
}
}
config = config | (option == 0 ? 0x8000 : 0x0000);
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
while (ctr < size) {
uint16_t len = (size - ctr) >= blockSize ? blockSize : (size - ctr);
/* Init transfer */
if (trb_init_transfer(3) == -1) {
- unlockPorts();
+ unlockPorts(0);
return -1;
}
status = trb_fifo_read(3, FIFO_MODE_REG_WRITE, NULL, 0);
}
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
return status;
}
trb_errno = TRB_NONE;
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* Init transfer */
if (trb_init_transfer(3) == -1) {
- unlockPorts();
+ unlockPorts(0);
return -1;
}
status = trb_fifo_read(3, FIFO_MODE_UID, (uint32_t*)data, dsize);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
if ((status > 0) && (status % 4 != 0)) {
trb_errno = TRB_INVALID_PKG_NUMBER;
return -1;
}
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* Init transfer */
if (trb_init_transfer(3) == -1) {
- unlockPorts();
+ unlockPorts(0);
return -1;
}
status = trb_fifo_read(3, FIFO_MODE_SET_ADDRESS, NULL, 0);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
if (status == -1) return -1;
if (status != 2) {
if (data == NULL) return -1;
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* Init transfer IPU Channel */
if (trb_init_transfer(1) == -1) {
- unlockPorts();
+ unlockPorts(0);
return -1;
}
status = trb_fifo_read(1, FIFO_MODE_IPU_DATA, data, dsize);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
return status;
}
trb_errno = TRB_NONE;
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* Init transfer trigger */
if (trb_init_transfer(0) == -1) {
- unlockPorts();
+ unlockPorts(0);
return -1;
}
/* Check for replay packets (trigger) */
status = trb_fifo_read(0, FIFO_MODE_TERM_ONLY, NULL, 0);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
if (status == -1) return -1;
return -1;
}
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* Init transfer slowcontrol */
if (trb_init_transfer(3) == -1) {
- unlockPorts();
+ unlockPorts(0);
return -1;
}
/* Init transfer trigger */
if (trb_init_transfer(0) == -1) {
- unlockPorts();
+ unlockPorts(0);
return -1;
}
status = trb_fifo_read(3, FIFO_MODE_TERM_ONLY, NULL, 0);
if (status == -1) {
fifo_flush(0);
- unlockPorts();
+ unlockPorts(0);
return -1;
}
/* Check for replay packets (trigger) */
status = trb_fifo_read(0, FIFO_MODE_TERM_ONLY, NULL, 0);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
if (status == -1) return -1;
{
trb_errno = TRB_NONE;
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* DEBUG INFO */
if (trb_debug > 0) {
read32_from_FPGA(reg_address, value);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
return 0;
}
{
trb_errno = TRB_NONE;
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* DEBUG INFO */
if (trb_debug > 0) {
write32_to_FPGA(reg_address, value);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
return 0;
}
{
trb_errno = TRB_NONE;
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* DEBUG INFO */
if (trb_debug > 0) {
write32_to_FPGA(0x10, 0x8000);
sleep(6);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
return 0;
}
{
trb_errno = TRB_NONE;
- if (lockPorts() == -1) return -1;
+ if (lockPorts(0) == -1) return -1;
/* DEBUG INFO */
if (trb_debug > 0) {
setbitsPC(0x30000);
clrbitsPC(0x30000);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(0) == -1) return -1;
return 0;
}
uint32_t *data = NULL;
int i;
- if (lockPorts() == -1) return -1;
+ if (lockPorts(1) == -1) return -1;
data = (uint32_t *) malloc(sizeof(uint32_t) * NUM_ENDPOINTS * 2);
if (data == NULL) abort();
data, NUM_ENDPOINTS * 2);
if (status == -1) {
free(data);
- unlockPorts();
+ unlockPorts(1);
return -1;
}
default:
free(data);
- unlockPorts();
+ unlockPorts(1);
return -1;
}
if ((trb_register_write(trb_address, reg_address, value) == -1) &&
(trb_errno != TRB_ENDPOINT_NOT_REACHED)) {
free(data);
- unlockPorts();
+ unlockPorts(1);
return -1;
}
}
free(data);
- if (unlockPorts() == -1) return -1;
+ if (unlockPorts(1) == -1) return -1;
return 0;
}