SFP_MOD_0 : in std_logic;\r
\r
--AddOn\r
--- FE_GPIO : inout std_logic_vector(11 downto 0);\r
--- FE_CLK : out std_logic_vector( 2 downto 1);\r
--- FE_DIFF : inout std_logic_vector(63 downto 0);\r
- --INP : inout std_logic_vector(63 downto 0);\r
- --LED_ADDON : out std_logic_vector(5 downto 0);\r
+ -- FE_GPIO : inout std_logic_vector(11 downto 0);\r
+ -- FE_CLK : out std_logic_vector( 2 downto 1);\r
+ -- FE_DIFF : inout std_logic_vector(63 downto 0);\r
+ -- INP : inout std_logic_vector(63 downto 0);\r
+ -- LED_ADDON : out std_logic_vector(5 downto 0);\r
LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0);\r
LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0);\r
LED_ADDON_RJ : out std_logic_vector(1 downto 0);\r
HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only\r
);\r
\r
-\r
attribute syn_useioff : boolean;\r
attribute syn_useioff of FLASH_NCS : signal is true;\r
attribute syn_useioff of FLASH_SCLK : signal is true;\r
attribute syn_useioff of FLASH_MOSI : signal is true;\r
attribute syn_useioff of FLASH_MISO : signal is true;\r
\r
-\r
end entity;\r
\r
architecture arch of trb5sc_mimosis is\r
+\r
attribute syn_keep : boolean;\r
attribute syn_preserve : boolean;\r
\r
- signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40 : std_logic;\r
+ signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40, clk_80 : std_logic;\r
signal GSR_N : std_logic;\r
signal reset_i : std_logic;\r
signal clear_i : std_logic;\r
signal trigger_in_i : std_logic;\r
\r
-\r
attribute syn_keep of GSR_N : signal is true;\r
attribute syn_preserve of GSR_N : signal is true;\r
\r
signal readout_rx : READOUT_RX;\r
signal readout_tx : readout_tx_array_t(0 to 0);\r
\r
- signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX;\r
- signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX;\r
+ signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbtcore_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX;\r
+ signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbtcore_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX;\r
\r
signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
signal inp_i : std_logic_vector( 7 downto 0);\r
signal gbe_status : std_logic_vector(15 downto 0);\r
\r
-\r
signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0);\r
signal i2c_reg_2 : std_logic_vector(31 downto 0);\r
signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0);\r
signal i2c_go_100, i2c_go : std_logic;\r
signal i2c_reg_5_40 : std_logic_vector(31 downto 0);\r
signal counter : unsigned(23 downto 0);\r
+\r
--signal fwd_dst_mac : std_logic_vector(47 downto 0);\r
--signal fwd_dst_ip : std_logic_vector(31 downto 0);\r
--signal fwd_dst_port : std_logic_vector(15 downto 0);\r
\r
begin\r
\r
-\r
-trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);\r
-\r
+ trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);\r
\r
---------------------------------------------------------------------------\r
-- Clock & Reset Handling\r
);\r
\r
\r
+ THE_160_PLL : entity work.pll_200_160\r
+ port map(\r
+ CLKI => clk_full_osc,\r
+ CLKOP => clk_160,\r
+ CLKOS => clk_320,\r
+ CLKOS2=> clk_40,\r
+ CLKOS3=> clk_80\r
+ );\r
\r
-THE_160_PLL : entity work.pll_200_160\r
- port map(\r
- CLKI => clk_full_osc,\r
- CLKOP => clk_160,\r
- CLKOS => clk_320,\r
- CLKOS2=> clk_40\r
- );\r
-\r
-H5(3) <= clk_320;\r
-RJ(0) <= clk_40;\r
+ H5(3) <= clk_320;\r
+ RJ(0) <= clk_40;\r
\r
---------------------------------------------------------------------------\r
-- TrbNet Uplink\r
---------------------------------------------------------------------------\r
-- Bus Handler\r
---------------------------------------------------------------------------\r
-\r
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
generic map(\r
PORT_NUMBER => 5,\r
BUS_RX(2) => bustc_rx, --Clock switch\r
BUS_RX(3) => busmimosis_rx,\r
BUS_RX(4) => busi2c_rx,\r
- --BUS_RX(5) => busgbeip_rx,\r
- --BUS_RX(6) => busgbereg_rx,\r
- --BUS_RX(7) => busfwd_rx,\r
+ BUS_RX(5) => busgbtcore_rx,\r
+ -- BUS_RX(5) => busgbeip_rx,\r
+ -- BUS_RX(6) => busgbereg_rx,\r
+ -- BUS_RX(7) => busfwd_rx,\r
BUS_TX(0) => bustools_tx,\r
BUS_TX(1) => bussci_tx,\r
BUS_TX(2) => bustc_tx,\r
BUS_TX(3) => busmimosis_tx,\r
BUS_TX(4) => busi2c_tx,\r
- --BUS_TX(5) => busgbeip_tx,\r
- --BUS_TX(6) => busgbereg_tx,\r
- --BUS_TX(7) => busfwd_tx,\r
+ BUS_TX(5) => busgbtcore_tx,\r
+ -- BUS_TX(5) => busgbeip_tx,\r
+ -- BUS_TX(6) => busgbereg_tx,\r
+ -- BUS_TX(7) => busfwd_tx,\r
STAT_DEBUG => open\r
);\r
\r
DEBUG_OUT => debug_tools\r
);\r
\r
---counter <= counter + '1' when rising_edge(clk_sys);\r
---HDR_IO <= std_logic_vector(counter(15 downto 0));\r
---LED <= std_logic_vector(counter(23 downto 16));\r
+ -- counter <= counter + '1' when rising_edge(clk_sys);\r
+ -- HDR_IO <= std_logic_vector(counter(15 downto 0));\r
+ -- LED <= std_logic_vector(counter(23 downto 16));\r
\r
- --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z';\r
- --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z';\r
+ -- COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z';\r
+ -- COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z';\r
\r
FLASH_HOLD <= '1';\r
FLASH_WP <= '1';\r
---------------------------------------------------------------------------\r
-- I2C\r
---------------------------------------------------------------------------\r
-THE_I2C : entity work.i2c_slim2\r
- port map(\r
- CLOCK => clk_40,\r
- RESET => reset_i,\r
- -- I2C command / setup\r
- I2C_GO_IN => i2c_go,\r
- ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read\r
- WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word\r
- DIRECT_IN => i2c_reg_1(4), -- don't send command\r
- I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined)\r
- I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored)\r
- I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte)\r
- I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command\r
- I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command\r
- STATUS_OUT => i2c_reg_4(23 downto 16),\r
- VALID_OUT => i2c_reg_4(31),\r
- I2C_BUSY_OUT => i2c_reg_4(30),\r
- I2C_DONE_OUT => i2c_reg_4(29),\r
- -- I2C connections\r
- SDA_IN => PIN(4),\r
- SDA_OUT => mimosis_sda_drv,\r
- SCL_IN => PIN(3),\r
- SCL_OUT => mimosis_scl_drv,\r
- -- Debug\r
- BSM_OUT => i2c_reg_4(27 downto 24)\r
-);\r
+ THE_I2C : entity work.i2c_slim2\r
+ port map(\r
+ CLOCK => clk_40,\r
+ RESET => reset_i,\r
+ -- I2C command / setup\r
+ I2C_GO_IN => i2c_go,\r
+ ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read\r
+ WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word\r
+ DIRECT_IN => i2c_reg_1(4), -- don't send command\r
+ I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined)\r
+ I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored)\r
+ I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte)\r
+ I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command\r
+ I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command\r
+ STATUS_OUT => i2c_reg_4(23 downto 16),\r
+ VALID_OUT => i2c_reg_4(31),\r
+ I2C_BUSY_OUT => i2c_reg_4(30),\r
+ I2C_DONE_OUT => i2c_reg_4(29),\r
+ -- I2C connections\r
+ SDA_IN => PIN(4),\r
+ SDA_OUT => mimosis_sda_drv,\r
+ SCL_IN => PIN(3),\r
+ SCL_OUT => mimosis_scl_drv,\r
+ -- Debug\r
+ BSM_OUT => i2c_reg_4(27 downto 24)\r
+ );\r
\r
-- I2C signal open collector driver\r
-- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
-- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
\r
-PIN(4) <= MIMOSIS_SDA;\r
-PIN(3) <= MIMOSIS_SCL;\r
-MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
-MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
-\r
-H5(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC\r
-PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START\r
-PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET\r
-\r
-PROC_I2C_REGS : process begin\r
- wait until rising_edge(CLK_SYS);\r
- busi2c_tx.ack <= '0';\r
- busi2c_tx.unknown <= '0';\r
- busi2c_tx.nack <= '0';\r
- busi2c_tx.data <= (others => '0');\r
- i2c_go_100 <= '0';\r
-\r
- if busi2c_rx.write = '1' then\r
- busi2c_tx.ack <= '1';\r
- if busi2c_rx.addr(3 downto 0) = x"0" then\r
- i2c_reg_0 <= busi2c_rx.data;\r
- elsif busi2c_rx.addr(3 downto 0) = x"1" then\r
- i2c_reg_1 <= busi2c_rx.data;\r
- elsif busi2c_rx.addr(3 downto 0) = x"2" then\r
- i2c_reg_2 <= busi2c_rx.data;\r
- elsif busi2c_rx.addr(3 downto 0) = x"3" then\r
- i2c_go_100 <= busi2c_rx.data(0);\r
- elsif busi2c_rx.addr(3 downto 0) = x"5" then\r
- i2c_reg_5 <= busi2c_rx.data;\r
- else\r
- busi2c_tx.ack <= '0';\r
- busi2c_tx.unknown <= '1';\r
- end if;\r
- elsif busi2c_rx.read = '1' then\r
- busi2c_tx.ack <= '1';\r
- if busi2c_rx.addr(3 downto 0) = x"0" then\r
- busi2c_tx.data <= i2c_reg_0;\r
- elsif busi2c_rx.addr(3 downto 0) = x"1" then\r
- busi2c_tx.data <= i2c_reg_1;\r
- elsif busi2c_rx.addr(3 downto 0) = x"2" then\r
- busi2c_tx.data <= i2c_reg_2;\r
- elsif busi2c_rx.addr(3 downto 0) = x"3" then\r
- busi2c_tx.data <= (others => '0');\r
- elsif busi2c_rx.addr(3 downto 0) = x"4" then\r
- busi2c_tx.data <= i2c_reg_4;\r
- elsif busi2c_rx.addr(3 downto 0) = x"5" then\r
- busi2c_tx.data <= i2c_reg_5;\r
- else\r
- busi2c_tx.ack <= '0';\r
- busi2c_tx.unknown <= '1';\r
+ PIN(4) <= MIMOSIS_SDA;\r
+ PIN(3) <= MIMOSIS_SCL;\r
+ MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
+ MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+\r
+ H5(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC\r
+ PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START\r
+ PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET\r
\r
+ PROC_I2C_REGS : process\r
+ begin\r
+ wait until rising_edge(CLK_SYS);\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '0';\r
+ busi2c_tx.nack <= '0';\r
+ busi2c_tx.data <= (others => '0');\r
+ i2c_go_100 <= '0';\r
+\r
+ if busi2c_rx.write = '1' then\r
+ busi2c_tx.ack <= '1';\r
+ if busi2c_rx.addr(3 downto 0) = x"0" then\r
+ i2c_reg_0 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"1" then\r
+ i2c_reg_1 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"2" then\r
+ i2c_reg_2 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"3" then\r
+ i2c_go_100 <= busi2c_rx.data(0);\r
+ elsif busi2c_rx.addr(3 downto 0) = x"5" then\r
+ i2c_reg_5 <= busi2c_rx.data;\r
+ else\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '1';\r
+ end if;\r
+ elsif busi2c_rx.read = '1' then\r
+ busi2c_tx.ack <= '1';\r
+ if busi2c_rx.addr(3 downto 0) = x"0" then\r
+ busi2c_tx.data <= i2c_reg_0;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"1" then\r
+ busi2c_tx.data <= i2c_reg_1;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"2" then\r
+ busi2c_tx.data <= i2c_reg_2;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"3" then\r
+ busi2c_tx.data <= (others => '0');\r
+ elsif busi2c_rx.addr(3 downto 0) = x"4" then\r
+ busi2c_tx.data <= i2c_reg_4;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"5" then\r
+ busi2c_tx.data <= i2c_reg_5;\r
+ else\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '1';\r
+\r
+ end if;\r
end if;\r
- end if;\r
-end process;\r
+ end process;\r
\r
THE_I2C_GO_SYNC : pulse_sync\r
port map(\r
CLK_B_IN => clk_40,\r
RESET_B_IN => reset_i,\r
PULSE_B_OUT => i2c_go\r
- );\r
-\r
- THE_MIMOSIS_SIGNAL_SYNC : signal_sync\r
- generic map(\r
- WIDTH => 32,\r
- DEPTH => 2\r
- )\r
- port map(\r
- RESET => reset_i,\r
- CLK0 => clk_sys,\r
- CLK1 => clk_40,\r
- D_IN => i2c_reg_5,\r
- D_OUT => i2c_reg_5_40\r
- );\r
+ );\r
\r
+ THE_MIMOSIS_SIGNAL_SYNC : signal_sync\r
+ generic map(\r
+ WIDTH => 32,\r
+ DEPTH => 2\r
+ )\r
+ port map(\r
+ RESET => reset_i,\r
+ CLK0 => clk_sys,\r
+ CLK1 => clk_40,\r
+ D_IN => i2c_reg_5,\r
+ D_OUT => i2c_reg_5_40\r
+ );\r
\r
\r
---------------------------------------------------------------------------\r
---- GbE\r
-----------------------------------------------------------------------------\r
--GBE : entity work.gbe_wrapper\r
- --generic map(\r
- --DO_SIMULATION => 0,\r
- --INCLUDE_DEBUG => 0,\r
- --USE_INTERNAL_TRBNET_DUMMY => 0,\r
- --USE_EXTERNAL_TRBNET_DUMMY => 0,\r
- --RX_PATH_ENABLE => 1,\r
- --FIXED_SIZE_MODE => 1,\r
- --INCREMENTAL_MODE => 1,\r
- --FIXED_SIZE => 100,\r
- --FIXED_DELAY_MODE => 1,\r
- --UP_DOWN_MODE => 0,\r
- --UP_DOWN_LIMIT => 100,\r
- --FIXED_DELAY => 100,\r
-\r
- --NUMBER_OF_GBE_LINKS => 1,\r
- --LINKS_ACTIVE => "0001",\r
-\r
- --LINK_HAS_READOUT => "0000",\r
- --LINK_HAS_SLOWCTRL => "0000",\r
- --LINK_HAS_DHCP => "0001",\r
- --LINK_HAS_ARP => "0001",\r
- --LINK_HAS_PING => "0001",\r
- --LINK_HAS_FWD => "0001"\r
- --)\r
- --port map(\r
- --CLK_SYS_IN => clk_sys,\r
- --CLK_125_IN => CLK_125,\r
- --RESET => reset_i,\r
- --GSR_N => GSR_N,\r
- ---- Trigger\r
- --TRIGGER_IN => '0',\r
- ---- SFP\r
- --SD_PRSNT_N_IN(0) => SFP_MOD_0,\r
- --SD_LOS_IN(0) => SFP_LOS,\r
- --SD_TXDIS_OUT(0) => SFP_TX_DIS,\r
- ---- trigger channel\r
- ---- only for LINK_HAS_READOUT\r
- --CTS_NUMBER_IN => (others => '0'),\r
- --CTS_CODE_IN => (others => '0'),\r
- --CTS_INFORMATION_IN => (others => '0'),\r
- --CTS_READOUT_TYPE_IN => (others => '0'),\r
- --CTS_START_READOUT_IN => '0',\r
- --CTS_DATA_OUT => open,\r
- --CTS_DATAREADY_OUT => open,\r
- --CTS_READOUT_FINISHED_OUT => open,\r
- --CTS_READ_IN => '1',\r
- --CTS_LENGTH_OUT => open,\r
- --CTS_ERROR_PATTERN_OUT => open,\r
- ---- data channel\r
- ---- only for LINK_HAS_READOUT\r
- --FEE_DATA_IN => (others => '0'),\r
- --FEE_DATAREADY_IN => '0',\r
- --FEE_READ_OUT => open,\r
- --FEE_STATUS_BITS_IN => (others => '0'),\r
- --FEE_BUSY_IN => '0',\r
- ---- unique adresses\r
- --MC_UNIQUE_ID_IN => timer.uid,\r
- --MY_TRBNET_ADDRESS_IN => timer.network_address,\r
- --ISSUE_REBOOT_OUT => open, --BUG: needs to be connected\r
- ---- slow control by GbE\r
- --GSC_CLK_IN => open,\r
- --GSC_INIT_DATAREADY_OUT => open,\r
- --GSC_INIT_DATA_OUT => open,\r
- --GSC_INIT_PACKET_NUM_OUT => open,\r
- --GSC_INIT_READ_IN => '1',\r
- --GSC_REPLY_DATAREADY_IN => '0',\r
- --GSC_REPLY_DATA_IN => (others => '0'),\r
- --GSC_REPLY_PACKET_NUM_IN => (others => '0'),\r
- --GSC_REPLY_READ_OUT => open,\r
- --GSC_BUSY_IN => '0',\r
- ---- readout\r
- --BUS_IP_RX => busgbeip_rx, -- registers inside GbE\r
- --BUS_IP_TX => busgbeip_tx, -- registers inside GbE\r
- --BUS_REG_RX => busgbereg_rx, -- registers inside GbE\r
- --BUS_REG_TX => busgbereg_tx, -- registers inside GbE\r
- ---- Forwarder\r
- --FWD_DST_MAC_IN(47 downto 0) => fwd_dst_mac,\r
- --FWD_DST_IP_IN(31 downto 0) => fwd_dst_ip,\r
- --FWD_DST_UDP_IN(15 downto 0) => fwd_dst_port,\r
- --FWD_DATA_IN(7 downto 0) => fwd_data,\r
- --FWD_DATA_VALID_IN(0) => fwd_datavalid,\r
- --FWD_SOP_IN(0) => fwd_sop,\r
- --FWD_EOP_IN(0) => fwd_eop,\r
- --FWD_READY_OUT(0) => fwd_ready,\r
- --FWD_FULL_OUT(0) => fwd_full,\r
- ---- reset\r
- --MAKE_RESET_OUT => open, -- reset by GbE --BUG: needs to be connected\r
- ---- debug and status\r
- --STATUS_OUT => open,\r
- --DEBUG_OUT => open\r
- --);\r
+ --generic map(\r
+ --DO_SIMULATION => 0,\r
+ --INCLUDE_DEBUG => 0,\r
+ --USE_INTERNAL_TRBNET_DUMMY => 0,\r
+ --USE_EXTERNAL_TRBNET_DUMMY => 0,\r
+ --RX_PATH_ENABLE => 1,\r
+ --FIXED_SIZE_MODE => 1,\r
+ --INCREMENTAL_MODE => 1,\r
+ --FIXED_SIZE => 100,\r
+ --FIXED_DELAY_MODE => 1,\r
+ --UP_DOWN_MODE => 0,\r
+ --UP_DOWN_LIMIT => 100,\r
+ --FIXED_DELAY => 100,\r
+\r
+ --NUMBER_OF_GBE_LINKS => 1,\r
+ --LINKS_ACTIVE => "0001",\r
+\r
+ --LINK_HAS_READOUT => "0000",\r
+ --LINK_HAS_SLOWCTRL => "0000",\r
+ --LINK_HAS_DHCP => "0001",\r
+ --LINK_HAS_ARP => "0001",\r
+ --LINK_HAS_PING => "0001",\r
+ --LINK_HAS_FWD => "0001"\r
+ --)\r
+ --port map(\r
+ --CLK_SYS_IN => clk_sys,\r
+ --CLK_125_IN => CLK_125,\r
+ --RESET => reset_i,\r
+ --GSR_N => GSR_N,\r
+ ---- Trigger\r
+ --TRIGGER_IN => '0',\r
+ ---- SFP\r
+ --SD_PRSNT_N_IN(0) => SFP_MOD_0,\r
+ --SD_LOS_IN(0) => SFP_LOS,\r
+ --SD_TXDIS_OUT(0) => SFP_TX_DIS,\r
+ ---- trigger channel\r
+ ---- only for LINK_HAS_READOUT\r
+ --CTS_NUMBER_IN => (others => '0'),\r
+ --CTS_CODE_IN => (others => '0'),\r
+ --CTS_INFORMATION_IN => (others => '0'),\r
+ --CTS_READOUT_TYPE_IN => (others => '0'),\r
+ --CTS_START_READOUT_IN => '0',\r
+ --CTS_DATA_OUT => open,\r
+ --CTS_DATAREADY_OUT => open,\r
+ --CTS_READOUT_FINISHED_OUT => open,\r
+ --CTS_READ_IN => '1',\r
+ --CTS_LENGTH_OUT => open,\r
+ --CTS_ERROR_PATTERN_OUT => open,\r
+ ---- data channel\r
+ ---- only for LINK_HAS_READOUT\r
+ --FEE_DATA_IN => (others => '0'),\r
+ --FEE_DATAREADY_IN => '0',\r
+ --FEE_READ_OUT => open,\r
+ --FEE_STATUS_BITS_IN => (others => '0'),\r
+ --FEE_BUSY_IN => '0',\r
+ ---- unique adresses\r
+ --MC_UNIQUE_ID_IN => timer.uid,\r
+ --MY_TRBNET_ADDRESS_IN => timer.network_address,\r
+ --ISSUE_REBOOT_OUT => open, --BUG: needs to be connected\r
+ ---- slow control by GbE\r
+ --GSC_CLK_IN => open,\r
+ --GSC_INIT_DATAREADY_OUT => open,\r
+ --GSC_INIT_DATA_OUT => open,\r
+ --GSC_INIT_PACKET_NUM_OUT => open,\r
+ --GSC_INIT_READ_IN => '1',\r
+ --GSC_REPLY_DATAREADY_IN => '0',\r
+ --GSC_REPLY_DATA_IN => (others => '0'),\r
+ --GSC_REPLY_PACKET_NUM_IN => (others => '0'),\r
+ --GSC_REPLY_READ_OUT => open,\r
+ --GSC_BUSY_IN => '0',\r
+ ---- readout\r
+ --BUS_IP_RX => busgbeip_rx, -- registers inside GbE\r
+ --BUS_IP_TX => busgbeip_tx, -- registers inside GbE\r
+ --BUS_REG_RX => busgbereg_rx, -- registers inside GbE\r
+ --BUS_REG_TX => busgbereg_tx, -- registers inside GbE\r
+ ---- Forwarder\r
+ --FWD_DST_MAC_IN(47 downto 0) => fwd_dst_mac,\r
+ --FWD_DST_IP_IN(31 downto 0) => fwd_dst_ip,\r
+ --FWD_DST_UDP_IN(15 downto 0) => fwd_dst_port,\r
+ --FWD_DATA_IN(7 downto 0) => fwd_data,\r
+ --FWD_DATA_VALID_IN(0) => fwd_datavalid,\r
+ --FWD_SOP_IN(0) => fwd_sop,\r
+ --FWD_EOP_IN(0) => fwd_eop,\r
+ --FWD_READY_OUT(0) => fwd_ready,\r
+ --FWD_FULL_OUT(0) => fwd_full,\r
+ ---- reset\r
+ --MAKE_RESET_OUT => open, -- reset by GbE --BUG: needs to be connected\r
+ ---- debug and status\r
+ --STATUS_OUT => open,\r
+ --DEBUG_OUT => open\r
+ --);\r
\r
\r
\r
--busfwd_tx.unknown <= '0';\r
\r
--if busfwd_rx.write = '1' then\r
- --busfwd_tx.ack <= '1';\r
- --case busfwd_rx.addr(7 downto 0) is\r
- --when x"00" => fwd_dst_ip <= busfwd_rx.data;\r
- --when x"01" => fwd_dst_port <= busfwd_rx.data(15 downto 0);\r
- --when x"02" => fwd_dst_mac(31 downto 0) <= busfwd_rx.data;\r
- --when x"03" => fwd_dst_mac(47 downto 32) <= busfwd_rx.data(15 downto 0);\r
- --when x"04" => fwd_length <= busfwd_rx.data(15 downto 0);\r
- --when x"05" => fwd_do_send <= busfwd_rx.data(0);\r
- --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1';\r
- --end case;\r
+ --busfwd_tx.ack <= '1';\r
+ --case busfwd_rx.addr(7 downto 0) is\r
+ --when x"00" => fwd_dst_ip <= busfwd_rx.data;\r
+ --when x"01" => fwd_dst_port <= busfwd_rx.data(15 downto 0);\r
+ --when x"02" => fwd_dst_mac(31 downto 0) <= busfwd_rx.data;\r
+ --when x"03" => fwd_dst_mac(47 downto 32) <= busfwd_rx.data(15 downto 0);\r
+ --when x"04" => fwd_length <= busfwd_rx.data(15 downto 0);\r
+ --when x"05" => fwd_do_send <= busfwd_rx.data(0);\r
+ --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1';\r
+ --end case;\r
--elsif busfwd_rx.read = '1' then\r
- --busfwd_tx.ack <= '1';\r
- --case busfwd_rx.addr(7 downto 0) is\r
- --when x"00" => busfwd_tx.data <= fwd_dst_ip;\r
- --when x"01" => busfwd_tx.data <= x"0000" & fwd_dst_port;\r
- --when x"02" => busfwd_tx.data <= fwd_dst_mac(31 downto 0);\r
- --when x"03" => busfwd_tx.data <= x"0000" & fwd_dst_mac(47 downto 32);\r
- --when x"04" => busfwd_tx.data <= x"0000" & fwd_length;\r
- --when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send;\r
- --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1';\r
- --end case;\r
+ --busfwd_tx.ack <= '1';\r
+ --case busfwd_rx.addr(7 downto 0) is\r
+ --when x"00" => busfwd_tx.data <= fwd_dst_ip;\r
+ --when x"01" => busfwd_tx.data <= x"0000" & fwd_dst_port;\r
+ --when x"02" => busfwd_tx.data <= fwd_dst_mac(31 downto 0);\r
+ --when x"03" => busfwd_tx.data <= x"0000" & fwd_dst_mac(47 downto 32);\r
+ --when x"04" => busfwd_tx.data <= x"0000" & fwd_length;\r
+ --when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send;\r
+ --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1';\r
+ --end case;\r
--end if;\r
--if reset_i = '1' then\r
- --fwd_do_send <= '0';\r
+ --fwd_do_send <= '0';\r
--end if;\r
--end process;\r
\r
-- readout_tx(0).data_write <= '0';\r
-- readout_tx(0).busy_release <= '1';\r
\r
-SFP_ADDON_TX_DIS <= (others => '0');\r
+ SFP_ADDON_TX_DIS <= (others => '0');\r
end architecture;\r
-\r
-\r
-\r
SFP_MOD_0 : in std_logic;\r
\r
--AddOn\r
- --FE_GPIO : inout std_logic_vector(11 downto 0);\r
- --FE_CLK : out std_logic_vector( 2 downto 1);\r
- --FE_DIFF : inout std_logic_vector(63 downto 0);\r
- --INP : inout std_logic_vector(63 downto 0);\r
- --LED_ADDON : out std_logic_vector(5 downto 0);\r
+ -- FE_GPIO : inout std_logic_vector(11 downto 0);\r
+ -- FE_CLK : out std_logic_vector( 2 downto 1);\r
+ -- FE_DIFF : inout std_logic_vector(63 downto 0);\r
+ -- INP : inout std_logic_vector(63 downto 0);\r
+ -- LED_ADDON : out std_logic_vector(5 downto 0);\r
LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0);\r
LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0);\r
LED_ADDON_RJ : out std_logic_vector(1 downto 0);\r
I2C_SCL : inout std_logic;\r
TMP_ALERT : in std_logic;\r
\r
- --GBTSCA\r
- SCA_RX : in std_logic_vector(1 downto 0);\r
- SCA_TX : out std_logic_vector(1 downto 0);\r
- SCA_CLK : out std_logic_vector(1 downto 0);\r
-\r
--LED\r
LED : out std_logic_vector(8 downto 1);\r
LED_SFP_YELLOW : out std_logic;\r
\r
end entity;\r
\r
-\r
architecture arch of trb5sc_mimosis is\r
\r
attribute syn_keep : boolean;\r
\r
begin\r
\r
-\r
trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);\r
\r
-\r
---------------------------------------------------------------------------\r
-- Clock & Reset Handling\r
---------------------------------------------------------------------------\r
DEBUG_OUT => debug_clock_reset\r
);\r
\r
+\r
THE_160_PLL : entity work.pll_200_160\r
port map(\r
CLKI => clk_full_osc,\r
H5(3) <= clk_320;\r
RJ(0) <= clk_40;\r
\r
-\r
---------------------------------------------------------------------------\r
-- TrbNet Uplink\r
---------------------------------------------------------------------------\r
---------------------------------------------------------------------------\r
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
generic map(\r
- PORT_NUMBER => 5,\r
+ PORT_NUMBER => 6,\r
PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"),\r
PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 8, 6 => 8, 7 => 8, others => 0),\r
PORT_MASK_ENABLE => 1\r
BUS_RX(1) => bussci_rx, --SCI Serdes\r
BUS_RX(2) => bustc_rx, --Clock switch\r
BUS_RX(3) => busmimosis_rx,\r
- BUS_RX(4) => busgbtcore_rx,\r
- -- BUS_RX(4) => busi2c_rx,\r
+ BUS_RX(4) => busi2c_rx,\r
+ BUS_RX(5) => busgbtcore_rx,\r
-- BUS_RX(5) => busgbeip_rx,\r
-- BUS_RX(6) => busgbereg_rx,\r
-- BUS_RX(7) => busfwd_rx,\r
BUS_TX(1) => bussci_tx,\r
BUS_TX(2) => bustc_tx,\r
BUS_TX(3) => busmimosis_tx,\r
- BUS_TX(4) => busgbtcore_tx,\r
- -- BUS_TX(4) => busi2c_tx,\r
+ BUS_TX(4) => busi2c_tx,\r
+ BUS_TX(5) => busgbtcore_tx,\r
-- BUS_TX(5) => busgbeip_tx,\r
-- BUS_TX(6) => busgbereg_tx,\r
-- BUS_TX(7) => busfwd_tx,\r
DEBUG_OUT => debug_tools\r
);\r
\r
---counter <= counter + '1' when rising_edge(clk_sys);\r
---HDR_IO <= std_logic_vector(counter(15 downto 0));\r
---LED <= std_logic_vector(counter(23 downto 16));\r
+ -- counter <= counter + '1' when rising_edge(clk_sys);\r
+ -- HDR_IO <= std_logic_vector(counter(15 downto 0));\r
+ -- LED <= std_logic_vector(counter(23 downto 16));\r
\r
- --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z';\r
- --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z';\r
+ -- COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z';\r
+ -- COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z';\r
\r
FLASH_HOLD <= '1';\r
FLASH_WP <= '1';\r
\r
+---------------------------------------------------------------------------\r
+-- I2C\r
+---------------------------------------------------------------------------\r
+ THE_I2C : entity work.i2c_slim2\r
+ port map(\r
+ CLOCK => clk_40,\r
+ RESET => reset_i,\r
+ -- I2C command / setup\r
+ I2C_GO_IN => i2c_go,\r
+ ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read\r
+ WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word\r
+ DIRECT_IN => i2c_reg_1(4), -- don't send command\r
+ I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined)\r
+ I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored)\r
+ I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte)\r
+ I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command\r
+ I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command\r
+ STATUS_OUT => i2c_reg_4(23 downto 16),\r
+ VALID_OUT => i2c_reg_4(31),\r
+ I2C_BUSY_OUT => i2c_reg_4(30),\r
+ I2C_DONE_OUT => i2c_reg_4(29),\r
+ -- I2C connections\r
+ SDA_IN => PIN(4),\r
+ SDA_OUT => mimosis_sda_drv,\r
+ SCL_IN => PIN(3),\r
+ SCL_OUT => mimosis_scl_drv,\r
+ -- Debug\r
+ BSM_OUT => i2c_reg_4(27 downto 24)\r
+ );\r
+\r
+-- I2C signal open collector driver\r
+-- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
+-- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+\r
+ PIN(4) <= MIMOSIS_SDA;\r
+ PIN(3) <= MIMOSIS_SCL;\r
+ MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
+ MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+\r
+ H5(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC\r
+ PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START\r
+ PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET\r
+\r
+ PROC_I2C_REGS : process\r
+ begin\r
+ wait until rising_edge(CLK_SYS);\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '0';\r
+ busi2c_tx.nack <= '0';\r
+ busi2c_tx.data <= (others => '0');\r
+ i2c_go_100 <= '0';\r
+\r
+ if busi2c_rx.write = '1' then\r
+ busi2c_tx.ack <= '1';\r
+ if busi2c_rx.addr(3 downto 0) = x"0" then\r
+ i2c_reg_0 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"1" then\r
+ i2c_reg_1 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"2" then\r
+ i2c_reg_2 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"3" then\r
+ i2c_go_100 <= busi2c_rx.data(0);\r
+ elsif busi2c_rx.addr(3 downto 0) = x"5" then\r
+ i2c_reg_5 <= busi2c_rx.data;\r
+ else\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '1';\r
+ end if;\r
+ elsif busi2c_rx.read = '1' then\r
+ busi2c_tx.ack <= '1';\r
+ if busi2c_rx.addr(3 downto 0) = x"0" then\r
+ busi2c_tx.data <= i2c_reg_0;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"1" then\r
+ busi2c_tx.data <= i2c_reg_1;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"2" then\r
+ busi2c_tx.data <= i2c_reg_2;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"3" then\r
+ busi2c_tx.data <= (others => '0');\r
+ elsif busi2c_rx.addr(3 downto 0) = x"4" then\r
+ busi2c_tx.data <= i2c_reg_4;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"5" then\r
+ busi2c_tx.data <= i2c_reg_5;\r
+ else\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '1';\r
+\r
+ end if;\r
+ end if;\r
+ end process;\r
+\r
+ THE_I2C_GO_SYNC : pulse_sync\r
+ port map(\r
+ CLK_A_IN => clk_sys,\r
+ RESET_A_IN => reset_i,\r
+ PULSE_A_IN => i2c_go_100,\r
+ CLK_B_IN => clk_40,\r
+ RESET_B_IN => reset_i,\r
+ PULSE_B_OUT => i2c_go\r
+ );\r
+\r
+ THE_MIMOSIS_SIGNAL_SYNC : signal_sync\r
+ generic map(\r
+ WIDTH => 32,\r
+ DEPTH => 2\r
+ )\r
+ port map(\r
+ RESET => reset_i,\r
+ CLK0 => clk_sys,\r
+ CLK1 => clk_40,\r
+ D_IN => i2c_reg_5,\r
+ D_OUT => i2c_reg_5_40\r
+ );\r
+\r
\r
---------------------------------------------------------------------------\r
-- LED\r
LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4));\r
LED_ADDON_SFP_ORANGE(1) <= '0';\r
\r
+-----------------------------------------------------------------------------\r
+---- GbE\r
+-----------------------------------------------------------------------------\r
+ --GBE : entity work.gbe_wrapper\r
+ --generic map(\r
+ --DO_SIMULATION => 0,\r
+ --INCLUDE_DEBUG => 0,\r
+ --USE_INTERNAL_TRBNET_DUMMY => 0,\r
+ --USE_EXTERNAL_TRBNET_DUMMY => 0,\r
+ --RX_PATH_ENABLE => 1,\r
+ --FIXED_SIZE_MODE => 1,\r
+ --INCREMENTAL_MODE => 1,\r
+ --FIXED_SIZE => 100,\r
+ --FIXED_DELAY_MODE => 1,\r
+ --UP_DOWN_MODE => 0,\r
+ --UP_DOWN_LIMIT => 100,\r
+ --FIXED_DELAY => 100,\r
+\r
+ --NUMBER_OF_GBE_LINKS => 1,\r
+ --LINKS_ACTIVE => "0001",\r
+\r
+ --LINK_HAS_READOUT => "0000",\r
+ --LINK_HAS_SLOWCTRL => "0000",\r
+ --LINK_HAS_DHCP => "0001",\r
+ --LINK_HAS_ARP => "0001",\r
+ --LINK_HAS_PING => "0001",\r
+ --LINK_HAS_FWD => "0001"\r
+ --)\r
+ --port map(\r
+ --CLK_SYS_IN => clk_sys,\r
+ --CLK_125_IN => CLK_125,\r
+ --RESET => reset_i,\r
+ --GSR_N => GSR_N,\r
+ ---- Trigger\r
+ --TRIGGER_IN => '0',\r
+ ---- SFP\r
+ --SD_PRSNT_N_IN(0) => SFP_MOD_0,\r
+ --SD_LOS_IN(0) => SFP_LOS,\r
+ --SD_TXDIS_OUT(0) => SFP_TX_DIS,\r
+ ---- trigger channel\r
+ ---- only for LINK_HAS_READOUT\r
+ --CTS_NUMBER_IN => (others => '0'),\r
+ --CTS_CODE_IN => (others => '0'),\r
+ --CTS_INFORMATION_IN => (others => '0'),\r
+ --CTS_READOUT_TYPE_IN => (others => '0'),\r
+ --CTS_START_READOUT_IN => '0',\r
+ --CTS_DATA_OUT => open,\r
+ --CTS_DATAREADY_OUT => open,\r
+ --CTS_READOUT_FINISHED_OUT => open,\r
+ --CTS_READ_IN => '1',\r
+ --CTS_LENGTH_OUT => open,\r
+ --CTS_ERROR_PATTERN_OUT => open,\r
+ ---- data channel\r
+ ---- only for LINK_HAS_READOUT\r
+ --FEE_DATA_IN => (others => '0'),\r
+ --FEE_DATAREADY_IN => '0',\r
+ --FEE_READ_OUT => open,\r
+ --FEE_STATUS_BITS_IN => (others => '0'),\r
+ --FEE_BUSY_IN => '0',\r
+ ---- unique adresses\r
+ --MC_UNIQUE_ID_IN => timer.uid,\r
+ --MY_TRBNET_ADDRESS_IN => timer.network_address,\r
+ --ISSUE_REBOOT_OUT => open, --BUG: needs to be connected\r
+ ---- slow control by GbE\r
+ --GSC_CLK_IN => open,\r
+ --GSC_INIT_DATAREADY_OUT => open,\r
+ --GSC_INIT_DATA_OUT => open,\r
+ --GSC_INIT_PACKET_NUM_OUT => open,\r
+ --GSC_INIT_READ_IN => '1',\r
+ --GSC_REPLY_DATAREADY_IN => '0',\r
+ --GSC_REPLY_DATA_IN => (others => '0'),\r
+ --GSC_REPLY_PACKET_NUM_IN => (others => '0'),\r
+ --GSC_REPLY_READ_OUT => open,\r
+ --GSC_BUSY_IN => '0',\r
+ ---- readout\r
+ --BUS_IP_RX => busgbeip_rx, -- registers inside GbE\r
+ --BUS_IP_TX => busgbeip_tx, -- registers inside GbE\r
+ --BUS_REG_RX => busgbereg_rx, -- registers inside GbE\r
+ --BUS_REG_TX => busgbereg_tx, -- registers inside GbE\r
+ ---- Forwarder\r
+ --FWD_DST_MAC_IN(47 downto 0) => fwd_dst_mac,\r
+ --FWD_DST_IP_IN(31 downto 0) => fwd_dst_ip,\r
+ --FWD_DST_UDP_IN(15 downto 0) => fwd_dst_port,\r
+ --FWD_DATA_IN(7 downto 0) => fwd_data,\r
+ --FWD_DATA_VALID_IN(0) => fwd_datavalid,\r
+ --FWD_SOP_IN(0) => fwd_sop,\r
+ --FWD_EOP_IN(0) => fwd_eop,\r
+ --FWD_READY_OUT(0) => fwd_ready,\r
+ --FWD_FULL_OUT(0) => fwd_full,\r
+ ---- reset\r
+ --MAKE_RESET_OUT => open, -- reset by GbE --BUG: needs to be connected\r
+ ---- debug and status\r
+ --STATUS_OUT => open,\r
+ --DEBUG_OUT => open\r
+ --);\r
+\r
+\r
+\r
+-----------------------------------------------------------------------------\r
+---- Test registers\r
+-----------------------------------------------------------------------------\r
+--THE_REGS : process begin\r
+ --wait until rising_edge(clk_sys);\r
+ --busfwd_tx.ack <= '0';\r
+ --busfwd_tx.nack <= '0';\r
+ --busfwd_tx.unknown <= '0';\r
+\r
+ --if busfwd_rx.write = '1' then\r
+ --busfwd_tx.ack <= '1';\r
+ --case busfwd_rx.addr(7 downto 0) is\r
+ --when x"00" => fwd_dst_ip <= busfwd_rx.data;\r
+ --when x"01" => fwd_dst_port <= busfwd_rx.data(15 downto 0);\r
+ --when x"02" => fwd_dst_mac(31 downto 0) <= busfwd_rx.data;\r
+ --when x"03" => fwd_dst_mac(47 downto 32) <= busfwd_rx.data(15 downto 0);\r
+ --when x"04" => fwd_length <= busfwd_rx.data(15 downto 0);\r
+ --when x"05" => fwd_do_send <= busfwd_rx.data(0);\r
+ --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1';\r
+ --end case;\r
+ --elsif busfwd_rx.read = '1' then\r
+ --busfwd_tx.ack <= '1';\r
+ --case busfwd_rx.addr(7 downto 0) is\r
+ --when x"00" => busfwd_tx.data <= fwd_dst_ip;\r
+ --when x"01" => busfwd_tx.data <= x"0000" & fwd_dst_port;\r
+ --when x"02" => busfwd_tx.data <= fwd_dst_mac(31 downto 0);\r
+ --when x"03" => busfwd_tx.data <= x"0000" & fwd_dst_mac(47 downto 32);\r
+ --when x"04" => busfwd_tx.data <= x"0000" & fwd_length;\r
+ --when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send;\r
+ --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1';\r
+ --end case;\r
+ --end if;\r
+ --if reset_i = '1' then\r
+ --fwd_do_send <= '0';\r
+ --end if;\r
+--end process;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Output stage\r
+---------------------------------------------------------------------------\r
+ THE_OUT : entity work.testout\r
+ port map(\r
+ clkout => open,\r
+ refclk => clk_160,\r
+ reset => reset_i,\r
+ data => out_data,\r
+ data_cflag => open,\r
+ data_direction => (others => '0'),\r
+ data_loadn => (others => '1'),\r
+ data_move => (others => '0'),\r
+ dout => out_i\r
+ );\r
+\r
+ PROC_OUT : process\r
+ variable cnt : integer range 0 to 7;\r
+ begin\r
+ wait until rising_edge(clk_160);\r
+ cnt := cnt + 1;\r
+ case cnt is\r
+ when 0 => out_data <= x"ffff";\r
+ when 1 => out_data <= x"ffff";\r
+ when 2 => out_data <= x"ffff";\r
+ when 3 => out_data <= x"0000";\r
+ when 4 => out_data <= x"5555";\r
+ when 5 => out_data <= x"5555";\r
+ when 6 => out_data <= x"5555";\r
+ when 7 => out_data <= x"5555";\r
+ end case;\r
+ end process;\r
+\r
+ -- H3(3 downto 0) <= out_i(3 downto 0);\r
+ -- H4(3 downto 0) <= out_i(7 downto 4);\r
+\r
\r
---------------------------------------------------------------------------\r
-- GBT Core\r
jspc29 / trb5sc.git / commitdiff