Update threshold FPGA code

diff --cc thresholds/thresholds.prj
index 5c90a7caba2ee2f23a86c0f07278f96888c477f1,34f9f15e2c047cdee3f59e759e2744effd529653..0bb55f38a29f519fc3df648e0b344de8eea9aa7b
--- 1/thresholds/thresholds.prj
--- 2/thresholds/thresholds.prj
+++ b/thresholds/thresholds.prj
@@@ -8,16 -8,14 +8,14 @@@
  
  #add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
  add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
- add_file -vhdl -lib work "../../logicbox/code/uart_sctrl.vhd"
+ add_file -vhdl -lib work "../../dirich/code/spi_slave.vhd"
  add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd"
 -add_file -vhdl -lib work "../../mdcfee/code/pwm.vhd"
 +add_file -vhdl -lib work "../code/pwm_machxo.vhd"
- add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
- add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
  
- add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd"
- add_file -vhdl -lib work "../../logicbox/cores/efb.vhd"
- add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v"
- add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v"
+ #add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd"
+ #add_file -vhdl -lib work "../../logicbox/cores/efb.vhd"
+ #add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v"
+ #add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v"
  
  add_file -vhdl -lib work "thresholds.vhd"
  

diff --cc thresholds/thresholds.vhd
index 4bac2993f3cdb1480842eb235246b37d36bde8b5,f219a07af6ce7c10ca675931b3b62e3021e24663..b0de7917bca558b260f1cf8ec6b7da924a3635d9
--- 1/thresholds/thresholds.vhd
--- 2/thresholds/thresholds.vhd
+++ b/thresholds/thresholds.vhd
@@@ -10,14 -10,15 +10,12 @@@ use work.trb_net_std.all
  \r
  entity thresholds is\r
    port(\r
 -    --CLK    : in  std_logic;\r
 -  \r
 +    ID     : in  std_logic;\r
      OUTPUT : out std_logic_vector(15 downto 0);\r
-     TX_IN  : in  std_logic;\r
-     RX_OUT : out std_logic\r
- --     MISO_OUT : out std_logic;\r
- --     MOSI_IN  : in  std_logic;\r
- --     SCLK_IN  : in  std_logic;\r
- --     CS_IN    : in  std_logic\r
+     MISO_OUT : out std_logic;\r
+     MOSI_IN  : in  std_logic;\r
+     SCLK_IN  : in  std_logic;\r
 -    CS_IN    : in  std_logic;\r
 -    \r
 -    LED      : out std_logic_vector(7 downto 0)\r
++    CS_IN    : in  std_logic    \r
      );\r
  end entity;\r
  \r
@@@ -57,9 -58,8 +55,10 @@@ architecture arch of thresholds i
    signal flash_go      : std_logic;\r
    signal flash_busy    : std_logic;\r
    signal flash_err     : std_logic;\r
 -  \r
 +\r
 +  signal compensate_i  : signed(15 downto 0);\r
 +  signal pwm_i         : std_logic_vector(15 downto 0);\r
+   signal dummy_register : std_logic_vector(15 downto 0);\r
  \r
    component OSCH\r
      generic (NOM_FREQ: string := "33.25");\r
@@@ -135,20 -133,24 +132,23 @@@ PROC_REGS : process begi
    pwm_write_i<= '0';\r
    if bus_read = '1' then\r
      bus_ready <= '1';\r
-     case uart_addr is\r
+     case spi_addr is\r
 +      when x"10" => uart_tx_data <= std_logic_vector(compensate_i);\r
-       when x"ee" => uart_tx_data <= sed_debug;\r
+       when x"ee" => spi_tx_data <= sed_debug(15 downto 0);\r
+       when x"ef" => spi_tx_data <= sed_debug(31 downto 16);\r
 - \r
+       when x"e4" => spi_tx_data <= dummy_register;\r
 -      \r
      end case;\r
    elsif bus_write = '1' then\r
-     if uart_addr < x"10" then\r
-       pwm_data_i <= uart_rx_data(15 downto 0);\r
-       pwm_addr_i <= uart_addr(4 downto 0);\r
+     if spi_addr < x"10" then\r
+       pwm_data_i <= spi_rx_data(15 downto 0);\r
+       pwm_addr_i <= spi_addr(4 downto 0);\r
        pwm_write_i<= '1';\r
      else\r
-       case uart_addr is\r
- --         when x"10" => reg <= uart_rx_data;\r
+       case spi_addr is\r
 ---         when x"10" => reg <= spi_rx_data;\r
 +        when x"10" => compensate_i <= signed(uart_rx_data(15 downto 0);\r
 +        when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);\r
+         when x"ee" => controlsed_i <= spi_rx_data(3 downto 0);\r
 -        \r
+         when x"e4" => dummy_register <= spi_rx_data ;\r
        end case;\r
      end if;  \r
    end if;\r