Before Merge

diff --git a/code/soda_hub.vhd b/code/soda_hub.vhd
index b20d9383a5ead3e3cfe88243d444db5172109069..7c927cdab8bf4d33ff92fcf5ddcb5193cd4249bf 100644 (file)
--- a/code/soda_hub.vhd
+++ b/code/soda_hub.vhd
@@ -395,13 +395,13 @@ end process TRANSFORM;
                                buf_bus_data_out        <= calib_register_S(2);
                        elsif( (store_rd = '1') and (SODA_ADDR_IN = "0111") ) then
                                buf_bus_data_out        <= calib_register_S(3);
-                       elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then
+                       elsif( (store_rd = '1') and (SODA_ADDR_IN = "1000") ) then
                                buf_bus_data_out                <= CTRL_STATUS_register_S(0);
-                       elsif( (store_rd = '1') and (SODA_ADDR_IN = "0100") ) then
+                       elsif( (store_rd = '1') and (SODA_ADDR_IN = "1001") ) then
                                buf_bus_data_out                <= CTRL_STATUS_register_S(1);
-                       elsif( (store_rd = '1') and (SODA_ADDR_IN = "0101") ) then
+                       elsif( (store_rd = '1') and (SODA_ADDR_IN = "1010") ) then
                                buf_bus_data_out                <= CTRL_STATUS_register_S(2);
-                       elsif( (store_rd = '1') and (SODA_ADDR_IN = "0110") ) then
+                       elsif( (store_rd = '1') and (SODA_ADDR_IN = "1011") ) then
                                buf_bus_data_out                <= CTRL_STATUS_register_S(3);
                        end if;
                end if;

diff --git a/code/trb3_periph_sodasource.vhd b/code/trb3_periph_sodasource.vhd
index e97cf836e23b598c4e6915b0e43c7ccc40e182c5..d29cb1a806c657d5ca81234091a790ba8a5c8eb0 100644 (file)
--- a/code/trb3_periph_sodasource.vhd
+++ b/code/trb3_periph_sodasource.vhd
@@ -263,6 +263,7 @@ gen_200_PLL : if USE_125_MHZ = c_NO generate
        THE_MAIN_PLL : pll_in200_out100
                port map(
                        CLK   => CLK_GPLL_RIGHT,
+                       RESET => '0',\r
                        CLKOP => clk_100_osc,
                        CLKOK => clk_200_osc,
                        LOCK  => pll_lock
@@ -320,7 +321,7 @@ end generate;
       -- Status and control port
       STAT_OP            => med_stat_op(15 downto 0),
       CTRL_OP            => med_ctrl_op(15 downto 0),
-      STAT_DEBUG         => med_stat_debug(63 downto 0),
+      STAT_DEBUG         => open, --med_stat_debug(63 downto 0),\r
       CTRL_DEBUG         => (others => '0')
       );
 
@@ -560,12 +561,68 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down
                -- Status and control port
                STAT_OP                                 => med_stat_op(31 downto 16),
                CTRL_OP                                 => med_ctrl_op(31 downto 16),
-               STAT_DEBUG                              => open,
+               STAT_DEBUG                              => med_stat_debug(63 downto 0),\r
                CTRL_DEBUG                              => (others => '0')
        );      
 
+-- THE_SYNC_LINK : med_ecp3_sfp_sync\r
+--    generic map(\r
+--       SERDES_NUM  => 0,    --number of serdes in quad\r
+--       IS_SYNC_SLAVE => c_NO\r
+--       )\r
+--    port map(\r
+--       CLK                  => clk_200_osc,\r
+--       SYSCLK               => clk_100_osc,\r
+--       RESET                => reset_i,\r
+--       CLEAR                => clear_i,\r
+--       --Internal Connection for TrbNet data -> not used a.t.m.\r
+--       MED_DATA_IN          => med_data_out(31 downto 16),\r
+--       MED_PACKET_NUM_IN    => med_packet_num_out(5 downto 3),\r
+--       MED_DATAREADY_IN     => med_dataready_out(1),\r
+--       MED_READ_OUT         => med_read_in(1),\r
+--       MED_DATA_OUT         => med_data_in(31 downto 16),\r
+--       MED_PACKET_NUM_OUT   => med_packet_num_in(5 downto 3),\r
+--       MED_DATAREADY_OUT    => med_dataready_in(1),\r
+--       MED_READ_IN          => med_read_out(1),\r
+--       CLK_RX_HALF_OUT      => soda_rx_clock_half,\r
+--       CLK_RX_FULL_OUT      => soda_rx_clock_full,\r
+-- --       TX_HALF_CLK_OUT      => soda_tx_clock_half,\r
+-- --       TX_FULL_CLK_OUT      => soda_tx_clock_full,\r
+-- \r
+--       RX_DLM               => rx_dlm_i,\r
+--       RX_DLM_WORD          => rx_dlm_word,\r
+--       TX_DLM               => tx_dlm_i,\r
+--       TX_DLM_WORD          => tx_dlm_word,\r
+-- --       TX_DLM_PREVIEW_IN    => tx_dlm_preview_S,       --PL!\r
+-- --       LINK_PHASE_OUT       => link_phase_S,     --PL!\r
+--       --SFP Connection\r
+--       SD_RXD_P_IN          => SERDES_ADDON_RX(0),\r
+--       SD_RXD_N_IN          => SERDES_ADDON_RX(1),\r
+--       SD_TXD_P_OUT         => SERDES_ADDON_TX(0),\r
+--       SD_TXD_N_OUT         => SERDES_ADDON_TX(1),\r
+--       SD_REFCLK_P_IN       => '0',\r
+--       SD_REFCLK_N_IN       => '0',\r
+--       SD_PRSNT_N_IN        => SFP_MOD0(1),\r
+--       SD_LOS_IN            => SFP_LOS(1),\r
+--       SD_TXDIS_OUT         => sfp_txdis_S(1),   --SFP_TXDIS(1),\r
+-- \r
+--       SCI_DATA_IN          => sci2_data_in,\r
+--       SCI_DATA_OUT         => sci2_data_out,\r
+--       SCI_ADDR             => sci2_addr,\r
+--       SCI_READ             => sci2_read,\r
+--       SCI_WRITE            => sci2_write,\r
+--       SCI_ACK              => sci2_ack,  \r
+--       SCI_NACK             => sci2_nack,\r
+--       -- Status and control port\r
+--       STAT_OP              => med_stat_op(31 downto 16),\r
+--       CTRL_OP              => med_ctrl_op(31 downto 16),\r
+--       STAT_DEBUG           => med_stat_debug(63 downto 0),\r
+--       CTRL_DEBUG           => (others => '0')\r
+--    );       \r
+       \r
        SFP_TXDIS(1)    <=      sfp_txdis_S(1);
 
+       \r
 ---------------------------------------------------------------------------
 -- Burst- and 40MHz cycle generator
 ---------------------------------------------------------------------------         
@@ -594,7 +651,7 @@ THE_SODA_SOURCE : soda_source
                RESET                                           => reset_i,
 \r
                SODA_BURST_PULSE_IN     => SOB_S,
-               SODA_CYCLE_IN                           => soda_40mhz_cycle_S,
+               SODA_CYCLE_IN                           => soda_40mhz_cycle_S,\r
 
                RX_DLM_WORD_IN                  => rx_dlm_word,
                RX_DLM_IN                               => rx_dlm_i,
@@ -627,44 +684,37 @@ THE_SODA_SOURCE : soda_source
 ---------------------------------------------------------------------------
 -- GREEN LED under sfp
 ---------------------------------------------------------------------------    
-       LED_LINKOK(1)   <= SFP_LOS(1);  --med_stat_op(8);
+       LED_LINKOK(1)   <= not med_stat_op(9);\r
        LED_LINKOK(2)   <=      SFP_LOS(2);
        LED_LINKOK(3)   <= SFP_LOS(3);
        LED_LINKOK(4)   <= SFP_LOS(4);
        LED_LINKOK(5)   <= SFP_LOS(5);
        LED_LINKOK(6)   <= SFP_LOS(6);
 
-       LED_RX(1)               <= '1' when (med_stat_op(10)='0') else '0';     -- rx_allow
+       LED_RX(1)               <= not (med_stat_op(11) or med_stat_op(10));\r
        LED_RX(2)               <= '1';
        LED_RX(3)               <= '1';
        LED_RX(4)               <= '1';
        LED_RX(5)               <= '1';
        LED_RX(6)               <= '1';
        
-       LED_TX(1)               <= '1' when (med_stat_op(9)='0') else '0';      -- tx_allow
+       LED_TX(1)               <= not med_stat_op(12);\r
        LED_TX(2)               <= '1';
        LED_TX(3)               <= '1';
        LED_TX(4)               <= '1';
        LED_TX(5)               <= '1';
        LED_TX(6)               <= '1';
 
+-- STAT_OP(12) <= led_dlm or last_led_dlm;\r
+-- STAT_OP(11) <= led_tx or last_led_tx;\r
+-- STAT_OP(10) <= led_rx or last_led_rx;\r
+-- STAT_OP(9)  <= led_ok;      \r
+       \r
 ---------------------------------------------------------------------------
 -- Test Connector
 ---------------------------------------------------------------------------    
---  TEST_LINE(15 downto 0) <= (others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
-
-       blink : process (clk_100_osc)
-       begin
-               if rising_edge(clk_100_osc) then
-                       if (time_counter = x"FFFFFFFF") then
-                               time_counter <= x"00000000";
-                       else
-                               time_counter <= time_counter + 1;
-                       end if;
-               end if;
-   end process;
+ TEST_LINE(13 downto 0) <= med_stat_debug(13 downto 0);\r
+ TEST_LINE(14) <= soda_rx_clock_half;\r
+ TEST_LINE(15) <= soda_tx_clock_half;\r
 
 end trb3_periph_sodasource_arch;
\ No newline at end of file

diff --git a/ctsh.ldf b/ctsh.ldf
index e5c10ded198298618950b0cb2cc6312302558a66..649498b0cd4080bfff119729f043c7bc3054e29f 100644 (file)
--- a/ctsh.ldf
+++ b/ctsh.ldf
@@ -2,7 +2,7 @@
 <BaliProject version="3.2" title="ctsh" device="LFE3-150EA-8FN672C" default_implementation="ctsh">
     <Options/>
     <Implementation title="ctsh" dir="ctsh" description="ctsh" synthesis="synplify" default_strategy="Strategy1">
-        <Options top="Cu_trb3_periph_soda_hub"/>
+        <Options def_top="Cu_trb3_periph_soda_hub" top="Cu_trb3_periph_soda_hub"/>
         <Source name="code/soda_components.vhd" type="VHDL" type_short="VHDL">
             <Options/>
         </Source>

diff --git a/soda_client.lpf b/soda_client.lpf
index ae44d91b30b6bc6d3f02835233a3e692db2aad44..05dff1a7bfe83b25004b2d3a5c6590a4a851f3c2 100644 (file)
--- a/soda_client.lpf
+++ b/soda_client.lpf
@@ -161,5 +161,5 @@ USE PRIMARY NET "clk_200_osc" ;
 USE PRIMARY NET "clk_100_osc" ;
 FREQUENCY NET "clk_200_osc" 200.000000 MHz ;
 FREQUENCY NET "clk_100_osc" 100.000000 MHz ;
-FREQUENCY NET "THE_SYNC_LINK/rx_full_clk" 200.000000 MHz ;
-FREQUENCY NET "THE_SYNC_LINK/rx_half_clk" 100.000000 MHz ;
+FREQUENCY NET "rx_full_clk" 200.000000 MHz ;
+FREQUENCY NET "rx_half_clk" 100.000000 MHz ;

diff --git a/soda_client/serdes_sync_upstream.txt b/soda_client/serdes_sync_upstream.txt
index a057cb3f6f141d77e64032356708bb8ee8cad9e1..9f2bf0dd014150a12899fdf00327afa2a06bdedb 100644 (file)
--- a/soda_client/serdes_sync_upstream.txt
+++ b/soda_client/serdes_sync_upstream.txt
@@ -44,7 +44,7 @@ CH3_COMMA_M             "1111111100"
 CH3_RXWA                "ENABLED"
 CH3_ILSM                "ENABLED"
 CH3_CTC                 "DISABLED"
-CH3_CC_MATCH4           "0100011100"
+CH3_CC_MATCH4           "0000000000"
 CH3_CC_MATCH_MODE       "1"
 CH3_CC_MIN_IPG          "3"
 CCHMARK                 "9"