updated fifo, Jan

diff --git a/trb_net16_fifo.vhd b/trb_net16_fifo.vhd
index 234e653be4b8c3bd0ee881bda87328a6a48f8355..0a3c9889bca59520d0ecfb85f0b4d5e085eccaed 100644 (file)
--- a/trb_net16_fifo.vhd
+++ b/trb_net16_fifo.vhd
@@ -39,7 +39,9 @@ architecture trb_net16_fifo_arch of trb_net16_fifo is
 
   component trb_net_fifo is
     generic (WIDTH : integer := DATA_WIDTH + NUM_WIDTH;   -- FIFO word width
-            DEPTH : integer := DEPTH + 2);
+            DEPTH : integer := DEPTH + 2;
+            FORCE_LUT : integer := 0
+            );
     port (
       CLK    : in std_logic;
       RESET  : in std_logic;

diff --git a/trb_net_fifo.vhd b/trb_net_fifo.vhd
index 582182cfd89e96a7cd7fa68c132046410a30dd95..21174a1596ea8e35921de3016012ef672510a581 100644 (file)
--- a/trb_net_fifo.vhd
+++ b/trb_net_fifo.vhd
@@ -14,7 +14,7 @@ entity trb_net_fifo is
   
   generic (WIDTH : integer := 18;      -- FIFO word width
            DEPTH : integer := 3;     -- Depth of the FIFO, 2^(n+1)
-           FORCE_LUT : integer range 0 to 1 := 0): --don't allow use of BlockRAM
+           FORCE_LUT : integer range 0 to 1 := 0); --don't allow use of BlockRAM
 
   port (CLK    : in std_logic;                 
         RESET  : in std_logic;