--- /dev/null
+-- endpoint for stand-along GbE with only slow control
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.config.all;
+
+
+entity trb_net16_endpoint_standalone_sctrl is
+ generic (
+ FIFO_TO_INT_DEPTH : integer := 6;
+ FIFO_TO_APL_DEPTH : integer := 6;
+ APL_WRITE_ALL_WORDS : integer := c_NO;
+ ADDRESS_MASK : std_logic_vector(15 downto 0) := x"FFFF";
+ BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"FF";
+ REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
+ REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO;
+ REGIO_USE_1WIRE_INTERFACE : integer range 0 to 4 := c_YES
+ );
+
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic := '1';
+
+ --Port to GbE
+ GSC_INIT_DATAREADY_IN : in std_logic;
+ GSC_INIT_DATA_IN : in std_logic_vector(15 downto 0);
+ GSC_INIT_PACKET_NUM_IN : in std_logic_vector(2 downto 0);
+ GSC_INIT_READ_OUT : out std_logic;
+ GSC_REPLY_DATAREADY_OUT : out std_logic;
+ GSC_REPLY_DATA_OUT : out std_logic_vector(15 downto 0);
+ GSC_REPLY_PACKET_NUM_OUT : out std_logic_vector(2 downto 0);
+ GSC_REPLY_READ_IN : in std_logic;
+ GBE_MAKE_RESET_IN : in std_logic; --for monitoring only
+
+ --Slow Control Port
+ --common registers 0x00-0x2F
+ REGIO_COMMON_STAT_REG_IN : in std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
+ REGIO_COMMON_CTRL_REG_OUT : out std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ REGIO_COMMON_STAT_STROBE_OUT : out std_logic_vector(std_COMSTATREG-1 downto 0);
+ REGIO_COMMON_CTRL_STROBE_OUT : out std_logic_vector(std_COMCTRLREG-1 downto 0);
+
+ --internal data port
+ BUS_RX : out CTRLBUS_RX;
+ BUS_TX : in CTRLBUS_TX;
+ --Data port - external master (e.g. Flash or Debug)
+ BUS_MASTER_IN : out CTRLBUS_TX;
+ BUS_MASTER_OUT : in CTRLBUS_RX := (data => (others => '0'), addr => (others => '0'), write => '0', read => '0', timeout => '0');
+ BUS_MASTER_ACTIVE : in std_logic := '0';
+
+ --Sensors & ID
+ ONEWIRE_INOUT : inout std_logic;
+ I2C_SCL : inout std_logic;
+ I2C_SDA : inout std_logic;
+
+ TIMERS_OUT : out TIMERS; --clock ticks, temperature, unique id
+ MY_ADDRESS_OUT : out std_logic_vector(15 downto 0)
+
+ );
+end entity;
+
+architecture arch of trb_net16_endpoint_standalone_sctrl is
+
+ signal temperature_i : std_logic_vector (11 downto 0);
+ signal unique_id_i : std_logic_vector (63 downto 0);
+ signal my_address_i : std_logic_vector (15 downto 0);
+ signal regio_rx : CTRLBUS_RX;
+ signal make_trbnet_reset : std_logic;
+ signal last_make_trbnet_reset : std_logic;
+ signal link_and_reset_status : std_logic_vector(3 downto 0);
+
+ signal buf_IDRAM_DATA_IN : std_logic_vector(15 downto 0);
+ signal buf_IDRAM_DATA_OUT : std_logic_vector(15 downto 0);
+ signal buf_IDRAM_ADDR_IN : std_logic_vector(2 downto 0);
+ signal buf_IDRAM_WR_IN : std_logic;
+ signal buf_stat_onewire : std_logic_vector(31 downto 0);
+
+ signal buf_COMMON_STAT_REG_IN : std_logic_vector(std_COMSTATREG*32-1 downto 0);
+ signal buf_COMMON_CTRL_REG_OUT : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
+ signal buf_COMMON_STAT_REG_STROBE : std_logic_vector(std_COMSTATREG-1 downto 0);
+ signal buf_COMMON_CTRL_REG_STROBE : std_logic_vector(std_COMCTRLREG-1 downto 0);
+
+ signal buf_APL_DATA_IN : std_logic_vector(15 downto 0);
+ signal buf_APL_PACKET_NUM_IN : std_logic_vector(2 downto 0);
+ signal buf_APL_DATAREADY_IN : std_logic;
+ signal buf_APL_READ_OUT : std_logic;
+ signal buf_APL_SHORT_TRANSFER_IN : std_logic_vector(3 downto 0);
+ signal buf_APL_DTYPE_IN : std_logic_vector(3 downto 0);
+ signal buf_APL_ERROR_PATTERN_IN : std_logic_vector(31 downto 0);
+ signal buf_APL_SEND_IN : std_logic;
+ signal buf_APL_DATA_OUT : std_logic_vector(15 downto 0);
+ signal buf_APL_PACKET_NUM_OUT : std_logic_vector(2 downto 0);
+ signal buf_APL_DATAREADY_OUT : std_logic;
+ signal buf_APL_READ_IN : std_logic;
+ signal buf_APL_TYP_OUT : std_logic_vector(2 downto 0);
+ signal buf_APL_RUN_OUT : std_logic;
+ signal buf_APL_SEQNR_OUT : std_logic_vector(7 downto 0);
+
+
+
+begin
+
+ DAT_PASSIVE_API: trb_net16_api_base
+ generic map (
+ API_TYPE => c_API_PASSIVE,
+ FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH,
+ FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH,
+ FORCE_REPLY => c_YES,
+ SBUF_VERSION => 0,
+ USE_VENDOR_CORES => c_YES,
+ SECURE_MODE_TO_APL => c_YES,
+ SECURE_MODE_TO_INT => c_YES,
+ APL_WRITE_ALL_WORDS => c_NO,
+ ADDRESS_MASK => ADDRESS_MASK,
+ BROADCAST_BITMASK => BROADCAST_BITMASK,
+ BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR
+ )
+ port map (
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+ -- APL Transmitter port
+ APL_DATA_IN => buf_APL_DATA_IN,
+ APL_PACKET_NUM_IN => buf_APL_PACKET_NUM_IN,
+ APL_DATAREADY_IN => buf_APL_DATAREADY_IN,
+ APL_READ_OUT => buf_APL_READ_OUT,
+ APL_SHORT_TRANSFER_IN => buf_APL_SHORT_TRANSFER_IN,
+ APL_DTYPE_IN => buf_APL_DTYPE_IN,
+ APL_ERROR_PATTERN_IN => buf_APL_ERROR_PATTERN_IN,
+ APL_SEND_IN => buf_APL_SEND_IN,
+ APL_TARGET_ADDRESS_IN => (others => '0'),
+ -- Receiver port
+ APL_DATA_OUT => buf_APL_DATA_OUT,
+ APL_PACKET_NUM_OUT=> buf_APL_PACKET_NUM_OUT,
+ APL_TYP_OUT => buf_APL_TYP_OUT,
+ APL_DATAREADY_OUT => buf_APL_DATAREADY_OUT,
+ APL_READ_IN => buf_APL_READ_IN,
+ -- APL Control port
+ APL_RUN_OUT => buf_APL_RUN_OUT,
+ APL_MY_ADDRESS_IN => my_address_i,
+ APL_SEQNR_OUT => buf_APL_SEQNR_OUT,
+ APL_LENGTH_IN => (others => '1'),
+ -- Internal direction port
+ INT_MASTER_DATAREADY_OUT => open,
+ INT_MASTER_DATA_OUT => open,
+ INT_MASTER_PACKET_NUM_OUT=> open,
+ INT_MASTER_READ_IN => '1',
+ INT_MASTER_DATAREADY_IN => GSC_INIT_DATAREADY_IN,
+ INT_MASTER_DATA_IN => GSC_INIT_DATA_IN,
+ INT_MASTER_PACKET_NUM_IN => GSC_INIT_PACKET_NUM_IN,
+ INT_MASTER_READ_OUT => GSC_INIT_READ_OUT,
+ INT_SLAVE_DATAREADY_OUT => GSC_REPLY_DATAREADY_OUT,
+ INT_SLAVE_DATA_OUT => GSC_REPLY_DATA_OUT,
+ INT_SLAVE_PACKET_NUM_OUT => GSC_REPLY_PACKET_NUM_OUT,
+ INT_SLAVE_READ_IN => GSC_REPLY_READ_IN,
+ INT_SLAVE_DATAREADY_IN => '0',
+ INT_SLAVE_DATA_IN => x"0000",
+ INT_SLAVE_PACKET_NUM_IN => "000",
+ INT_SLAVE_READ_OUT => open,
+ -- Status and control port
+ CTRL_SEQNR_RESET => buf_COMMON_CTRL_REG_OUT(10),
+ STAT_FIFO_TO_INT => open,
+ STAT_FIFO_TO_APL => open
+ );
+
+
+ regIO : trb_net16_regIO
+ generic map(
+ NUM_STAT_REGS => 0,
+ NUM_CTRL_REGS => 0,
+ INIT_CTRL_REGS => (others => '0'),
+ USED_CTRL_REGS => (others => '0'),
+ USED_CTRL_BITMASK => (others => '0'),
+ INCLUDED_FEATURES => INCLUDED_FEATURES,
+ HARDWARE_VERSION => HARDWARE_INFO,
+ CLOCK_FREQ => CLOCK_FREQUENCY
+ )
+ port map(
+ -- Misc
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => '1',
+ -- Port to API
+ API_DATA_OUT => buf_APL_DATA_IN,
+ API_PACKET_NUM_OUT => buf_APL_PACKET_NUM_IN,
+ API_DATAREADY_OUT => buf_APL_DATAREADY_IN,
+ API_READ_IN => buf_APL_READ_OUT,
+ API_SHORT_TRANSFER_OUT => buf_APL_SHORT_TRANSFER_IN,
+ API_DTYPE_OUT => buf_APL_DTYPE_IN,
+ API_ERROR_PATTERN_OUT => buf_APL_ERROR_PATTERN_IN,
+ API_SEND_OUT => buf_APL_SEND_IN,
+ API_DATA_IN => buf_APL_DATA_OUT,
+ API_PACKET_NUM_IN => buf_APL_PACKET_NUM_OUT,
+ API_TYP_IN => buf_APL_TYP_OUT,
+ API_DATAREADY_IN => buf_APL_DATAREADY_OUT,
+ API_READ_OUT => buf_APL_READ_IN,
+ API_RUN_IN => buf_APL_RUN_OUT,
+ API_SEQNR_IN => buf_APL_SEQNR_OUT,
+ --Port to write Unique ID
+ IDRAM_DATA_IN => buf_IDRAM_DATA_IN,
+ IDRAM_DATA_OUT => open,
+ IDRAM_ADDR_IN => buf_IDRAM_ADDR_IN,
+ IDRAM_WR_IN => buf_IDRAM_WR_IN,
+ MY_ADDRESS_OUT => my_address_i,
+ TRIGGER_MONITOR => '0',
+ GLOBAL_TIME => TIMERS_OUT.microsecond,
+ LOCAL_TIME => TIMERS_OUT.clock,
+ TIME_SINCE_LAST_TRG => TIMERS_OUT.last_trigger,
+ TIMER_US_TICK => TIMERS_OUT.tick_us,
+ TIMER_MS_TICK => TIMERS_OUT.tick_ms,
+ --Common Register in / out
+ COMMON_STAT_REG_IN => buf_COMMON_STAT_REG_IN,
+ COMMON_CTRL_REG_OUT => buf_COMMON_CTRL_REG_OUT,
+ COMMON_STAT_REG_STROBE => buf_COMMON_STAT_REG_STROBE,
+ COMMON_CTRL_REG_STROBE => buf_COMMON_CTRL_REG_STROBE,
+ --Custom Register in / out
+ REGISTERS_IN => (others => '0'),
+ REGISTERS_OUT => open,
+ STAT_REG_STROBE => open,
+ CTRL_REG_STROBE => open,
+ --Data bus
+ DAT_ADDR_OUT => regio_rx.addr,
+ DAT_READ_ENABLE_OUT => regio_rx.read,
+ DAT_WRITE_ENABLE_OUT => regio_rx.write,
+ DAT_DATA_OUT => regio_rx.data,
+ DAT_DATA_IN => BUS_TX.data,
+ DAT_DATAREADY_IN => BUS_TX.ack,
+ DAT_NO_MORE_DATA_IN => BUS_TX.nack,
+ DAT_UNKNOWN_ADDR_IN => BUS_TX.unknown,
+ DAT_TIMEOUT_OUT => regio_rx.timeout,
+ DAT_WRITE_ACK_IN => BUS_TX.ack,
+ STAT => open,
+ STAT_ADDR_DEBUG => open
+ );
+
+ REGIO_COMMON_STAT_STROBE_OUT <= buf_COMMON_STAT_REG_STROBE;
+ REGIO_COMMON_CTRL_STROBE_OUT <= buf_COMMON_CTRL_REG_STROBE;
+ REGIO_COMMON_CTRL_REG_OUT <= buf_COMMON_CTRL_REG_OUT;
+
+ TIMERS_OUT.temperature <= temperature_i;
+ TIMERS_OUT.uid <= unique_id_i;
+
+ BUS_RX <= regio_rx when BUS_MASTER_ACTIVE = '0' else BUS_MASTER_OUT;
+ BUS_MASTER_IN <= BUS_TX;
+ MY_ADDRESS_OUT <= my_address_i;
+-------------------------------------------------
+-- ID Chips
+-------------------------------------------------
+ assert REGIO_USE_1WIRE_INTERFACE /= c_NO report "No ID chip is not supported" severity error;
+ assert REGIO_USE_1WIRE_INTERFACE /= c_MONITOR report "Onewire monitor is not supported" severity error;
+
+ gen_XilinxDNA : if REGIO_USE_1WIRE_INTERFACE = c_XDNA generate
+ XilinxDNA : trb_net_xdna
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ DATA_OUT => buf_IDRAM_DATA_IN,
+ ADDR_OUT => buf_IDRAM_ADDR_IN,
+ WRITE_OUT=> buf_IDRAM_WR_IN,
+ TEMP_OUT => temperature_i,
+ ID_OUT => unique_id_i
+ );
+ end generate;
+
+ gen_1wire : if REGIO_USE_1WIRE_INTERFACE = c_YES generate
+ onewire_interface : trb_net_onewire
+ generic map(
+ USE_TEMPERATURE_READOUT => c_YES,
+ CLK_PERIOD => 10
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ --connection to 1-wire interface
+ ONEWIRE => ONEWIRE_INOUT,
+ MONITOR_OUT => open,
+ --connection to id ram, according to memory map in TrbNetRegIO
+ DATA_OUT => buf_IDRAM_DATA_IN,
+ ADDR_OUT => buf_IDRAM_ADDR_IN,
+ WRITE_OUT=> buf_IDRAM_WR_IN,
+ TEMP_OUT => temperature_i,
+ ID_OUT => unique_id_i,
+ STAT => buf_stat_onewire
+ );
+ end generate;
+
+ gen_i2c : if REGIO_USE_1WIRE_INTERFACE = c_I2C generate
+ i2c_interface : trb_net_i2cwire
+ generic map(
+ USE_TEMPERATURE_READOUT => c_YES,
+ CLK_PERIOD => 10
+ )
+ port map(
+ CLK => CLK,
+ RESET => RESET,
+ READOUT_ENABLE_IN => '1',
+ --connection to I2C interface
+ SCL_INOUT => I2C_SCL,
+ SDA_INOUT => I2C_SDA,
+ --connection to id ram, according to memory map in TrbNetRegIO
+ DATA_OUT => buf_IDRAM_DATA_IN,
+ ADDR_OUT => buf_IDRAM_ADDR_IN,
+ WRITE_OUT => buf_IDRAM_WR_IN,
+ TEMP_OUT => temperature_i,
+ ID_OUT => unique_id_i,
+ STAT => buf_stat_onewire
+ );
+ end generate;
+
+
+-------------------------------------------------
+-- Common Status Register
+-------------------------------------------------
+ proc_gen_common_stat_regs : process(REGIO_COMMON_STAT_REG_IN, temperature_i, buf_stat_onewire)
+ begin
+ buf_COMMON_STAT_REG_IN <= REGIO_COMMON_STAT_REG_IN;
+ buf_COMMON_STAT_REG_IN(31 downto 20) <= temperature_i;
+ buf_COMMON_STAT_REG_IN(131 downto 128) <= link_and_reset_status(3 downto 0);
+ buf_COMMON_STAT_REG_IN(319 downto 288) <= buf_stat_onewire;
+ end process;
+
+
+ REG_LINK_ERROR : process(CLK)
+ begin
+ if rising_edge(CLK) then
+
+ if make_trbnet_reset = '1' then
+ link_and_reset_status(3 downto 0) <= link_and_reset_status(3 downto 0) + '1';
+ end if;
+
+ if buf_COMMON_CTRL_REG_OUT(5) = '1' then
+ link_and_reset_status <= (others => '0');
+ end if;
+
+ end if;
+ end process;
+
+ PROC_FIND_TRBNET_RESET : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ last_make_trbnet_reset <= GBE_MAKE_RESET_IN;
+ make_trbnet_reset <= GBE_MAKE_RESET_IN and not last_make_trbnet_reset;
+ end if;
+ end process;
+
+end architecture;
jspc29 / trbnet.git / commitdiff