new entity for generation of mbs tiggers, based on DLM words/signals

diff --git a/src/mbs_generator_cbmrich.vhd b/src/mbs_generator_cbmrich.vhd
new file mode 100644 (file)
index 0000000..ac7c977
--- /dev/null
+++ b/src/mbs_generator_cbmrich.vhd
@@ -0,0 +1,115 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+use work.trb3_components.all;
+
+
+entity mbs_generator_cbmrich is
+   port(
+      CLK_SYS               : in  std_logic;  -- e.g. 100 MHz
+      CLK_RX                : in  std_logic;  -- 200MHz from SERDES
+      RESET_IN              : in  std_logic;  -- could be used after busy_release to make sure entity is in correct state
+
+      DLM_RX_IN             : in  std_logic;  -- flag of inoming dlm word
+      DLM_RX_DATA           : in  std_logic_vector( 7 downto 0); -- data of the dlm word. valid untill next dlm_rx_in
+      
+      MBS_LOC_TRIG          : out std_logic;
+      MBS_LOC_TRIG_NUM      : out std_logic_vector(15 downto 0);
+      
+      BUS_RX                : in  CTRLBUS_RX;
+      BUS_TX                : out CTRLBUS_TX
+   );
+end entity;
+
+architecture mbs_generator_cbmrich_arch of mbs_generator_cbmrich is
+
+  signal mbs_local_trigger     : std_logic;
+  signal mbs_local_trigger_num : std_logic_vector(15 downto 0);
+  
+  signal dlm_rx_i              : std_logic;
+  signal dlm_rx_data_i         : std_logic_vector(7 downto 0);
+
+begin
+
+
+---------------------------------------------------------------------------
+-- Generation of Trigger Signal for MBS Transmitter
+--------------------------------------------------------------------------- 
+
+   dlm_rx_i      <= DLM_RX_IN;
+   dlm_rx_data_i <= DLM_RX_DATA;
+
+   THE_LOCAL_MBS_CREATE : process
+     variable cnt : unsigned(17 downto 0) := (others => '0');
+   begin
+--     wait until rising_edge(clk_sys);
+     wait until rising_edge(CLK_RX);
+     mbs_local_trigger <= '0';
+     if (RESET_IN = '1') then
+       cnt := 0;
+       mbs_local_trigger_num <= (others => '0');
+     elsif (dlm_rx_i = '1') then
+       mbs_local_trigger     <= '1';
+       mbs_local_trigger_num <= (others => '0');    
+       cnt := 20479;--(10240*2)-1;
+     else
+       cnt := cnt + 1;
+       if (cnt = 20479) then --(10240*2)-1;
+         mbs_local_trigger     <= '1';
+         mbs_local_trigger_num <= std_logic_vector(unsigned(mbs_local_trigger_num) + 1);
+       end if;
+       if (cnt = (10240*2)) then
+         mbs_local_trigger <= '1';
+         cnt := 0;
+       end if;
+     end if;
+   end process;
+   
+   
+  MBS_LOC_TRIG     <= mbs_local_trigger;
+  MBS_LOC_TRIG_NUM <= mbs_local_trigger_num;
+
+   
+---------------------------------------------------------------------------
+-- Bus Handler for slow control  (Curr. Address: 0xe400)
+--------------------------------------------------------------------------- 
+
+  proc_reg : process 
+  begin
+    wait until rising_edge(CLK_SYS);
+    BUS_TX.ack     <= '0';
+    BUS_TX.nack    <= '0';
+    BUS_TX.unknown <= '0';
+
+    if BUS_RX.write = '1' then
+      BUS_TX.ack <= '1';
+--       case BUS_RX.addr(11 downto 0) is
+--         when x"000"   => 
+--                 PLACEHOLDER <= BUS_RX.data(31 downto 0);
+-- 
+--         when others   =>
+--                 BUS_TX.ack      <= '0';
+--                 BUS_TX.unknown  <= '1';
+--       end case;
+      BUS_TX.ack      <= '0';
+      BUS_TX.unknown  <= '1';
+    end if;  
+    
+    if BUS_RX.read = '1' then
+      BUS_TX.ack <= '1';
+      if BUS_RX.addr(11 downto 4) = x"00" then
+        case BUS_RX.addr(3 downto 0) is
+          when x"0"     =>  BUS_TX.data(31 downto 0) <= x"12345678";
+        
+          when others   =>  BUS_TX.ack     <= '0';
+                            BUS_TX.unknown <= '1';
+        end case;
+      end if;
+    end if;  
+  end process;   
+
+end architecture;