fpga_aux_to_board : out std_logic_vector(9 downto 0);
--TRBv3 connections
+ TIMING_TRG_IN : in std_logic;
LVL1_TRG_DATA_VALID_IN : in std_logic;
LVL1_VALID_TIMING_TRG_IN : in std_logic;
LVL1_VALID_NOTIMING_TRG_IN : in std_logic;
--signal declarations
-- Bus Handler
- constant NUM_PORTS : integer := 6;
+ constant NUM_PORTS : integer := 7;
signal slv_read : std_logic_vector(NUM_PORTS-1 downto 0);
signal slv_write : std_logic_vector(NUM_PORTS-1 downto 0);
signal memdata : std_logic_vector(31 downto 0);
signal memwren : std_logic;
signal ro_busy : std_logic;
+
+ --data from event buffer
+ signal buffer_data : std_logic_vector(31 downto 0);
+ signal buffer_data_valid : std_logic;
+
+ --signals from trigger handler
+ signal valid_trigger_int : std_logic;
+ signal timing_trigger : std_logic;
+ signal status_trigger : std_logic;
+ signal buffer_fast_clear : std_logic;
+ signal flush_buffer : std_logic;
begin -- Behavioral
3 => x"0080", -- MuPix DACs
4 => x"0800", -- Hitbus Histograms
5 => x"0300", -- Event Buffer
+ 6 => x"0100", -- Trigger Handler
others => x"0000"),
PORT_ADDR_MASK
3 => 4, -- MuPix DACs
4 => 8, -- HitBus Histograms
5 => 8, -- Event Buffer
+ 6 => 8, -- Trigger Handler
others => 0)
--PORT_MASK_ENABLE => 1
MuPixData_in => memdata,
MuPixDataWr_in => memwren,
MuPixEndOfEvent_in => ro_busy,
- FEE_DATA_OUT => FEE_DATA_OUT,
- FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT,
- FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT,
+ FEE_DATA_OUT => buffer_data,
+ FEE_DATA_WRITE_OUT => buffer_data_valid,
+ FEE_DATA_FINISHED_OUT => open,
FEE_DATA_ALMOST_FULL_IN => FEE_DATA_ALMOST_FULL_IN,
+ valid_trigger_in => flush_buffer_int,
+ clear_buffer_in => buffer_fast_clear;
SLV_READ_IN => slv_read(5),
SLV_WRITE_IN => slv_write(5),
SLV_DATA_IN => slv_data_wr(5*32+31 downto 5*32),
SLV_NO_MORE_DATA_OUT => slv_no_more_data(5),
SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(5));
+
+ TriggerHandler_1: entity work.TriggerHandler
+ port map (
+ CLK_IN => clk,
+ RESET_IN => reset,
+ TIMING_TRIGGER_IN => TIMING_TRG_IN,
+ LVL1_TRG_DATA_VALID_IN => LVL1_TRG_DATA_VALID_IN,
+ LVL1_VALID_TIMING_TRG_IN => LVL1_VALID_TIMING_TRG_IN,
+ LVL1_VALID_NOTIMING_TRG_IN => LVL1_VALID_NOTIMING_TRG_IN,
+ LVL1_INVALID_TRG_IN => LVL1_INVALID_TRG_IN,
+ LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN,
+ LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN,
+ LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN,
+ LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN,
+ LVL1_INT_TRG_NUMBER_IN => LVL1_INT_TRG_NUMBER_IN,
+ FEE_DATA_OUT => FEE_DATA_OUT,
+ FEE_DATA_WRITE_OUT => FEE_DATA_WRITE_OUT,
+ FEE_DATA_FINISHED_OUT => FEE_DATA_FINISHED_OUT,
+ FEE_TRG_RELEASE_OUT => FEE_TRG_RELEASE_OUT,
+ FEE_TRG_STATUSBITS_OUT => FEE_TRG_STATUSBITS_OUT,
+ FEE_DATA_0_IN => buffer_data,
+ FEE_DATA_WRITE_0_IN => buffer_data_valid,
+ TRIGGER_BUSY_MUPIX_DATA_IN => ro_busy or buffer_data_valid,
+ VALID_TRIGGER_OUT => valid_trigger_int,
+ TRIGGER_TIMING_OUT => timing_trigger,
+ TRIGGER_STATUS_OUT => status_trigger,
+ FAST_CLEAR_OUT => buffer_fast_clear,
+ FLUSH_BUFFER_OUT => flush_buffer,
+ SLV_READ_IN => slv_read(6),
+ SLV_WRITE_IN => slv_write(6),
+ SLV_DATA_OUT => slv_data_rd(6*32+31 downto 6*32),
+ SLV_DATA_IN => slv_data_wr(6*32+31 downto 6*32),
+ SLV_ADDR_IN => slv_addr(6*32+31 downto 6*32),
+ SLV_ACK_OUT => slv_ack(6),
+ SLV_NO_MORE_DATA_OUT => slv_no_more_data(6),
+ SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6);
+
end Behavioral;
--Readout Indicator
ro_busy : out std_logic;
+ --trigger
+ trigger_ext : in std_logic;
+
--TRB SlowControl
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
architecture RTL of mupix_interface is
- type ro_state_type is (reset, waiting, readman, loadpix, pulld, loadcol, readcol, hitgenerator, hitgeneratorwait);
+ type ro_state_type is (reset, waiting, readman, loadpix, pulld, loadcol, readcol, hitgenerator, hitgeneratorwait,pause);
signal state : ro_state_type;
signal delcounter : unsigned(3 downto 0);
signal delaycounters : std_logic_vector(31 downto 0);
-
+ signal pauseregister : std_logic_vector(31 downto 0);
+ signal pausecounter : unsigned (31 downto 0);
signal ro_busy_int : std_logic;
-
signal graycount : std_logic_vector(7 downto 0);
-
signal eventcounter : unsigned(31 downto 0);
-
signal hitcounter : unsigned(10 downto 0);
-
signal triggering : std_logic;
signal busy_r : std_logic := '0';
signal continousread : std_logic;
signal gen_hit_time : std_logic_vector(7 downto 0) := (others => '0');
signal testoutro : std_logic_vector (127 downto 0);
-
-
- signal resetgraycounter : std_logic;
-
+
--Control Registers
+ signal resetgraycounter : std_logic;
signal roregwritten : std_logic := '0';
signal roregister : std_logic_vector(31 downto 0) := (others => '0');
signal rocontrolbits : std_logic_vector(31 downto 0) := (others => '0');
--x0023: Hit Generator
--x0024: Delay Counters
--x0025: EventCounter
+ --x0026: Pause Register
-----------------------------------------------------------------------------
SLV_HANDLER : process(clk)
when x"0025" =>
SLV_DATA_OUT <= std_logic_vector(eventcounter);
SLV_ACK_OUT <= '1';
+ when x"0026" =>
+ SLV_DATA_OUT <= pauseregister;
+ SLV_ACK_OUT <= '1';
when others =>
SLV_UNKNOWN_ADDR_OUT <= '1';
end case;
when x"0024" =>
delaycounters <= SLV_DATA_IN;
SLV_ACK_OUT <= '1';
+ when x"0026" =>
+ pauseregister <= SLV_DATA_IN;
+ SLV_ACK_OUT <= '1';
when others =>
SLV_UNKNOWN_ADDR_OUT <= '1';
end case;
--testout(15 downto 0) <= testoutro(15 downto 0);
-----------------------------------------------------------------------------
- --MuPix 3 Readout Statemachine
+ --MuPix 3/4/6 Readout Statemachine
-----------------------------------------------------------------------------
ro_statemachine : process(rstn, clk)
memwren <= '0';
ro_busy_int <= '0';
eventcounter <= (others => '0');
- --timeoutcounter <= (others => '0');
endofevent <= '0';
+ when pause =>
+ pausecounter <= pausecounter +1;
+ if(pausecounter = pauseregister) then
+ state <= waiting;
+ pausecounter <= (others => '0');
+ end if;
+ ldpix <= '0';
+ ldcol <= '0';
+ rdcol <= '0';
+ pulldown <= '0';
+ memwren <= '0';
+ endofevent <= '0';
+ ro_busy_int <= '0';
when waiting =>
testoutro(1) <= '1';
memwren <= '0';
pulldown <= '0';
if(readmanual = '1') then
state <= readman;
- elsif(continousread = '1' or readnow = '1') then
+ elsif(continousread = '1' or readnow = '1' or(triggering = '1' and trigger_ext = '1' and generatetriggeredhits = '0')) then
state <= loadpix;
ldpix <= '1';
delcounter <= unsigned(delaycounters(3 downto 0));
eventcounter <= eventcounter + 1;
- elsif(generatetriggeredhits = '1' and busy_r = '0') then
+ elsif(generatetriggeredhits = '1' and trigger_ext = '1') then
state <= hitgenerator;
delcounter <= "0100";
eventcounter <= eventcounter + 1;
elsif(delcounter = "0011") then -- write event counter
memdata <= std_logic_vector(eventcounter);
memwren <= '1';
- elsif(delcounter = "0001") then
- memwren <= '1';
- memdata <= x"00000000"; --add empty trigger
- --number
end if;
if(delcounter = "0000") then
state <= pulld;
when pulld =>
testoutro(3) <= '1';
memwren <= '0';
- if unsigned(delaycounters(7 downto 4)) = delcounter + 1 then
+ if unsigned(delaycounters(7 downto 4)) = delcounter then
pulldown <= '0';
end if;
delcounter <= delcounter - 1;
when loadcol =>
testoutro(4) <= '1';
memwren <= '0';
- if(delcounter + 1 = unsigned(delaycounters(11 downto 8))) then
+ if(delcounter = unsigned(delaycounters(11 downto 8))) then
ldcol <= '0';
end if;
delcounter <= delcounter - 1;
state <= loadcol;
endofevent <= '0';
- if(delcounter = "000" and priout = '1') then
+ if(delcounter = "0000" and priout = '1') then
state <= readcol;
rdcol <= '1';
delcounter <= unsigned(delaycounters(15 downto 12));
- elsif(delcounter = "000") then
+ elsif(delcounter = "0000") then
-- end of event
memwren <= '1';
memdata <= "10111110111011111011111011101111"; --0xBEEFBEEF
endofevent <= '1';
- state <= waiting;
+ state <= pause;
end if;
when readcol =>
testoutro(5) <= '1';
memwren <= '0';
state <= readcol;
endofevent <= '0';
- if(delcounter = "0010") then
+ if (delcounter = delaycounter(27 downto 24)) then
+ priout_reg <= priout;
+ end if;
+ if(delcounter = delaycounter(31 downto 28)) then
memdata <= "111100001111" & hit_col & hit_row & hit_time; --0xF0F
memwren <= '1';
- hitcounter <= hitcounter + 1;
+ hitcounter <= hitcounter + '1';
state <= readcol;
elsif(delcounter = "0000" and hitcounter = "11111111111") then
- -- 2048 hits - force end of event
+ -- 2048 hits - this makes no sense
+ -- force end of event
memwren <= '1';
memdata <= "10111110111011111011111011101111"; --0xBEEFBEEF
endofevent <= '1';
- state <= waiting;
+ state <= pause;
elsif(delcounter = "0000" and priout = '1') then
state <= readcol;
rdcol <= '1';
spi_ld_to_board : out std_logic;
fpga_led_to_board : out std_logic_vector(3 downto 0);
fpga_aux_to_board : out std_logic_vector(9 downto 0);
+ TIMING_TRG_IN : in std_logic;
LVL1_TRG_DATA_VALID_IN : in std_logic;
LVL1_VALID_TIMING_TRG_IN : in std_logic;
LVL1_VALID_NOTIMING_TRG_IN : in std_logic;
REGIO_UNKNOWN_ADDR_OUT : out std_logic);
end component;
- --Interface to MuPix 3/4
+ --Interface to MuPix 3/4/6
component mupix_interface
port (
rstn : in std_logic;
FEE_DATA_WRITE_OUT : out std_logic;
FEE_DATA_FINISHED_OUT : out std_logic;
FEE_DATA_ALMOST_FULL_IN : in std_logic;
+ valid_trigger_in : in std_logic;
+ clear_buffer_in : in std_logic;
SLV_READ_IN : in std_logic;
SLV_WRITE_IN : in std_logic;
SLV_DATA_IN : in std_logic_vector(31 downto 0);
SLV_NO_MORE_DATA_OUT : out std_logic;
SLV_UNKNOWN_ADDR_OUT : out std_logic);
end component;
-
+
+ --Trigger Handler
+ component TriggerHandler is
+ port (
+ CLK_IN : in std_logic;
+ RESET_IN : in std_logic;
+ TIMING_TRIGGER_IN : in std_logic;
+ LVL1_TRG_DATA_VALID_IN : in std_logic;
+ LVL1_VALID_TIMING_TRG_IN : in std_logic;
+ LVL1_VALID_NOTIMING_TRG_IN : in std_logic;
+ LVL1_INVALID_TRG_IN : in std_logic;
+ LVL1_TRG_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ LVL1_TRG_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
+ LVL1_INT_TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
+ FEE_DATA_OUT : out std_logic_vector(31 downto 0);
+ FEE_DATA_WRITE_OUT : out std_logic;
+ FEE_DATA_FINISHED_OUT : out std_logic;
+ FEE_TRG_RELEASE_OUT : out std_logic;
+ FEE_TRG_STATUSBITS_OUT : out std_logic_vector(31 downto 0);
+ FEE_DATA_0_IN : in std_logic_vector(31 downto 0);
+ FEE_DATA_WRITE_0_IN : in std_logic;
+ TRIGGER_BUSY_MUPIX_DATA_IN : in std_logic;
+ VALID_TRIGGER_OUT : out std_logic;
+ TRIGGER_TIMING_OUT : out std_logic;
+ TRIGGER_STATUS_OUT : out std_logic;
+ FAST_CLEAR_OUT : out std_logic;
+ FLUSH_BUFFER_OUT : out std_logic;
+ SLV_READ_IN : in std_logic;
+ SLV_WRITE_IN : in std_logic;
+ SLV_DATA_OUT : out std_logic_vector(31 downto 0);
+ SLV_DATA_IN : in std_logic_vector(31 downto 0);
+ SLV_ADDR_IN : in std_logic_vector(15 downto 0);
+ SLV_ACK_OUT : out std_logic;
+ SLV_NO_MORE_DATA_OUT : out std_logic;
+ SLV_UNKNOWN_ADDR_OUT : out std_logic);
+ end component TriggerHandler;
end mupix_components;
fpga_led_to_board => fpga_led_to_board,
fpga_aux_to_board => fpga_aux_to_board,
-
+ TIMING_TRG_IN => TRIGGER_RIGHT,
LVL1_TRG_DATA_VALID_IN => trg_data_valid_i,
LVL1_VALID_TIMING_TRG_IN => trg_timing_valid_i,
LVL1_VALID_NOTIMING_TRG_IN => trg_notiming_valid_i,
jspc29 / trb3.git / commitdiff