changed amps2 to new flash and SPI scheme, IF

diff --git a/amps2/padiwa_amps2.prj b/amps2/padiwa_amps2.prj
index 03d5ddc4296885f56b51dd634812a281f42cddd8..d7e790cfbf7448f6c47805fd426104456505f611 100644 (file)
--- a/amps2/padiwa_amps2.prj
+++ b/amps2/padiwa_amps2.prj
@@ -7,7 +7,8 @@
 add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.9_x64/cae_library/synthesis/vhdl/machxo3lf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "workdir/version.vhd"
-add_file -vhdl -lib work "../source/spi_slave.vhd"
+#add_file -vhdl -lib work "../source/spi_slave.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave.vhd"
 add_file -vhdl -lib work "../source/Stretcher.vhd"
 add_file -vhdl -lib work "../source/Stretcher_A.vhd"
 add_file -vhdl -lib work "../source/Stretcher_B.vhd"
@@ -25,6 +26,12 @@ add_file -vhdl -lib work "padiwa_amps2.vhd"
 #add_file -vhdl -lib work "../code/sedcheck.vhd"
 #add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
 
+add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash.vhd"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB.v"
+add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd"
+
 
 #implementation: "PadiwaAmps2"
 impl -add workdir -type fpga

diff --git a/amps2/padiwa_amps2.vhd b/amps2/padiwa_amps2.vhd
index dfe77e835c6892deefbff8f2ba174a39f0cb4d97..d0dc11152824cad6b9793d8d75bb413835c5b900 100644 (file)
--- a/amps2/padiwa_amps2.vhd
+++ b/amps2/padiwa_amps2.vhd
@@ -52,10 +52,10 @@ architecture arch of padiwa_amps2 is
   signal led_timer : led_timer_t;\r
   signal led_state : std_logic_vector(8 downto 1);\r
 \r
-  signal ram_write_i : std_logic;\r
-  signal ram_data_i: std_logic_vector(7 downto 0);\r
-  signal ram_data_o: std_logic_vector(7 downto 0);\r
-  signal ram_addr_i: std_logic_vector(3 downto 0);\r
+--  signal ram_write_i : std_logic;\r
+--  signal ram_data_i: std_logic_vector(7 downto 0);\r
+--  signal ram_data_o: std_logic_vector(7 downto 0);\r
+--  signal ram_addr_i: std_logic_vector(3 downto 0);\r
   signal temperature_i : std_logic_vector(11 downto 0);\r
 \r
  \r
@@ -63,18 +63,33 @@ architecture arch of padiwa_amps2 is
   signal INP_i       : std_logic_vector(15 downto 0);\r
   signal fast_input  : std_logic_vector(8  downto 1);\r
   signal slow_input  : std_logic_vector(8  downto 1);\r
-  signal spi_reg00_i : std_logic_vector(15 downto 0);\r
-  signal spi_reg10_i : std_logic_vector(15 downto 0);\r
-  signal spi_reg20_i : std_logic_vector(15 downto 0);\r
-  signal spi_reg40_i : std_logic_vector(15 downto 0);\r
-  signal spi_data_i  : std_logic_vector(15 downto 0);\r
-  signal spi_operation_i : std_logic_vector(3 downto 0);\r
-  signal spi_channel_i   : std_logic_vector(7 downto 0);\r
-  signal spi_write_i     : std_logic_vector(15 downto 0);\r
-  signal buf_SPI_OUT     : std_logic;\r
-  signal spi_debug_i     : std_logic_vector(15 downto 0);\r
-  signal last_spi_channel: std_logic_vector(7 downto 0);\r
-\r
+--  signal spi_reg00_i : std_logic_vector(15 downto 0);\r
+--  signal spi_reg10_i : std_logic_vector(15 downto 0);\r
+--  signal spi_reg20_i : std_logic_vector(15 downto 0);\r
+--  signal spi_reg40_i : std_logic_vector(15 downto 0);\r
+--  signal spi_data_i  : std_logic_vector(15 downto 0);\r
+--  signal spi_operation_i : std_logic_vector(3 downto 0);\r
+--  signal spi_channel_i   : std_logic_vector(7 downto 0);\r
+--  signal spi_write_i     : std_logic_vector(15 downto 0);\r
+--  signal buf_SPI_OUT     : std_logic;\r
+--  signal spi_debug_i     : std_logic_vector(15 downto 0);\r
+--  signal last_spi_channel: std_logic_vector(7 downto 0);\r
+  signal spi_rx_data : std_logic_vector(15 downto 0);\r
+  signal spi_tx_data : std_logic_vector(15 downto 0);\r
+  signal spi_addr    : std_logic_vector(7 downto 0);\r
+  signal bus_read    : std_logic := '0';\r
+  signal bus_write   : std_logic := '0';\r
+  signal bus_ready   : std_logic;\r
+  signal bus_busy    : std_logic;\r
+\r
+  signal spi_data_out  : std_logic_vector(15 downto 0);\r
+  signal spi_data_in   : std_logic_vector(15 downto 0);\r
+  signal spi_addr_out  : std_logic_vector(7 downto 0);\r
+  signal spi_write_out : std_logic;\r
+  signal spi_read_out  : std_logic;\r
+  signal spi_ready_in  : std_logic;\r
+  signal spi_busy_out  : std_logic;\r
+  \r
   \r
 \r
   signal inp_select    : integer range 0 to 31 := 0;\r
@@ -167,41 +182,78 @@ THE_PLL : entity work.pll_in133_out33_133_266
 ---------------------------------------------------------------------------\r
 -- SPI Interface\r
 ---------------------------------------------------------------------------  \r
-THE_SPI_SLAVE : entity work.spi_slave\r
-  port map(\r
-               CLK        => clk_i,\r
-    SPI_CLK    => SPI_CLK,\r
-    SPI_CS     => SPI_CS,\r
-    SPI_IN     => SPI_IN,\r
-    SPI_OUT    => buf_SPI_OUT,\r
-    DATA_OUT   => spi_data_i,\r
-    REG00_IN   => spi_reg00_i,\r
-    REG10_IN   => spi_reg10_i,\r
-    REG20_IN   => spi_reg20_i,\r
-    REG40_IN   => spi_reg40_i,\r
-    OPERATION_OUT => spi_operation_i,\r
-    CHANNEL_OUT   => spi_channel_i,\r
-    WRITE_OUT     => spi_write_i,\r
-    DEBUG_OUT     => spi_debug_i\r
-    );\r
-\r
-SPI_OUT <= buf_SPI_OUT;    \r
-\r
-spi_reg00_i <= pwm_data_o;\r
+--THE_SPI_SLAVE : entity work.spi_slave\r
+--  port map(\r
+--             CLK        => clk_i,\r
+--    SPI_CLK    => SPI_CLK,\r
+--    SPI_CS     => SPI_CS,\r
+--    SPI_IN     => SPI_IN,\r
+--    SPI_OUT    => buf_SPI_OUT,\r
+--    DATA_OUT   => spi_data_i,\r
+--    REG00_IN   => spi_reg00_i,\r
+--    REG10_IN   => spi_reg10_i,\r
+--    REG20_IN   => spi_reg20_i,\r
+--    REG40_IN   => spi_reg40_i,\r
+--    OPERATION_OUT => spi_operation_i,\r
+--    CHANNEL_OUT   => spi_channel_i,\r
+--    WRITE_OUT     => spi_write_i,\r
+--    DEBUG_OUT     => spi_debug_i\r
+--    );\r
+\r
+--SPI_OUT <= buf_SPI_OUT;    \r
+\r
+--spi_reg00_i <= pwm_data_o;\r
 -- spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(2 downto 0))));\r
 -- spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o;\r
-spi_reg10_i <= (others => '0');\r
-spi_reg40_i <= '0' & '0' & "000000" & ram_data_o;\r
-  \r
+--spi_reg10_i <= (others => '0');\r
+--spi_reg40_i <= '0' & '0' & "000000" & ram_data_o;\r
 \r
----------------------------------------------------------------------------\r
--- RAM Interface\r
----------------------------------------------------------------------------  \r
+THE_SPI : entity work.spi_slave\r
+  port map(\r
+    CLK       => clk_i,\r
+    SPI_CLK   => SPI_CLK,\r
+    SPI_CS    => SPI_CS,\r
+    SPI_IN    => SPI_IN,\r
+    SPI_OUT   => SPI_OUT,\r
+\r
+    DATA_OUT  => spi_data_out,\r
+    DATA_IN   => spi_data_in,\r
+    ADDR_OUT  => spi_addr_out,\r
+    WRITE_OUT => spi_write_out,\r
+    READ_OUT  => spi_read_out,\r
+    READY_IN  => spi_ready_in,\r
+\r
+    DEBUG     => open\r
+  );\r
 \r
 ---------------------------------------------------------------------------\r
 -- Flash Controller\r
 ---------------------------------------------------------------------------  \r
 \r
+THE_FLASH_CONTROLLER : entity generic_flash_ctrl\r
+  port map(\r
+    CLK => clk_i,\r
+    RESET => '0',\r
+\r
+    SPI_DATA_IN   => spi_data_out,\r
+    SPI_DATA_OUT  => spi_data_in,\r
+    SPI_ADDR_IN   => spi_addr_out,\r
+    SPI_WRITE_IN  => spi_write_out,\r
+    SPI_READ_IN   => spi_read_out,\r
+    SPI_READY_OUT => spi_ready_in,\r
+    SPI_BUSY_IN   => spi_busy_out,\r
+\r
+    LOC_DATA_OUT  => spi_rx_data,\r
+    LOC_DATA_IN   => spi_tx_data,\r
+    LOC_ADDR_OUT  => spi_addr,\r
+    LOC_WRITE_OUT => bus_write,\r
+    LOC_READ_OUT  => bus_read,\r
+    LOC_READY_IN  => bus_ready,\r
+    LOC_BUSY_OUT  => bus_busy\r
+  );\r
+    \r
+\r
+\r
 ---------------------------------------------------------------------------\r
 -- Temperature and UID reader\r
 ---------------------------------------------------------------------------  \r
@@ -215,64 +267,67 @@ temperature_i_s <= temperature_i when rising_edge(clk_33);
 comp_setting_s <= comp_setting when rising_edge(clk_33);\r
 temp_calc_i <= signed(temperature_i_s) * signed(comp_setting_s) when rising_edge(clk_33);\r
 \r
+\r
 gen_comp: if TEMP_CORRECTION = 1 generate\r
   compensate_i <= temp_calc_i(27 downto 12) when rising_edge(clk_33);\r
 end generate;\r
+\r
 gen_no_comp: if TEMP_CORRECTION = 0 generate\r
   compensate_i <= (others => '0');\r
-end generate;\r
-\r
-\r
+end generate;             \r
+             \r
 ---------------------------------------------------------------------------\r
--- I/O Register 0x20\r
+-- I/O Register\r
 ---------------------------------------------------------------------------  \r
-THE_IO_REG_READ : process begin\r
-  wait until rising_edge(clk_i);\r
-  if spi_channel_i(4) = '0' then\r
-    case spi_channel_i(3 downto 0) is\r
-      when x"0" => spi_reg20_i <= input_enable;\r
-      when x"1" => spi_reg20_i <= inp_status;\r
-      when x"2" => spi_reg20_i <= x"0" & "000" & led_status(8) & led_state ;\r
-      when x"3" => spi_reg20_i <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5));\r
-      when x"4" => spi_reg20_i <= inp_invert;\r
-      when x"5" => spi_reg20_i <= inp_stretch;\r
-      when x"6" => spi_reg20_i <= comp_setting;\r
-      when x"7" => spi_reg20_i <= x"00" & discharge_disable;\r
-      when x"8" => spi_reg20_i <= x"00" & discharge_override;\r
-      when x"9" => spi_reg20_i <= x"00" & discharge_highz;\r
-      when x"a" => spi_reg20_i <= x"00" & delay_invert;\r
-      when x"b" => spi_reg20_i <= x"00" & std_logic_vector(to_unsigned(delayselect,8));\r
---       when x"f" => spi_reg20_i <= ffarr_data; \r
-      when others => null;\r
-    end case;\r
-  else\r
-    case spi_channel_i(3 downto 0) is\r
-      when x"0" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));\r
-      when x"1" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));\r
-      when x"2" => spi_reg20_i <= x"0000";\r
-      when others => null;\r
-    end case;\r
-  end if;\r
-end process;\r
 \r
-THE_IO_REG_WRITE : process begin\r
+THE_IO_REG : process begin\r
   wait until rising_edge(clk_i);\r
-  if spi_write_i(2) = '1' then\r
-    case spi_channel_i(3 downto 0) is\r
-      when x"0" => input_enable <= spi_data_i;\r
-      when x"1" => null;\r
-      when x"2" => led_status <= spi_data_i(8 downto 0);\r
-      when x"3" => inp_select <= to_integer(unsigned(spi_data_i(4 downto 0)));\r
-      when x"4" => inp_invert <= spi_data_i;\r
-      when x"5" => inp_stretch <= spi_data_i;\r
-      when x"6" => comp_setting <= spi_data_i;\r
-      when x"7" => discharge_disable  <= spi_data_i(7 downto 0);\r
-      when x"8" => discharge_override <= spi_data_i(7 downto 0);\r
-      when x"9" => discharge_highz    <= spi_data_i(7 downto 0);\r
-      when x"a" => delay_invert       <= spi_data_i(7 downto 0);\r
-      when x"b" => delayselect        <= to_integer(unsigned(spi_data_i(7 downto 0)));\r
+  bus_ready     <= '0';\r
+  pwm_write_i   <= '0';    \r
+\r
+  if bus_read = '1' then\r
+    bus_ready <= '1';\r
+    case spi_addr is\r
+      when x"20" => spi_tx_data <= input_enable;\r
+      when x"21" => spi_tx_data <= inp_status;\r
+      when x"22" => spi_tx_data <= x"0" & "000" & led_status(8) & led_state ;\r
+      when x"23" => spi_tx_data <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5));\r
+      when x"24" => spi_tx_data <= inp_invert;\r
+      when x"25" => spi_tx_data <= inp_stretch;\r
+      when x"26" => spi_tx_data <= comp_setting;\r
+      when x"27" => spi_tx_data <= x"00" & discharge_disable;\r
+      when x"28" => spi_tx_data <= x"00" & discharge_override;\r
+      when x"29" => spi_tx_data <= x"00" & discharge_highz;\r
+      when x"2a" => spi_tx_data <= x"00" & delay_invert;\r
+      when x"2b" => spi_tx_data <= x"00" & std_logic_vector(to_unsigned(delayselect,8));\r
+\r
+      when x"30" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));\r
+      when x"31" => spi_tx_data <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));\r
+      when x"32" => spi_tx_data <= x"0000";\r
       when others => null;\r
     end case;\r
+  elsif bus_write = '1' then\r
+    if (spi_addr >= x"00") and (spi_addr < x"10") then  -- write directly to PWM\r
+      pwm_data_i  <= spi_rx_data;\r
+      pwm_addr_i  <= spi_addr(3 downto 0);\r
+      pwm_write_i <= '1';\r
+    else\r
+      case spi_addr is\r
+        when x"20" => input_enable <= spi_rx_data;\r
+        when x"21" => null;\r
+        when x"22" => led_status <= spi_rx_data(8 downto 0);\r
+        when x"23" => inp_select <= to_integer(unsigned(spi_rx_data(4 downto 0)));\r
+        when x"24" => inp_invert <= spi_rx_data;\r
+        when x"25" => inp_stretch <= spi_rx_data;\r
+        when x"26" => comp_setting <= spi_rx_data;\r
+        when x"27" => discharge_disable  <= spi_rx_data(7 downto 0);\r
+        when x"28" => discharge_override <= spi_rx_data(7 downto 0);\r
+        when x"29" => discharge_highz    <= spi_rx_data(7 downto 0);\r
+        when x"2a" => delay_invert       <= spi_rx_data(7 downto 0);\r
+        when x"2b" => delayselect        <= to_integer(unsigned(spi_rx_data(7 downto 0)));\r
+        when others => null;  \r
+      end case;\r
+    end if;\r
   end if;\r
 end process;\r
 \r
@@ -292,30 +347,6 @@ THE_PWM_GEN : entity work.pwm_generator
     );\r
 \r
 \r
-\r
--- PROC_PWM_DATA_MUX : process(fsm_copydat, spi_data_i, spi_write_i, spi_channel_i,\r
---                             pwm_fsm_addr, pwm_fsm_data_i, pwm_fsm_write,\r
---                             ram_fsm_addr_i, ram_fsm_data_i, ram_fsm_write_i)\r
--- begin\r
---   if(fsm_copydat = IDLE) then\r
-    pwm_data_i  <= spi_data_i;\r
-    pwm_write_i <= spi_write_i(0);\r
-    pwm_addr_i  <= spi_channel_i(3 downto 0);\r
-    ram_write_i <= spi_write_i(4);\r
-    ram_data_i  <= spi_data_i(7 downto 0);\r
-    ram_addr_i  <= spi_channel_i(3 downto 0);\r
---   else\r
---     pwm_data_i  <= pwm_fsm_data_i;\r
---     pwm_write_i <= pwm_fsm_write;\r
---     pwm_addr_i  <= pwm_fsm_addr;\r
---     ram_write_i <= ram_fsm_write_i;\r
---     ram_data_i  <= ram_fsm_data_i;\r
---     ram_addr_i  <= ram_fsm_addr_i;\r
---   end if;\r
--- end process;\r
-\r
-    \r
-\r
 ---------------------------------------------------------------------------\r
 -- LED\r
 ---------------------------------------------------------------------------\r