Adjusting timeout for external clock detection to allow for correct selection when...

diff --git a/adcaddon/config.vhd b/adcaddon/config.vhd
index cc5efa496a66659e9ced2cda9b3c0e209fed69c1..700293a91dc2776f3072c4ef1fc66b66a91d9d47 100644 (file)
--- a/adcaddon/config.vhd
+++ b/adcaddon/config.vhd
@@ -13,6 +13,7 @@ package config is
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
     constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
+    constant CLOCK_FAST_SELECT        : integer := c_NO; --fast clock select (135us) or slow (280ms)?
     
 --Use sync mode, RX clock for all parts of the FPGA
     constant USE_RXCLOCK            : integer := c_NO;

diff --git a/backplanemaster/config.vhd b/backplanemaster/config.vhd
index eb775b478a6ac2b35806726c9f6a310e03fd5804..4fe7a18e1e459d7d71a8534dae44355f7936c50b 100644 (file)
--- a/backplanemaster/config.vhd
+++ b/backplanemaster/config.vhd
@@ -14,6 +14,7 @@ package config is
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
     constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
+    constant CLOCK_FAST_SELECT        : integer := c_YES; --fast clock select (135us) or slow (280ms)?
     
 --Use sync mode, RX clock for all parts of the FPGA
     constant USE_RXCLOCK            : integer := c_NO;

diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd
index 6ad71bd16061a2a2b676f7c9f269f12db66f5ac4..77ba5d970e6637e5719f9349924028051e15026c 100644 (file)
--- a/code/clock_reset_handler.vhd
+++ b/code/clock_reset_handler.vhd
@@ -47,7 +47,7 @@ signal pll_int_lock, pll_ext_lock : std_logic;
 signal wait_for_lock : std_logic := '1';
 signal clock_select  : std_logic := '0';
 
-signal timer   : unsigned(15 downto 0) := (others => '0');
+signal timer   : unsigned(26 downto 0) := (others => '0');
 signal clear_n_i : std_logic := '0';
 signal reset_i   : std_logic;
 
@@ -169,10 +169,10 @@ gen_norecov_clock : if USE_RXCLOCK = c_NO generate
   
   process begin
     wait until rising_edge(INT_CLK_IN);
-    if timer(15) = '1' and timer(0) = '0' then  --after 135us
+    if timer(26-CLOCK_FAST_SELECT*11) = '1' and timer(0) = '0' then  --after 135us or 8.8ms
       timer <= timer + 1;
       clock_select <= pll_ext_lock; 
-    elsif timer(15) = '1' and timer(0) = '1' then  --after 135us plus 1
+    elsif timer(26-CLOCK_FAST_SELECT*11) = '1' and timer(0) = '1' then  --after 135us or 8.8ms plus 1
       timer <= timer;
     else  
       timer <= timer + 1;
@@ -183,7 +183,7 @@ gen_norecov_clock : if USE_RXCLOCK = c_NO generate
   
 end generate;
 
-clear_n_i <= timer(15) when rising_edge(INT_CLK_IN);
+clear_n_i <= timer(26-CLOCK_FAST_SELECT*11) when rising_edge(INT_CLK_IN);
 
 ---------------------------------------------------------------------------
 -- Reset generation

diff --git a/hubaddon/config.vhd b/hubaddon/config.vhd
index 41269f789a45ddd34ae9c9b87270c00557e35b12..13c11fe02e9d28d91d2a15abef40cdd935588ee9 100644 (file)
--- a/hubaddon/config.vhd
+++ b/hubaddon/config.vhd
@@ -14,6 +14,7 @@ package config is
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
     constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
+    constant CLOCK_FAST_SELECT        : integer := c_NO; --fast clock select (135us) or slow (280ms)?
     
 --Use sync mode, RX clock for all parts of the FPGA
     constant USE_RXCLOCK            : integer := c_NO;

diff --git a/padiwa/config.vhd b/padiwa/config.vhd
index 33017d286462467c3644951f653d49f694e6461a..2827b400cd7b25d4a2b2590f9e3a3054c4aee86d 100644 (file)
--- a/padiwa/config.vhd
+++ b/padiwa/config.vhd
@@ -28,6 +28,7 @@ package config is
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
     constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
+    constant CLOCK_FAST_SELECT        : integer := c_NO; --fast clock select (135us) or slow (280ms)?
     
 --Use sync mode, RX clock for all parts of the FPGA
     constant USE_RXCLOCK            : integer := c_NO;

diff --git a/pulser/config.vhd b/pulser/config.vhd
index a56d795b57d906763e3e37fd2f7417f1e7d47916..1fb8e03f5e943638e3cfc02eb8da1bba0c0d988a 100644 (file)
--- a/pulser/config.vhd
+++ b/pulser/config.vhd
@@ -13,6 +13,7 @@ package config is
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
     constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
+    constant CLOCK_FAST_SELECT        : integer := c_NO; --fast clock select (135us) or slow (280ms)?
     
 --Use sync mode, RX clock for all parts of the FPGA
     constant USE_RXCLOCK            : integer := c_NO;

diff --git a/tdctemplate/config.vhd b/tdctemplate/config.vhd
index add1abab921c5b9f2ae8874be211f0fe78fa1271..a91b01bb17cfe957ce60e604e670dc153868b114 100644 (file)
--- a/tdctemplate/config.vhd
+++ b/tdctemplate/config.vhd
@@ -28,6 +28,7 @@ package config is
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
     constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
+    constant CLOCK_FAST_SELECT        : integer := c_NO; --fast clock select (135us) or slow (280ms)?
     
 --Use sync mode, RX clock for all parts of the FPGA
     constant USE_RXCLOCK            : integer := c_NO;

diff --git a/template/config.vhd b/template/config.vhd
index 83021146f3789be71308b0a716b6c57bc91266b4..baa4db7302f4f3323947ed269bc2ecb8b07421d2 100644 (file)
--- a/template/config.vhd
+++ b/template/config.vhd
@@ -13,6 +13,7 @@ package config is
 --Runs with 120 MHz instead of 100 MHz     
     constant USE_120_MHZ            : integer := c_NO; 
     constant USE_EXTERNAL_CLOCK     : integer := c_YES; --'no' not implemented.
+    constant CLOCK_FAST_SELECT        : integer := c_NO; --fast clock select (135us) or slow (280ms)?
     
 --Use sync mode, RX clock for all parts of the FPGA
     constant USE_RXCLOCK            : integer := c_NO;

diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl
index d3aaf19eb05e20d5b0ffc77fe3e107d829a52635..f3d687dc4242d7188d76bbf3eec9406515a687b4 100644 (file)
--- a/template/config_compile_frankfurt.pl
+++ b/template/config_compile_frankfurt.pl
@@ -2,10 +2,10 @@ TOPNAME                      => "trb3sc_basic",
 lm_license_file_for_synplify => "1702\@hadeb05.gsi.de", #"27000\@lxcad01.gsi.de";
 lm_license_file_for_par      => "1702\@hadeb05.gsi.de",
 lattice_path                 => '/d/jspc29/lattice/diamond/3.6_x64',
-synplify_path                => '/d/jspc29/lattice/synplify/J-2014.09-SP2/',
+synplify_path                => '/d/jspc29/lattice/synplify/K-2015.09/',
 synplify_command             => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
-#synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
-
+# synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
+# synplify_command             => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #",
 nodelist_file                => 'nodelist_frankfurt.txt',