ADA AddOn project is brought up-to-date with tdc 2.1.2 and SPI interface for PADI...

diff --git a/ADA_Addon/compile_constraints.pl b/ADA_Addon/compile_constraints.pl
index 44a9c031dc5b51a59f262a0bd3d1d8ee3cbfe5b0..17202159b35a8caed45d3e9eddb52712aad389f4 100755 (executable)
--- a/ADA_Addon/compile_constraints.pl
+++ b/ADA_Addon/compile_constraints.pl
@@ -7,9 +7,9 @@ my $TOPNAME                      = "trb3_periph_ADA";  #Name of top-level entity
 
 
 #create full lpf file
-system("cp ../base/trb3_periph_ADA.lpf diamond/$TOPNAME.lpf");
-system("cat currentRelease/trbnet_constraints.lpf >> diamond/$TOPNAME.lpf");
-system("cat currentRelease/tdc_constraints_64.lpf >> diamond/$TOPNAME.lpf");
-system("cat currentRelease/unimportant_lines_constraints.lpf >> diamond/$TOPNAME.lpf");
-system("cat unimportant_lines_constraints.lpf >> diamond/$TOPNAME.lpf");
+system("cp ../base/trb3_periph_ADA.lpf workdir/diamond/$TOPNAME.lpf");
+system("cat tdc_release/trbnet_constraints.lpf >> workdir/diamond/$TOPNAME.lpf");
+system("cat tdc_release/tdc_constraints_64.lpf >> workdir/diamond/$TOPNAME.lpf");
+system("cat tdc_release/unimportant_lines_constraints.lpf >> workdir/diamond/$TOPNAME.lpf");
+system("cat unimportant_lines_constraints.lpf >> workdir/diamond/$TOPNAME.lpf");
 

diff --git a/ADA_Addon/config.vhd b/ADA_Addon/config.vhd
index 34f27208dca9aa376953eb96099bb979daea1889..5913c3ee0fd881cdc612fafb21e064e68590fe5e 100644 (file)
--- a/ADA_Addon/config.vhd
+++ b/ADA_Addon/config.vhd
@@ -25,11 +25,12 @@ package config is
   constant EVENT_MAX_SIZE          : integer := 4096;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
 
 --Include SPI on AddOn connector
-  constant INCLUDE_SPI : integer := c_YES;
+  constant INCLUDE_SPI  : integer := c_YES;
+  constant SPI_FOR_PADI : integer := c_YES;
 
 --Add logic to generate configurable trigger signal from input signals.
-  constant INCLUDE_TRIGGER_LOGIC : integer := c_YES;
-  constant INCLUDE_STATISTICS    : integer := c_YES;  --Do histos of all inputs
+  constant INCLUDE_TRIGGER_LOGIC : integer := c_NO;
+  constant INCLUDE_STATISTICS    : integer := c_NO;  --Do histos of all inputs
   constant PHYSICAL_INPUTS       : integer := 32;  --number of inputs connected
   constant USE_SINGLE_FIFO       : integer := c_YES;  -- single fifo for statistics
   

diff --git a/ADA_Addon/currentRelease b/ADA_Addon/currentRelease
deleted file mode 120000 (symlink)
index 02a0ff9..0000000
--- a/ADA_Addon/currentRelease
+++ /dev/null
@@ -1 +0,0 @@
-../tdc_releases/tdc_v2.1.1
\ No newline at end of file

diff --git a/ADA_Addon/trb3_periph_ADA.prj b/ADA_Addon/trb3_periph_ADA.prj
index 18831c2dd51918b348f55a8bcc4d7b819bb67930..9013bebd98398a203df40d5b17e3448a7712a052 100644 (file)
--- a/ADA_Addon/trb3_periph_ADA.prj
+++ b/ADA_Addon/trb3_periph_ADA.prj
@@ -1,5 +1,4 @@
 
-
 # implementation: "workdir"
 impl -add workdir -type fpga
 
@@ -19,16 +18,16 @@ set_option -resource_sharing true
 # map options
 set_option -frequency 200
 set_option -fanout_limit 100
+
+# Lattice XP
 set_option -disable_io_insertion 0
 set_option -retiming 0
 set_option -pipe 0
-#set_option -force_gsr 
 set_option -force_gsr false
 set_option -fixgatedclocks 3
 set_option -fixgeneratedclocks 3
 set_option -compiler_compatible true
 
-
 # simulation options
 set_option -write_verilog 0
 set_option -write_vhdl 1
@@ -41,36 +40,27 @@ project -result_format "edif"
 project -result_file "workdir/trb3_periph_ADA.edf"
 
 #implementation attributes
-
 set_option -vlog_std v2001
 set_option -project_relative_includes 1
+
+# design plan options
 impl -active "workdir"
 
 ####################
 
 
-
-#add_file options
-
+#project files
 add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "currectRelease/tdc_version.vhd"
+add_file -vhdl -lib work "tdc_release/tdc_version.vhd"
 add_file -vhdl -lib work "config.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib "work" "../base/trb3_components.vhd"
-
+add_file -vhdl -lib work "../base/trb3_components.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
@@ -93,24 +83,34 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
-
 add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
 add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
 add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
 add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
 add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
-
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" 
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
@@ -123,47 +123,46 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
-
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
-
-add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
-
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
 add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
-
-add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
-
-###############
-#Change path to tdc release also in compile script!
-###############
-#add_file -vhdl -lib "work" "currentRelease/Adder_304.vhd"
-add_file -vhdl -lib "work" "currentRelease/bit_sync.vhd"
-add_file -vhdl -lib "work" "currentRelease/BusHandler.vhd"
-add_file -vhdl -lib "work" "currentRelease/Channel.vhd"
-add_file -vhdl -lib "work" "currentRelease/Channel_200.vhd"
-add_file -vhdl -lib "work" "currentRelease/Encoder_304_Bit.vhd"
-add_file -vhdl -lib "work" "currentRelease/LogicAnalyser.vhd"
-add_file -vhdl -lib "work" "currentRelease/Readout.vhd"
-add_file -vhdl -lib "work" "currentRelease/ROM4_Encoder.vhd"
-add_file -vhdl -lib "work" "currentRelease/ROM_encoder_3.vhd"
-add_file -vhdl -lib "work" "currentRelease/ShiftRegisterSISO.vhd"
-add_file -vhdl -lib "work" "currentRelease/TDC.vhd"
-add_file -vhdl -lib "work" "currentRelease/TriggerHandler.vhd"
-add_file -vhdl -lib "work" "currentRelease/up_counter.vhd"
-add_file -vhdl -lib "work" "currentRelease/fallingEdgeDetect.vhd"
-add_file -vhdl -lib "work" "currentRelease/risingEdgeDetect.vhd"
-add_file -vhdl -lib "work" "currentRelease/hit_inv.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_36x128_OutReg.vhd"
-add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd"
-add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd"
-
-add_file -vhdl -lib "work" "trb3_periph_ADA.vhd"
+add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd"
+add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib work "../base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../base/code/sedcheck.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out100.vhd"
+add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
+add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
+add_file -vhdl -lib work "tdc_release/BusHandler.vhd"
+add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
+add_file -vhdl -lib work "tdc_release/Channel.vhd"
+add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
+add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
+add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
+add_file -vhdl -lib work "tdc_release/Readout.vhd"
+add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
+add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
+add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
+add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
+add_file -vhdl -lib work "tdc_release/TDC.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+add_file -vhdl -lib work "tdc_release/up_counter.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
+add_file -vhdl -lib work "trb3_periph_ADA.vhd"
+add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in20_out100.vhd"

diff --git a/ADA_Addon/trb3_periph_ADA.vhd b/ADA_Addon/trb3_periph_ADA.vhd
index 6c96b55dcfd2e402efc082df7478bf8e05854d4e..73d238273895fa1d1bd828a50ebc92fa5fa6d32c 120000 (symlink)
--- a/ADA_Addon/trb3_periph_ADA.vhd
+++ b/ADA_Addon/trb3_periph_ADA.vhd
@@ -1 +1 @@
-currentRelease/trb3_periph_ADA.vhd
\ No newline at end of file
+tdc_release/trb3_periph_ADA.vhd
\ No newline at end of file

diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd
index c61ab58994e847748df4ba91d8ce47c68db0eefd..5af6f3c73cea9492549be0a1a3ecfee894f7aab2 100644 (file)
--- a/base/trb3_components.vhd
+++ b/base/trb3_components.vhd
@@ -45,33 +45,6 @@ package trb3_components is
       LOCK  : out std_logic);
   end component pll_in200_out100;
 
-  component pll_in20_out100 is
-    port (
-      CLK   : in  std_logic;            -- 20 MHz
-      CLKOP : out std_logic;            -- 100 MHz
-      CLKOS : out std_logic;            -- 20 MHz, bypass
-      LOCK  : out std_logic);
-  end component pll_in20_out100;
-  
-  component pll_calibration is
-    port (
-      CLK   : in  std_logic;            -- clk_in 100MHz       
-      CLKOP : out std_logic;            -- 12,5MHz %50 Duty cyc
-      LOCK  : out std_logic);
-  end component pll_calibration;
-
-  component OSCF  -- internal oscillator with a frequency of 2MHz
--- synthesis translate_off
-    generic (NOM_FREQ :     string := "20.0");
--- synthesis translate_on
-    port (OSC         : out std_logic);
-  end component;
-
-  --component OSCF
-  --  port (OSC : out
-  --        std_logic);
-  --end component;
-
   component adc_ad9222
     generic(
       CHANNELS   : integer range 4 to 4   := 4;

diff --git a/base/trb3_periph_ADA.lpf b/base/trb3_periph_ADA.lpf
index 746468fb4fc124ca5df2c4babf24c42e26db1b3b..494cb7bee1a897fa914a341d465527cebd350ba2 100644 (file)
--- a/base/trb3_periph_ADA.lpf
+++ b/base/trb3_periph_ADA.lpf
@@ -166,18 +166,22 @@ IOBUF GROUP "INP_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
 #LOCATE COMP  "SPARE_LINE_2"    SITE "W4";  #198
 #LOCATE COMP  "SPARE_LINE_3"    SITE "W5";  #200
 
-LOCATE COMP  "DAC_SDI"    SITE "D4";     #"DQUL_2"    DQUL0_2   #78
-LOCATE COMP  "DAC_SCK"    SITE "C3";     #"DQUL_4"    DQUL0_4   #82
-LOCATE COMP  "DAC_CS_1"   SITE "H6";     #"DQUL_10"   DQUL0_8   #94
-LOCATE COMP  "DAC_CS_2"   SITE "AA24";   #"DQUL_10"   DQUL0_8   #94
-LOCATE COMP  "DAC_CS_3"   SITE "U24";    #"DQUL_10"   DQUL0_8   #94
-LOCATE COMP  "DAC_CS_4"   SITE "U23";    #"DQUL_10"   DQUL0_8   #94
-LOCATE COMP  "DAC_SDO"     SITE "G5";     #"DQUL_6"    DQSUL0_T  #86
-
-DEFINE PORT GROUP "DAC_group" "DAC_*" ;
-IOBUF GROUP "DAC_group" IO_TYPE=LVDS25;
-
-#IOBUF PORT "DAC_SDO" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+LOCATE COMP  "DAC_OUT_SDO"    SITE "D4";     #"DQUL_2"    DQUL0_2   #78
+LOCATE COMP  "DAC_OUT_SCK"    SITE "C3";     #"DQUL_4"    DQUL0_4   #82
+LOCATE COMP  "DAC_OUT_CS_1"   SITE "H6";     #"DQUL_10"   DQUL0_8   #94
+LOCATE COMP  "DAC_OUT_CS_2"   SITE "AA24";   #"DQUL_10"   DQUL0_8   #94
+LOCATE COMP  "DAC_OUT_CS_3"   SITE "U24";    #"DQUL_10"   DQUL0_8   #94
+LOCATE COMP  "DAC_OUT_CS_4"   SITE "U23";    #"DQUL_10"   DQUL0_8   #94
+LOCATE COMP  "DAC_IN_SDI"     SITE "G5";     #"DQUL_6"    DQSUL0_T  #86
+LOCATE COMP  "DAC_OUT_CLR"    SITE "U24";    #"DQLR2_6"
+
+DEFINE PORT GROUP "DAC_IN_group" "DAC_IN_*" ;
+IOBUF GROUP "DAC_IN_group" IO_TYPE=LVDS25 DIFFRESISTOR=100;
+
+DEFINE PORT GROUP "DAC_OUT_group" "DAC_OUT_*" ;
+IOBUF GROUP "DAC_OUT_group" IO_TYPE=LVDS25;
+
+IOBUF PORT "DAC_OUT_SDO" IO_TYPE=LVDS25E ;
 
 #################################################################
 # DAC SPI & Flash ROM & Reboot