]> jspc29.x-matter.uni-frankfurt.de Git - trb3.git/commitdiff
CBM: Wrong status bits for event packer; CTS: clean up
authorManuel Penschuck <manuel.penschuck@stud.uni-frankfurt.de>
Sun, 28 Sep 2014 18:37:39 +0000 (20:37 +0200)
committerManuel Penschuck <manuel.penschuck@stud.uni-frankfurt.de>
Sun, 28 Sep 2014 18:37:39 +0000 (20:37 +0200)
base/trb3_central_cts.lpf
cbmnet/code/cbmnet_interface_pkg.vhd
cbmnet/code/cbmnet_readout.vhd
cbmnet/code/cbmnet_readout_event_packer.vhd
cts/cts.fdc [deleted file]
cts/old/compile2_frankfurt.pl [deleted file]
cts/old/constraints_cts_fpga2.lpf [deleted file]
cts/old/cts_fpga2.p2t [deleted file]
cts/old/cts_fpga2.prj [deleted file]
cts/old/cts_fpga2.vhd [deleted file]
cts/project2/cts.ldf [deleted file]

index d19b6c61960d7129c04c67b50a0c70b2b8a8e39e..f91381f4204987f79a0bd6dfa34165a2599b2a54 100644 (file)
@@ -338,7 +338,7 @@ IOBUF GROUP "JINLVDS_group" IO_TYPE=LVTTL33 PULLMODE=DOWN;
 LOCATE COMP  "DISCRIMINATOR_IN_0"   SITE "T32";
 LOCATE COMP  "DISCRIMINATOR_IN_1"   SITE "T30";
 DEFINE PORT GROUP "DISCRIMINATOR_group" "DISCRIMINATOR*" ;
-IOBUF GROUP  "DISCRIMINATOR_group" IO_TYPE=LVDS25 DIFFRESISTOR=NONE;
+IOBUF GROUP  "DISCRIMINATOR_group" IO_TYPE=LVDS25 DIFFRESISTOR=OFF;
 
 LOCATE COMP  "JOUT1_0"   SITE "B4";
 LOCATE COMP  "JOUT1_1"   SITE "B3";
index 84103e6a01455c579bf675f5b2807c6ee8ff4694..ff3f0f289d80b8179c5de9f248859c1d39dcbc6f 100644 (file)
@@ -400,7 +400,7 @@ package cbmnet_interface_pkg is
       HUB_CTS_CODE_IN                : in  std_logic_vector (7  downto 0);
       HUB_CTS_INFORMATION_IN         : in  std_logic_vector (7  downto 0);
       HUB_CTS_READOUT_TYPE_IN        : in  std_logic_vector (3  downto 0);
-      GBE_CTS_STATUS_BITS_IN         : in  std_logic_vector (31 downto 0);
+      HUB_FEE_STATUS_BITS_IN         : in  std_logic_vector (31 downto 0);
       
       
       -- connect to decoder
index 4baae75a311e39d546ae1f1ce15d80b7f3b6c1ec..7639cc7a76f9c11fe3764f492133222e3bcd4165 100644 (file)
@@ -202,7 +202,7 @@ begin
       HUB_CTS_CODE_IN                => HUB_CTS_CODE_IN,         -- in  std_logic_vector (7  downto 0);
       HUB_CTS_INFORMATION_IN         => HUB_CTS_INFORMATION_IN,  -- in  std_logic_vector (7  downto 0);
       HUB_CTS_READOUT_TYPE_IN        => HUB_CTS_READOUT_TYPE_IN, -- in  std_logic_vector (3  downto 0);
-      GBE_CTS_STATUS_BITS_IN         => GBE_CTS_STATUS_BITS_IN,  -- in  std_logic_vector (31 downto 0);
+      HUB_FEE_STATUS_BITS_IN         => HUB_FEE_STATUS_BITS_IN,  -- in  std_logic_vector (31 downto 0);
       
       -- connect to decoder
       DEC_EVT_INFO_IN                => dec_evt_info_i,    -- in  std_logic_vector(31 downto 0);
index 21bbc56b9cc546a866a37af89c1bab053a775c6c..1fc4580ba8eed22c3586a8f440f33599afbec64d 100644 (file)
@@ -13,7 +13,7 @@ entity CBMNET_READOUT_EVENT_PACKER is
       HUB_CTS_CODE_IN                : in  std_logic_vector (7  downto 0);
       HUB_CTS_INFORMATION_IN         : in  std_logic_vector (7  downto 0);
       HUB_CTS_READOUT_TYPE_IN        : in  std_logic_vector (3  downto 0);
-      GBE_CTS_STATUS_BITS_IN         : in  std_logic_vector (31 downto 0);
+      HUB_FEE_STATUS_BITS_IN         : in  std_logic_vector (31 downto 0);
       
       
       -- connect to decoder
@@ -177,12 +177,12 @@ begin
                fsm_i <= TRL_STATUS_H;            
 
             when TRL_STATUS_H =>
-               header_data_i <= GBE_CTS_STATUS_BITS_IN(31 downto 16);
+               header_data_i <= HUB_FEE_STATUS_BITS_IN(31 downto 16);
                header_enqueue_i <= '1';
                fsm_i <= TRL_STATUS_L;
             when TRL_STATUS_L =>
                header_token_i <= "11";
-               header_data_i <= GBE_CTS_STATUS_BITS_IN(15 downto  0);
+               header_data_i <= HUB_FEE_STATUS_BITS_IN(15 downto  0);
                header_enqueue_i <= '1';
                wpacket_complete_i <= '1';
                fsm_i <= IDLE;                         
diff --git a/cts/cts.fdc b/cts/cts.fdc
deleted file mode 100644 (file)
index 3a276a1..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-
-###==== BEGIN Header
-
-# Synopsys, Inc. constraint file
-# /local/trb/cvs/trb3/cts/cts.fdc
-# Written on Mon Feb 25 14:14:25 2013
-# by Synplify Pro, G-2012.09-SP1  FDC Constraint Editor
-
-# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END.
-# These sections are generated from SCOPE spreadsheet tabs.
-
-###==== END Header
-
-###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit)
-###==== END Collections
-
-###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit)
-
-###==== END Clocks
-
-###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit)
-###==== END "Generated Clocks"
-
-###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit)
-###==== END Inputs/Outputs
-
-###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit)
-###==== END "Delay Paths"
-
-###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit)
-###==== END Attributes
-
-###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit)
-###==== END "I/O Standards"
-
-###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit)
-define_compile_point  {v:work.trb_net16_med_ecp3_sfp_work_trb3_central_trb3_central_arch_11layer0} -type {locked,partition}
-define_compile_point  {v:work.trb_net16_med_ecp3_sfp_4_onboard_work_trb3_central_trb3_central_arch_16layer0} -type {locked,partition}
-define_compile_point  {v:work.trb_net16_hub_streaming_port_sctrl_cts_work_trb3_central_trb3_central_arch_36layer0} -type {locked,partition}
-define_compile_point  {v:work.trb_net16_gbe_buf_0_0} -type {locked,partition}
-define_compile_point  {v:work.TDC_5_0_2} -type {locked,partition}
-define_compile_point  {v:work.CTS_work_trb3_central_trb3_central_arch_6layer0} -type {locked,partition}
-define_compile_point  {v:work.trb_net16_regIO_work_trb3_central_trb3_central_arch_29layer0} -type {locked,partition}
-###==== END "Compile Points"
-
-
diff --git a/cts/old/compile2_frankfurt.pl b/cts/old/compile2_frankfurt.pl
deleted file mode 100755 (executable)
index b794a17..0000000
+++ /dev/null
@@ -1,156 +0,0 @@
-#!/usr/bin/perl
-use Data::Dumper;
-use warnings;
-use strict;
-
-
-
-
-###################################################################################
-#Settings for this project
-my $TOPNAME                      = "cts_fpga2";  #Name of top-level entity
-my $lattice_path                 = '/d/jspc29/lattice/diamond/1.4';
-my $synplify_path                = '/d/jspc29/lattice/synplify/F-2012.03-SP1/';#fpga_e201103/';
-my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de";
-my $lm_license_file_for_par      = "1702\@hadeb05.gsi.de";
-###################################################################################
-
-
-
-
-
-
-
-
-use FileHandle;
-
-$ENV{'SYNPLIFY'}=$synplify_path;
-$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify;
-
-
-
-my $FAMILYNAME="LATTICEECP2M";
-my $DEVICENAME="LFE2M100E";
-my $PACKAGE="FPBGA900";
-my $SPEEDGRADE="5";
-
-
-
-#create full lpf file
-system("cp ../../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
-system("cat constraints_".$TOPNAME.".lpf >> workdir/$TOPNAME.lpf");
-
-
-#set -e
-#set -o errexit
-
-#generate timestamp
-my $t=time;
-my $fh = new FileHandle(">version.vhd");
-die "could not open file" if (! defined $fh);
-print $fh <<EOF;
-
---## attention, automatically generated. Don't change by hand.
-library ieee;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.std_logic_ARITH.ALL;
-USE IEEE.std_logic_UNSIGNED.ALL;
-use ieee.numeric_std.all;
-
-package version is
-
-    constant VERSION_NUMBER_TIME  : integer   := $t;
-
-end package version;
-EOF
-$fh->close;
-
-system("env| grep LM_");
-my $r = "";
-
-my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj";
-$r=execute($c, "do_not_exit" );
-
-
-chdir "workdir";
-$fh = new FileHandle("<$TOPNAME".".srr");
-my @a = <$fh>;
-$fh -> close;
-
-
-
-foreach (@a)
-{
-    if(/\@E:/)
-    {
-  print "\n";
-  $c="cat $TOPNAME.srr | grep \"\@E\"";
-  system($c);
-        print "\n\n";
-  exit 129;
-    }
-}
-
-
-$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par;
-
-
-$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate   -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild  -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
-execute($c);
-
-my $tpmap = $TOPNAME . "_map" ;
-
-$c=qq|$lattice_path/ispfpga/bin/lin/map  -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd"  -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
-execute($c);
-
-system("rm $TOPNAME.ncd");
-
-
-$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t"  "$tpmap.ncd" "$TOPNAME.ncd"|;
-execute($c);
-
-# IOR IO Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# TWR Timing Report
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold"  "$TOPNAME.ncd" "$TOPNAME.prf"|;
-execute($c);
-
-# $c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|;
-# execute($c);
-
-$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No  $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|;
-# $c=qq|$lattice_path/ispfpga/bin/lin/bitgen  -w "$TOPNAME.ncd"  "$TOPNAME.prf"|;
-execute($c);
-
-chdir "..";
-
-exit;
-
-sub execute {
-    my ($c, $op) = @_;
-    #print "option: $op \n";
-    $op = "" if(!$op);
-    print "\n\ncommand to execute: $c \n";
-    $r=system($c);
-    if($r) {
-  print "$!";
-  if($op ne "do_not_exit") {
-      exit;
-  }
-    }
-
-    return $r;
-
-}
diff --git a/cts/old/constraints_cts_fpga2.lpf b/cts/old/constraints_cts_fpga2.lpf
deleted file mode 100644 (file)
index 4e23e05..0000000
+++ /dev/null
@@ -1,78 +0,0 @@
-COMMERCIAL ;
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-
-#########################################
-# Clock Constraints
-#########################################
-  FREQUENCY PORT CLK_100_IN       100.000000 MHz  HOLD_MARGIN 0.100000 nS ;
-  FREQUENCY PORT CLK_125_IN       125.000000 MHz  HOLD_MARGIN 0.100000 nS ;
-
-
-
-#########################################
-# Serdes Placement
-#########################################
-REGION "MED0" "R9C100" 18 26 ;
-REGION "MED1" "R80C100" 25 26 ;
-
-LOCATE COMP   "THE_MEDIA_INTERFACE_0/gen_serdes_0_THE_SERDES/PCSC_INST" SITE "URPCS" ;
-LOCATE UGROUP "THE_MEDIA_INTERFACE_0/media_interface_group" REGION "MED0" ;
-
-LOCATE COMP   "THE_MEDIA_INTERFACE_1/gen_serdes_0_THE_SERDES/PCSC_INST" SITE "LRPCS" ;
-LOCATE UGROUP "THE_MEDIA_INTERFACE_1/media_interface_group" REGION "MED1" ;
-
-
-#########################################
-# Endpoint Placement
-#########################################
-REGION "ENDP_CTS_REGION" "R59C80" 52 48;
-REGION "ENDP_RDO_REGION" "R2C80" 56 48;
-
-#Readout endpoint
-
-LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/RegIO_group" REGION "ENDP_RDO_REGION";
-
-LOCATE UGROUP "THE_RDO_BUS_HANDLER/Bus_handler_group" REGION "ENDP_RDO_REGION";
-
-
-LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "ENDP_RDO_REGION";
-LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "ENDP_RDO_REGION";
-
-LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "ENDP_RDO_REGION";
-LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "ENDP_RDO_REGION";
-LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "ENDP_RDO_REGION";
-
-# LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "ENDP_RDO_REGION";
-# LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "ENDP_RDO_REGION";
-# LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3/OBUF_group" REGION "ENDP_RDO_REGION";
-
-LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "ENDP_RDO_REGION";
-LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "ENDP_RDO_REGION";
-LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "ENDP_RDO_REGION";
-
-#CTS endpoint
-LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "ENDP_CTS_REGION";
-LOCATE UGROUP "THE_CTS_ENDPOINT/regIO/RegIO_group" REGION "ENDP_CTS_REGION";
-
-LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_0_geniobuf_gen_api_act_DAT_ACTIVE_API/API_group" REGION "ENDP_CTS_REGION";
-LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_1_geniobuf_gen_api_act_DAT_ACTIVE_API/API_group" REGION "ENDP_CTS_REGION";
-LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_3_geniobuf_gen_api_pas_DAT_PASSIVE_API/API_group" REGION "ENDP_CTS_REGION";
-
-LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "ENDP_CTS_REGION";
-LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "ENDP_CTS_REGION";
-LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "ENDP_CTS_REGION";
-
-LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "ENDP_CTS_REGION";
-LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "ENDP_CTS_REGION";
-# LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3/OBUF_group" REGION "ENDP_CTS_REGION";
-
-# LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3/OBUF_group" REGION "ENDP_CTS_REGION";
-# LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3/OBUF_group" REGION "ENDP_CTS_REGION";
-LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "ENDP_CTS_REGION";
-
-
-
-
-
diff --git a/cts/old/cts_fpga2.p2t b/cts/old/cts_fpga2.p2t
deleted file mode 100644 (file)
index afbb9a1..0000000
+++ /dev/null
@@ -1,21 +0,0 @@
--w
--i 15
--l 5
--n 2
--y
--s 12
--t 1
--c 1
--e 2
--m ../base/nodelist_frankfurt.txt
-# -w
-# -i 6
-# -l 5
-# -n 1
-# -t 1
-# -s 1
-# -c 0
-# -e 0
-#
--exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:
-
diff --git a/cts/old/cts_fpga2.prj b/cts/old/cts_fpga2.prj
deleted file mode 100644 (file)
index b57896d..0000000
+++ /dev/null
@@ -1,137 +0,0 @@
-#-- Synplicity, Inc.
-#-- Version 9.0
-#-- Project file ../ctsaddon/cts_fpga1.prj
-
-
-
-#add_file options
-add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_onewire_listener.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
-
-add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_cts.vhd"
-
-
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/pll_in100_out100.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/trb_net_clock_generator.vhd"
-
-add_file -vhdl -lib work "cts_fpga2.vhd"
-
-
-
-
-#implementation: "workdir"
-impl -add workdir -type fpga
-
-#device options
-set_option -technology LATTICE-ECP2M
-set_option -part LFE2M100E
-set_option -package F900C
-set_option -speed_grade -5
-
-#compilation/mapping options
-set_option -default_enum_encoding sequential
-set_option -symbolic_fsm_compiler 1
-#set_option -resource_sharing 0
-set_option -top_module "cts_fpga2"
-
-#map options
-set_option -frequency auto
-set_option -fanout_limit 100
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
-set_option -force_gsr auto
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
-
-
-
-#simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 0
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 0
-
-#set result format/file last
-project -result_format "edif"
-project -result_file "workdir/cts_fpga2.edf"
-
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -project_relative_includes 1
-impl -active "workdir"
diff --git a/cts/old/cts_fpga2.vhd b/cts/old/cts_fpga2.vhd
deleted file mode 100644 (file)
index 63db7a0..0000000
+++ /dev/null
@@ -1,728 +0,0 @@
-LIBRARY ieee;
-use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
--- use work.trb_net16_hub_func.all;
-use work.version.all;
-
-entity cts_fpga2 is
-  port(
-    --Clocks
-    CLK_100_IN          : in  std_logic;
-    CLK_125_IN          : in  std_logic;
-    --Resets
-    RESET_FPGA_2        : in  std_logic;
-    ADDON_RESET         : in  std_logic;
-    --To Other FPGAs
-    ADO_LV              : inout std_logic_vector(61 downto 0);
-    FFC                 : inout std_logic_vector(22 downto 0);
-    --LED
-    LED_GBE_OK          : out std_logic;
-    LED_GBE_RX          : out std_logic;
-    LED_GBE_TX          : out std_logic;
-    LED_TRB_OK          : out std_logic;
-    LED_TRB_RX          : out std_logic;
-    LED_TRB_TX          : out std_logic;
-    LED_RED             : out std_logic;
-    LED_YELLOW          : out std_logic;
-    LED_GREEN           : out std_logic;
-    LED_ORANGE          : out std_logic;
-    --SFP
-    SFP_DATA_TX         : out   std_logic_vector(3 downto 0); --dummy serdes connection
-    SFP_DATA_RX         : in    std_logic_vector(3 downto 0); --dummy serdes connection
-    GBE_LOS             : in    std_logic;
-    GBE_MOD             : inout std_logic_vector(2 downto 0);
-    GBE_TX_DIS          : out   std_logic;
-    TRB_LOS             : in    std_logic;
-    TRB_MOD             : inout std_logic_vector(2 downto 0);
-    TRB_TX_DIS          : out   std_logic;
-    --Flash
-    SPI_CLK_OUT         : out std_logic;
-    SPI_CS_OUT          : out std_logic;
-    SPI_SI_OUT          : out std_logic;
-    SPI_SO_IN           : in  std_logic;
-    PROGRAMN_OUT        : out std_logic;
-    --RAM
-    RAM_ADSCB           : out std_logic;
-    RAM_ADSPB           : out std_logic;
-    RAM_ADVB            : out std_logic;
-    RAM_CE_2            : out std_logic;
-    RAM_CEB             : out std_logic;
-    RAM_CLK             : out std_logic;
-    RAM_GWB             : out std_logic;
-    RAM_OEB             : out std_logic;
-    RAM_A               : out std_logic_vector(19 downto 0);
-    RAM_DQ              : inout std_logic_vector(18 downto 1);
-    --Others
-    ONEWIRE_MONITOR_OUT : out std_logic;
-    TEMPSENS            : inout std_logic;
-    --Debug
-    TEST_LINE           : out std_logic_vector(15 downto 0)
-    );
-
-  attribute syn_useioff : boolean;
-  attribute syn_useioff of FFC                  : signal is true;
-  attribute syn_useioff of SPI_CLK_OUT          : signal is true;
-  attribute syn_useioff of SPI_CS_OUT           : signal is true;
-  attribute syn_useioff of SPI_SO_IN            : signal is true;
-  attribute syn_useioff of SPI_SI_OUT           : signal is true;
-  attribute syn_useioff of ADO_LV               : signal is true;
-  attribute syn_useioff of RAM_A                : signal is true;
-  attribute syn_useioff of RAM_DQ               : signal is true;
-  attribute syn_useioff of RAM_ADSCB            : signal is true;
-  attribute syn_useioff of RAM_ADSPB            : signal is true;
-  attribute syn_useioff of RAM_ADVB             : signal is true;
-  attribute syn_useioff of RAM_CE_2             : signal is true;
-  attribute syn_useioff of RAM_CEB              : signal is true;
-  attribute syn_useioff of RAM_CLK              : signal is true;
-  attribute syn_useioff of RAM_GWB              : signal is true;
-  attribute syn_useioff of RAM_OEB              : signal is true;
-
-  attribute syn_useioff of PROGRAMN_OUT         : signal is false;
-  attribute syn_useioff of LED_GBE_OK           : signal is false;
-  attribute syn_useioff of LED_GBE_RX           : signal is false;
-  attribute syn_useioff of LED_GBE_TX           : signal is false;
-  attribute syn_useioff of LED_TRB_OK           : signal is false;
-  attribute syn_useioff of LED_TRB_RX           : signal is false;
-  attribute syn_useioff of LED_TRB_TX           : signal is false;
-  attribute syn_useioff of LED_RED              : signal is false;
-  attribute syn_useioff of LED_YELLOW           : signal is false;
-  attribute syn_useioff of LED_GREEN            : signal is false;
-  attribute syn_useioff of LED_ORANGE           : signal is false;
-  attribute syn_useioff of TRB_LOS              : signal is false;
-  attribute syn_useioff of TRB_MOD              : signal is false;
-  attribute syn_useioff of TRB_TX_DIS           : signal is false;
-  attribute syn_useioff of GBE_LOS              : signal is false;
-  attribute syn_useioff of GBE_MOD              : signal is false;
-  attribute syn_useioff of GBE_TX_DIS           : signal is false;
-  attribute syn_useioff of ONEWIRE_MONITOR_OUT  : signal is false;
-  attribute syn_useioff of TEMPSENS             : signal is false;
-
-
-end entity;
-
-
-architecture cts_fpga2_arch of cts_fpga2 is
-
---Number of stat & ctrl registers on both endpoints. Number of Regs is 2**value
-  constant RDO_NUM_STAT_REGS     : integer := 2;
-  constant RDO_NUM_CTRL_REGS     : integer := 2;
-  constant CTS_NUM_STAT_REGS     : integer := 2;
-  constant CTS_NUM_CTRL_REGS     : integer := 2;
-
---Clock & Reset
-  signal clk_en                  : std_logic;
-  signal make_reset_via_network  : std_logic;
-  signal clk_100                 : std_logic;
-  signal pll_locked              : std_logic;
-  signal reset_async             : std_logic;
-  signal reset_i                 : std_logic;
-  signal delayed_restart_fpga    : std_logic;
-  signal restart_fpga_counter    : unsigned(11 downto 0);
-
---Media Interfaces
-  signal rdo_med_data_in         : std_logic_vector (16-1 downto 0);
-  signal rdo_med_packet_num_in   : std_logic_vector (3-1  downto 0);
-  signal rdo_med_dataready_in    : std_logic;
-  signal rdo_med_read_in         : std_logic;
-  signal rdo_med_data_out        : std_logic_vector (16-1 downto 0);
-  signal rdo_med_packet_num_out  : std_logic_vector (3-1  downto 0);
-  signal rdo_med_dataready_out   : std_logic;
-  signal rdo_med_read_out        : std_logic;
-  signal rdo_med_stat_op         : std_logic_vector (16-1 downto 0);
-  signal rdo_med_ctrl_op         : std_logic_vector (16-1 downto 0);
-  signal rdo_med_stat_debug      : std_logic_vector (64-1 downto 0);
-  signal cts_med_data_in         : std_logic_vector (16-1 downto 0);
-  signal cts_med_packet_num_in   : std_logic_vector (3-1  downto 0);
-  signal cts_med_dataready_in    : std_logic;
-  signal cts_med_read_in         : std_logic;
-  signal cts_med_data_out        : std_logic_vector (16-1 downto 0);
-  signal cts_med_packet_num_out  : std_logic_vector (3-1  downto 0);
-  signal cts_med_dataready_out   : std_logic;
-  signal cts_med_read_out        : std_logic;
-  signal cts_med_stat_op         : std_logic_vector (16-1 downto 0);
-  signal cts_med_ctrl_op         : std_logic_vector (16-1 downto 0);
-  signal cts_med_stat_debug      : std_logic_vector (64-1 downto 0);
-
---Trigger Port for Readout requests
-  signal rdo_trg_feedback_i      : std_logic;
-  signal rdo_trg_data_valid      : std_logic;
-  signal rdo_trg_valid_timing    : std_logic;
-  signal rdo_trg_valid_notiming  : std_logic;
-  signal rdo_trg_invalid         : std_logic;
-  signal rdo_trg_type            : std_logic_vector (3  downto 0);
-  signal rdo_trg_number          : std_logic_vector (15 downto 0);
-  signal rdo_trg_code            : std_logic_vector (7  downto 0);
-  signal rdo_trg_information     : std_logic_vector (23 downto 0);
-  signal rdo_trg_int_trg_number  : std_logic_vector (15 downto 0);
-  signal rdo_fee_trg_release     : std_logic;
-  signal rdo_fee_trg_statusbits  : std_logic_vector (31 downto 0);
-
---Data Port for Readout
-  signal rdo_fee_data            : std_logic_vector (31 downto 0);
-  signal rdo_fee_data_write      : std_logic;
-  signal rdo_fee_data_finished   : std_logic;
-  signal rdo_fee_data_almost_full: std_logic;
-
---RegIO Registers on Readout endpoint
-  signal rdo_regio_common_stat_reg_i       : std_logic_vector(std_COMSTATREG*32-1 downto 0);
-  signal rdo_regio_common_ctrl_reg_i       : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-  signal rdo_regio_common_stat_strobe_i    : std_logic_vector(std_COMSTATREG-1 downto 0);
-  signal rdo_regio_common_ctrl_strobe_i    : std_logic_vector(std_COMCTRLREG-1 downto 0);
-  signal rdo_regio_stat_reg_i              : std_logic_vector(2**(RDO_NUM_STAT_REGS)*32-1 downto 0);
-  signal rdo_regio_ctrl_reg_i              : std_logic_vector(2**(RDO_NUM_CTRL_REGS)*32-1 downto 0);
-  signal rdo_regio_stat_strobe_i           : std_logic_vector(2**(RDO_NUM_STAT_REGS)-1 downto 0);
-  signal rdo_regio_ctrl_strobe_i           : std_logic_vector(2**(RDO_NUM_CTRL_REGS)-1 downto 0);
-
---Regio Data Bus on Readout endpoint
-  signal rdo_regio_addr_out                : std_logic_vector(15 downto 0);
-  signal rdo_regio_read_enable_out         : std_logic;
-  signal rdo_regio_write_enable_out        : std_logic;
-  signal rdo_regio_data_out                : std_logic_vector(31 downto 0);
-  signal rdo_regio_data_in                 : std_logic_vector(31 downto 0);
-  signal rdo_regio_dataready_in            : std_logic;
-  signal rdo_regio_no_more_data_in         : std_logic;
-  signal rdo_regio_write_ack_in            : std_logic;
-  signal rdo_regio_unknown_addr_in         : std_logic;
-  signal rdo_regio_timeout_out             : std_logic;
-  signal cts_regio_onewire_monitor_i       : std_logic;
-
---Time signals from Readout endpoint
-  signal rdo_global_time         : std_logic_vector(31 downto 0);
-  signal rdo_local_time          : std_logic_vector(7  downto 0);
-  signal rdo_time_since_last_trg : std_logic_vector(31 downto 0);
-  signal rdo_timer_ticks         : std_logic_vector(1  downto 0);
-
-  signal cts_trg_send_i          : std_logic;
-  signal cts_trg_type_i          : std_logic_vector(3  downto 0);
-  signal cts_trg_number_i        : std_logic_vector(15 downto 0);
-  signal cts_trg_information_i   : std_logic_vector(23 downto 0);
-  signal cts_trg_rnd_code_i      : std_logic_vector(7  downto 0);
-  signal cts_trg_statusbits_i    : std_logic_vector(31 downto 0);
-  signal cts_trg_busy_i          : std_logic;
-
-  signal cts_ipu_send_i          : std_logic;
-  signal cts_ipu_type_i          : std_logic_vector(3  downto 0);
-  signal cts_ipu_number_i        : std_logic_vector(15 downto 0);
-  signal cts_ipu_information_i   : std_logic_vector(7  downto 0);
-  signal cts_ipu_rnd_code_i      : std_logic_vector(7  downto 0);
-
-  signal cts_ipu_data_i          : std_logic_vector(31 downto 0);
-  signal cts_ipu_dataready_i     : std_logic;
-  signal cts_ipu_read_i          : std_logic;
-  signal cts_ipu_statusbits_i    : std_logic_vector(31 downto 0);
-  signal cts_ipu_busy_i          : std_logic;
-
---Regio Data Bus on CTS endpoint
-  signal cts_common_stat_reg_i             : std_logic_vector(std_COMSTATREG*32-1 downto 0);
-  signal cts_common_ctrl_reg_i             : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
-  signal cts_common_stat_strobe_i          : std_logic_vector(std_COMSTATREG-1 downto 0);
-  signal cts_common_ctrl_strobe_i          : std_logic_vector(std_COMCTRLREG-1 downto 0);
-  signal cts_stat_reg_i                    : std_logic_vector(2**(RDO_NUM_STAT_REGS)*32-1 downto 0);
-  signal cts_ctrl_reg_i                    : std_logic_vector(2**(RDO_NUM_CTRL_REGS)*32-1 downto 0);
-  signal cts_stat_strobe_i                 : std_logic_vector(2**(RDO_NUM_STAT_REGS)-1 downto 0);
-  signal cts_ctrl_strobe_i                 : std_logic_vector(2**(RDO_NUM_CTRL_REGS)-1 downto 0);
-  signal cts_regio_addr_i                  : std_logic_vector(15 downto 0);
-  signal cts_regio_read_i                  : std_logic;
-  signal cts_regio_write_i                 : std_logic;
-  signal cts_regio_data_out_i              : std_logic_vector(31 downto 0);
-  signal cts_regio_data_in_i               : std_logic_vector(31 downto 0);
-  signal cts_regio_dataready_i             : std_logic;
-  signal cts_regio_no_more_data_i          : std_logic;
-  signal cts_regio_write_ack_i             : std_logic;
-  signal cts_regio_unknown_addr_i          : std_logic;
-  signal cts_regio_timeout_i               : std_logic;
-
---Time signals from CTS endpoint
-  signal cts_global_time_i       : std_logic_vector(31 downto 0);
-  signal cts_local_time_i        : std_logic_vector(7  downto 0);
-  signal cts_timer_ticks_i       : std_logic_vector(1  downto 0);
-
---SPI for flash programming
-  signal spictrl_read_en         : std_logic;
-  signal spictrl_write_en        : std_logic;
-  signal spictrl_data_in         : std_logic_vector (31 downto 0);
-  signal spictrl_addr            : std_logic;
-  signal spictrl_data_out        : std_logic_vector (31 downto 0);
-  signal spictrl_ack             : std_logic;
-  signal spictrl_busy            : std_logic;
-  signal spimem_read_en          : std_logic;
-  signal spimem_write_en         : std_logic;
-  signal spimem_data_in          : std_logic_vector (31 downto 0);
-  signal spimem_addr             : std_logic_vector (5 downto 0);
-  signal spimem_data_out         : std_logic_vector (31 downto 0);
-  signal spimem_ack              : std_logic;
-  signal spi_bram_addr           : std_logic_vector (7 downto 0);
-  signal spi_bram_wr_d           : std_logic_vector (7 downto 0);
-  signal spi_bram_rd_d           : std_logic_vector (7 downto 0);
-  signal spi_bram_we             : std_logic;
-
-
-
-begin
-
----------------------------------------------------------------------------
--- Clock & Reset state machine
----------------------------------------------------------------------------
-  clk_en                 <= '1';
-  make_reset_via_network <= rdo_med_stat_op(13) or cts_med_stat_op(13);
-
-  THE_PLL : pll_in100_out100
-    port map(
-      CLK      => CLK_100_IN,
-      CLKOP    => clk_100,
-      LOCK     => pll_locked
-      );
-
-
-  THE_RESET_HANDLER : trb_net_reset_handler
-    generic map(
-      RESET_DELAY     => x"0EEE"
-      )
-    port map(
-      CLEAR_IN        => '0',            -- reset input (high active, async)
-      CLEAR_N_IN      => '1',            -- reset input (low active, async)
-      CLK_IN          => CLK_100_IN,     -- raw master clock, NOT from PLL/DLL!
-      SYSCLK_IN       => clk_100,        -- PLL/DLL remastered clock
-      PLL_LOCKED_IN   => pll_locked,     -- master PLL lock signal (async)
-      RESET_IN        => '0',            -- general reset signal (SYSCLK)
-      TRB_RESET_IN    => make_reset_via_network, -- TRBnet reset signal (SYSCLK)
-      CLEAR_OUT       => reset_async,    -- async reset out, USE WITH CARE!
-      RESET_OUT       => reset_i,    -- synchronous reset out (SYSCLK)
-      DEBUG_OUT       => open
-    );
-
----------------------------------------------------------------------------
---  Media Interface
----------------------------------------------------------------------------
-  --Link to send IPU data & for slow control
-  THE_MEDIA_INTERFACE_0 : trb_net16_med_ecp_sfp_gbe
-    generic map(
-      SERDES_NUM => 0,
-      EXT_CLOCK  => c_NO
-      )
-    port map(
-      CLK                      => CLK_100_IN,
-      SYSCLK                   => clk_100,
-      RESET                    => reset_i,
-      CLEAR                    => reset_async,
-      CLK_EN                   => clk_en,
-      --Internal Connection
-      MED_DATA_IN              => rdo_med_data_out,
-      MED_PACKET_NUM_IN        => rdo_med_packet_num_out,
-      MED_DATAREADY_IN         => rdo_med_dataready_out,
-      MED_READ_OUT             => rdo_med_read_in,
-      MED_DATA_OUT             => rdo_med_data_in,
-      MED_PACKET_NUM_OUT       => rdo_med_packet_num_in,
-      MED_DATAREADY_OUT        => rdo_med_dataready_in,
-      MED_READ_IN              => rdo_med_read_out,
-      REFCLK2CORE_OUT          => open,
-      --SFP Connection
-      SD_RXD_P_IN              => SFP_DATA_RX(0),
-      SD_RXD_N_IN              => SFP_DATA_RX(1),
-      SD_TXD_P_OUT             => SFP_DATA_TX(0),
-      SD_TXD_N_OUT             => SFP_DATA_TX(1),
-      SD_REFCLK_P_IN           => '0',
-      SD_REFCLK_N_IN           => '0',
-      SD_PRSNT_N_IN            => GBE_MOD(0),
-      SD_LOS_IN                => GBE_LOS,
-      SD_TXDIS_OUT             => GBE_TX_DIS,
-      -- Status and control port
-      STAT_OP                  => rdo_med_stat_op,
-      CTRL_OP                  => rdo_med_ctrl_op,
-      STAT_DEBUG               => open,
-      CTRL_DEBUG               => (others => '0')
-    );
-
-  --Link to send triggers & readout requests
-  THE_MEDIA_INTERFACE_1 : trb_net16_med_ecp_sfp_gbe
-    generic map(
-      SERDES_NUM => 0,
-      EXT_CLOCK  => c_NO
-      )
-    port map(
-      CLK                      => CLK_100_IN,
-      SYSCLK                   => clk_100,
-      RESET                    => reset_i,
-      CLEAR                    => reset_async,
-      CLK_EN                   => clk_en,
-      --Internal Connection
-      MED_DATA_IN              => cts_med_data_out,
-      MED_PACKET_NUM_IN        => cts_med_packet_num_out,
-      MED_DATAREADY_IN         => cts_med_dataready_out,
-      MED_READ_OUT             => cts_med_read_in,
-      MED_DATA_OUT             => cts_med_data_in,
-      MED_PACKET_NUM_OUT       => cts_med_packet_num_in,
-      MED_DATAREADY_OUT        => cts_med_dataready_in,
-      MED_READ_IN              => cts_med_read_out,
-      REFCLK2CORE_OUT          => open,
-      --SFP Connection
-      SD_RXD_P_IN              => SFP_DATA_RX(2),
-      SD_RXD_N_IN              => SFP_DATA_RX(3),
-      SD_TXD_P_OUT             => SFP_DATA_TX(2),
-      SD_TXD_N_OUT             => SFP_DATA_TX(3),
-      SD_REFCLK_P_IN           => '0',
-      SD_REFCLK_N_IN           => '0',
-      SD_PRSNT_N_IN            => TRB_MOD(0),
-      SD_LOS_IN                => TRB_LOS,
-      SD_TXDIS_OUT             => TRB_TX_DIS,
-      -- Status and control port
-      STAT_OP                  => cts_med_stat_op,
-      CTRL_OP                  => cts_med_ctrl_op,
-      STAT_DEBUG               => open,
-      CTRL_DEBUG               => (others => '0')
-    );
-
----------------------------------------------------------------------------
--- TrbNet Endpoint
----------------------------------------------------------------------------
-
-
---the standard endpoint to send data
-  THE_DATA_ENDPOINT: trb_net16_endpoint_hades_full_handler
-    generic map(
-      REGIO_NUM_STAT_REGS        => RDO_NUM_STAT_REGS,
-      REGIO_NUM_CTRL_REGS        => RDO_NUM_CTRL_REGS,
-      ADDRESS_MASK               => x"FFFF",
-      BROADCAST_BITMASK          => x"FF",
-      REGIO_INIT_ADDRESS         => x"FC02",
-      REGIO_COMPILE_TIME         => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
-      REGIO_INIT_ENDPOINT_ID     => x"0002",
-      REGIO_COMPILE_VERSION      => x"0000",
-      REGIO_HARDWARE_VERSION     => x"52000000",
-      REGIO_USE_1WIRE_INTERFACE  => c_YES,
-      TIMING_TRIGGER_RAW         => c_NO,
-      CLOCK_FREQUENCY            => 100,
-      DATA_INTERFACE_NUMBER      => 1,
-      DATA_BUFFER_DEPTH          => 11,
-      DATA_BUFFER_WIDTH          => 32,
-      DATA_BUFFER_FULL_THRESH    => 2**11-128,
-      TRG_RELEASE_AFTER_DATA     => c_YES,
-      HEADER_BUFFER_DEPTH        => 9,
-      HEADER_BUFFER_FULL_THRESH  => 2**9-10
-      )
-    port map(
-      CLK                        => clk_100,
-      RESET                      => reset_i,
-      CLK_EN                     => clk_en,
-
-      MED_DATAREADY_OUT          => rdo_med_dataready_out,
-      MED_DATA_OUT               => rdo_med_data_out,
-      MED_PACKET_NUM_OUT         => rdo_med_packet_num_out,
-      MED_READ_IN                => rdo_med_read_in,
-      MED_DATAREADY_IN           => rdo_med_dataready_in,
-      MED_DATA_IN                => rdo_med_data_in,
-      MED_PACKET_NUM_IN          => rdo_med_packet_num_in,
-      MED_READ_OUT               => rdo_med_read_out,
-      MED_STAT_OP_IN             => rdo_med_stat_op,
-      MED_CTRL_OP_OUT            => rdo_med_ctrl_op,
-
-      -- LVL1 trigger APL
-      TRG_TIMING_TRG_RECEIVED_IN => rdo_trg_feedback_i, --has to be set for one clock cycle when trigger is sent
-                                                        --on other interface
-      LVL1_TRG_DATA_VALID_OUT    => rdo_trg_data_valid,
-      LVL1_VALID_TIMING_TRG_OUT  => rdo_trg_valid_timing,
-      LVL1_VALID_NOTIMING_TRG_OUT=> rdo_trg_valid_notiming,
-      LVL1_INVALID_TRG_OUT       => rdo_trg_invalid,
-      LVL1_TRG_TYPE_OUT          => rdo_trg_type,
-      LVL1_TRG_NUMBER_OUT        => rdo_trg_number,
-      LVL1_TRG_CODE_OUT          => rdo_trg_code,
-      LVL1_TRG_INFORMATION_OUT   => rdo_trg_information,
-      LVL1_INT_TRG_NUMBER_OUT    => rdo_trg_int_trg_number,
-
-      -- FEE Port
-      FEE_TRG_RELEASE_IN(0)      => rdo_fee_trg_release,
-      FEE_TRG_STATUSBITS_IN      => rdo_fee_trg_statusbits,
-      FEE_DATA_IN                => rdo_fee_data,
-      FEE_DATA_WRITE_IN(0)       => rdo_fee_data_write,
-      FEE_DATA_FINISHED_IN(0)    => rdo_fee_data_finished,
-      FEE_DATA_ALMOST_FULL_OUT(0)=> rdo_fee_data_almost_full,
-
-
-      -- Slow Control Data Port - stat & ctrl of board and readout logic
-      REGIO_COMMON_STAT_REG_IN     => rdo_regio_common_stat_reg_i,
-      REGIO_COMMON_CTRL_REG_OUT    => rdo_regio_common_ctrl_reg_i,
-      REGIO_COMMON_STAT_STROBE_OUT => rdo_regio_common_stat_strobe_i,
-      REGIO_COMMON_CTRL_STROBE_OUT => rdo_regio_common_ctrl_strobe_i,
-
-      REGIO_STAT_REG_IN          => rdo_regio_stat_reg_i,
-      REGIO_CTRL_REG_OUT         => rdo_regio_ctrl_reg_i,
-      REGIO_STAT_STROBE_OUT      => rdo_regio_stat_strobe_i,
-      REGIO_CTRL_STROBE_OUT      => rdo_regio_ctrl_strobe_i,
-
-      --Data interface used to configure Board, Flash & Readout
-      BUS_ADDR_OUT               => rdo_regio_addr_out,
-      BUS_READ_ENABLE_OUT        => rdo_regio_read_enable_out,
-      BUS_WRITE_ENABLE_OUT       => rdo_regio_write_enable_out,
-      BUS_DATA_OUT               => rdo_regio_data_out,
-      BUS_DATA_IN                => rdo_regio_data_in,
-      BUS_DATAREADY_IN           => rdo_regio_dataready_in,
-      BUS_NO_MORE_DATA_IN        => rdo_regio_no_more_data_in,
-      BUS_WRITE_ACK_IN           => rdo_regio_write_ack_in,
-      BUS_UNKNOWN_ADDR_IN        => rdo_regio_unknown_addr_in,
-      BUS_TIMEOUT_OUT            => rdo_regio_timeout_out,
-      ONEWIRE_INOUT              => TEMPSENS,
-      ONEWIRE_MONITOR_OUT        => cts_regio_onewire_monitor_i,
-      ONEWIRE_MONITOR_IN         => '0',
-
-      TIME_GLOBAL_OUT            => rdo_global_time,
-      TIME_LOCAL_OUT             => rdo_local_time,
-      TIME_SINCE_LAST_TRG_OUT    => rdo_time_since_last_trg,
-      TIME_TICKS_OUT             => rdo_timer_ticks
-      );
-
-
---The endpoint for the CTS to send triggers
-  THE_CTS_ENDPOINT : trb_net16_endpoint_hades_cts
-    generic map(
-      REGIO_NUM_STAT_REGS      => CTS_NUM_STAT_REGS, --log2 of number of status registers
-      REGIO_NUM_CTRL_REGS      => CTS_NUM_CTRL_REGS, --log2 of number of ctrl registers
-      --standard values for output registers
-      REGIO_INIT_CTRL_REGS     => (others => '0'),
-      --set to 0 for unused ctrl registers to save resources
-      REGIO_USED_CTRL_REGS     => (others => '1'),
-      --set to 0 for each unused bit in a register
-      REGIO_USED_CTRL_BITMASK  => (others => '1'),
-      REGIO_USE_DAT_PORT       => c_YES,  --internal data port
-      REGIO_INIT_ADDRESS       => x"FC03",
-      REGIO_INIT_BOARD_INFO    => x"0000_0000",
-      REGIO_INIT_ENDPOINT_ID   => x"0003",
-      REGIO_COMPILE_TIME       => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
-      REGIO_COMPILE_VERSION    => x"0001",
-      REGIO_HARDWARE_VERSION   => x"52000001",
-      REGIO_USE_1WIRE_INTERFACE=> c_MONITOR,
-      CLOCK_FREQUENCY          => 100
-      )
-    port map(
-      CLK                        => clk_100,
-      RESET                      => reset_i,
-      CLK_EN                     => clk_en,
-
-      MED_DATAREADY_OUT          => cts_med_dataready_out,
-      MED_DATA_OUT               => cts_med_data_out,
-      MED_PACKET_NUM_OUT         => cts_med_packet_num_out,
-      MED_READ_IN                => cts_med_read_in,
-      MED_DATAREADY_IN           => cts_med_dataready_in,
-      MED_DATA_IN                => cts_med_data_in,
-      MED_PACKET_NUM_IN          => cts_med_packet_num_in,
-      MED_READ_OUT               => cts_med_read_out,
-      MED_STAT_OP_IN             => cts_med_stat_op,
-      MED_CTRL_OP_OUT            => cts_med_ctrl_op,
-
-      --LVL1 trigger
-      TRG_SEND_IN                => cts_trg_send_i,
-      TRG_TYPE_IN                => cts_trg_type_i,
-      TRG_NUMBER_IN              => cts_trg_number_i,
-      TRG_INFORMATION_IN         => cts_trg_information_i,
-      TRG_RND_CODE_IN            => cts_trg_rnd_code_i,
-      TRG_STATUS_BITS_OUT        => cts_trg_statusbits_i,
-      TRG_BUSY_OUT               => cts_trg_busy_i,
-
-      --IPU Request
-      IPU_SEND_IN                => cts_ipu_send_i,
-      IPU_TYPE_IN                => cts_ipu_type_i,
-      IPU_NUMBER_IN              => cts_ipu_number_i,
-      IPU_INFORMATION_IN         => cts_ipu_information_i,
-      IPU_RND_CODE_IN            => cts_ipu_rnd_code_i,
-      -- Receiver port
-      IPU_DATA_OUT               => cts_ipu_data_i,
-      IPU_DATAREADY_OUT          => cts_ipu_dataready_i,
-      IPU_READ_IN                => cts_ipu_read_i,
-      IPU_STATUS_BITS_OUT        => cts_ipu_statusbits_i,
-      IPU_BUSY_OUT               => cts_ipu_busy_i,
-
-      -- Slow Control Data Port - registers for CTS logic
-      REGIO_COMMON_STAT_REG_IN   => cts_common_stat_reg_i,
-      REGIO_COMMON_CTRL_REG_OUT  => cts_common_ctrl_reg_i,
-      REGIO_REGISTERS_IN         => cts_stat_reg_i,
-      REGIO_REGISTERS_OUT        => cts_ctrl_reg_i,
-      COMMON_STAT_REG_STROBE     => cts_common_stat_strobe_i,
-      COMMON_CTRL_REG_STROBE     => cts_common_ctrl_strobe_i,
-      STAT_REG_STROBE            => cts_stat_strobe_i,
-      CTRL_REG_STROBE            => cts_ctrl_strobe_i,
-      --Internal Data Port for CTS configuration
-      REGIO_ADDR_OUT             => cts_regio_addr_i,
-      REGIO_READ_ENABLE_OUT      => cts_regio_read_i,
-      REGIO_WRITE_ENABLE_OUT     => cts_regio_write_i,
-      REGIO_DATA_OUT             => cts_regio_data_out_i,
-      REGIO_DATA_IN              => cts_regio_data_in_i,
-      REGIO_DATAREADY_IN         => cts_regio_dataready_i,
-      REGIO_NO_MORE_DATA_IN      => cts_regio_no_more_data_i,
-      REGIO_WRITE_ACK_IN         => cts_regio_write_ack_i,
-      REGIO_UNKNOWN_ADDR_IN      => cts_regio_unknown_addr_i,
-      REGIO_TIMEOUT_OUT          => cts_regio_timeout_i,
-      REGIO_ONEWIRE_INOUT        => open,
-      REGIO_ONEWIRE_MONITOR_OUT  => open,
-      REGIO_ONEWIRE_MONITOR_IN   => cts_regio_onewire_monitor_i,
-      TRIGGER_MONITOR_IN         => '0',
-      GLOBAL_TIME_OUT            => cts_global_time_i,
-      LOCAL_TIME_OUT             => cts_local_time_i,
-      TIME_SINCE_LAST_TRG_OUT    => open,
-      TIMER_TICKS_OUT            => cts_timer_ticks_i,
-      STAT_DEBUG_1               => open,
-      STAT_DEBUG_2               => open
-      );
-
----------------------------------------------------------------------------
--- Bus Handler on readout/slowcontrol endpoint
----------------------------------------------------------------------------
---  D000         spi status register
---  D001         spi ctrl register
---  D100 - D13F  spi memory
-
-  THE_RDO_BUS_HANDLER : trb_net16_regio_bus_handler
-    generic map(
-      PORT_NUMBER    => 2,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 1,       1 => 6,       others => 0)
-      )
-    port map(
-      CLK                   => clk_100,
-      RESET                 => reset_i,
-
-      DAT_ADDR_IN           => rdo_regio_addr_out,
-      DAT_DATA_IN           => rdo_regio_data_out,
-      DAT_DATA_OUT          => rdo_regio_data_in,
-      DAT_READ_ENABLE_IN    => rdo_regio_read_enable_out,
-      DAT_WRITE_ENABLE_IN   => rdo_regio_write_enable_out,
-      DAT_TIMEOUT_IN        => rdo_regio_timeout_out,
-      DAT_DATAREADY_OUT     => rdo_regio_dataready_in,
-      DAT_WRITE_ACK_OUT     => rdo_regio_write_ack_in,
-      DAT_NO_MORE_DATA_OUT  => rdo_regio_no_more_data_in,
-      DAT_UNKNOWN_ADDR_OUT  => rdo_regio_unknown_addr_in,
-
-    --Bus Handler (SPI CTRL)
-      BUS_READ_ENABLE_OUT(0)               => spictrl_read_en,
-      BUS_WRITE_ENABLE_OUT(0)              => spictrl_write_en,
-      BUS_DATA_OUT(0*32+31 downto 0*32)    => spictrl_data_in,
-      BUS_ADDR_OUT(0*16)                   => spictrl_addr,
-      BUS_ADDR_OUT(0*16+15 downto 0*16+1)  => open,
-      BUS_TIMEOUT_OUT(0)                   => open,
-      BUS_DATA_IN(0*32+31 downto 0*32)     => spictrl_data_out,
-      BUS_DATAREADY_IN(0)                  => spictrl_ack,
-      BUS_WRITE_ACK_IN(0)                  => spictrl_ack,
-      BUS_NO_MORE_DATA_IN(0)               => spictrl_busy,
-      BUS_UNKNOWN_ADDR_IN(0)               => '0',
-    --Bus Handler (SPI Memory)
-      BUS_READ_ENABLE_OUT(1)               => spimem_read_en,
-      BUS_WRITE_ENABLE_OUT(1)              => spimem_write_en,
-      BUS_DATA_OUT(1*32+31 downto 1*32)    => spimem_data_in,
-      BUS_ADDR_OUT(1*16+5 downto 1*16)     => spimem_addr,
-      BUS_ADDR_OUT(1*16+15 downto 1*16+6)  => open,
-      BUS_TIMEOUT_OUT(1)                   => open,
-      BUS_DATA_IN(1*32+31 downto 1*32)     => spimem_data_out,
-      BUS_DATAREADY_IN(1)                  => spimem_ack,
-      BUS_WRITE_ACK_IN(1)                  => spimem_ack,
-      BUS_NO_MORE_DATA_IN(1)               => '0',
-      BUS_UNKNOWN_ADDR_IN(1)               => '0',
-      STAT_DEBUG  => open
-      );
-
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-  THE_SPI_MASTER: spi_master
-    port map(
-      CLK_IN         => clk_100,
-      RESET_IN       => reset_i,
-      -- Slave bus
-      BUS_READ_IN    => spictrl_read_en,
-      BUS_WRITE_IN   => spictrl_write_en,
-      BUS_BUSY_OUT   => spictrl_busy,
-      BUS_ACK_OUT    => spictrl_ack,
-      BUS_ADDR_IN(0) => spictrl_addr,
-      BUS_DATA_IN    => spictrl_data_in,
-      BUS_DATA_OUT   => spictrl_data_out,
-      -- SPI connections
-      SPI_CS_OUT     => SPI_CS_OUT,
-      SPI_SDI_IN     => SPI_SO_IN,
-      SPI_SDO_OUT    => SPI_SI_OUT,
-      SPI_SCK_OUT    => SPI_CLK_OUT,
-      -- BRAM for read/write data
-      BRAM_A_OUT     => spi_bram_addr,
-      BRAM_WR_D_IN   => spi_bram_wr_d,
-      BRAM_RD_D_OUT  => spi_bram_rd_d,
-      BRAM_WE_OUT    => spi_bram_we,
-      -- Status lines
-      STAT           => open
-      );
-
-  -- data memory for SPI accesses
-  THE_SPI_MEMORY: spi_databus_memory
-    port map(
-      CLK_IN        => clk_100,
-      RESET_IN      => reset_i,
-      -- Slave bus
-      BUS_ADDR_IN   => spimem_addr,
-      BUS_READ_IN   => spimem_read_en,
-      BUS_WRITE_IN  => spimem_write_en,
-      BUS_ACK_OUT   => spimem_ack,
-      BUS_DATA_IN   => spimem_data_in,
-      BUS_DATA_OUT  => spimem_data_out,
-      -- state machine connections
-      BRAM_ADDR_IN  => spi_bram_addr,
-      BRAM_WR_D_OUT => spi_bram_wr_d,
-      BRAM_RD_D_IN  => spi_bram_rd_d,
-      BRAM_WE_IN    => spi_bram_we,
-      -- Status lines
-      STAT          => open
-      );
-
-
----------------------------------------------------------------------------
--- Reboot FPGA
----------------------------------------------------------------------------
-  PROC_REBOOT : process (clk_100)
-    begin
-      if reset_i = '1' then
-        PROGRAMN_OUT             <= '1';
-        delayed_restart_fpga     <= '0';
-        restart_fpga_counter     <= x"FFF";
-      elsif rising_edge(clk_100) then
-        PROGRAMN_OUT             <= not delayed_restart_fpga;
-        delayed_restart_fpga     <= '0';
-        if rdo_regio_common_ctrl_reg_i(15) = '1' then
-          restart_fpga_counter   <= x"000";
-        elsif restart_fpga_counter /= x"FFF" then
-          restart_fpga_counter   <= restart_fpga_counter + 1;
-          if restart_fpga_counter >= x"F00" then
-            delayed_restart_fpga <= '1';
-          end if;
-        end if;
-      end if;
-    end process;
-
----------------------------------------------------------------------------
--- I/O connection
----------------------------------------------------------------------------
-
-  ONEWIRE_MONITOR_OUT <= cts_regio_onewire_monitor_i;
-
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
-  PROC_REG_LED : process(clk_100)
-    begin
-      if rising_edge(clk_100) then
-        LED_TRB_OK <= not cts_med_stat_op(9);
-        LED_TRB_RX <= not cts_med_stat_op(10);
-        LED_TRB_TX <= not cts_med_stat_op(11);
-        LED_GBE_OK <= not rdo_med_stat_op(9);
-        LED_GBE_RX <= not rdo_med_stat_op(10);
-        LED_GBE_TX <= not rdo_med_stat_op(11);
-      end if;
-    end process;
-
-  LED_RED     <= '1';
-  LED_YELLOW  <= '1';
-  LED_GREEN   <= '1';
-  LED_ORANGE  <= '1';
-
-
-end architecture;
diff --git a/cts/project2/cts.ldf b/cts/project2/cts.ldf
deleted file mode 100755 (executable)
index 477dc19..0000000
+++ /dev/null
@@ -1,533 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<BaliProject version="2.0" title="cts" device="LFE3-150EA-8FN1156C" default_implementation="cts">
-    <Options/>
-    <Implementation title="cts" dir="cts" description="cts" default_strategy="Strategy1">
-        <Options top="trb3_central"/>
-        <Source name="../version.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_hub_func.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../base/trb3_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../base/code/mbs_vulom_recv.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/basics/signal_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/basics/pulse_sync.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/special/trb_net_reset_handler.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_ch4.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_receive_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_main_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_mac_control.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_prioritizer.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Forward.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test1.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Trash.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_type_validator.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ip_configurator.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_buf.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/trb_net16_gbe_setup.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/mb_mac_sim.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/slv_mac_memory.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_16kx8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x72.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/statts_mem.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/sgmii_channel_smi.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_pcs.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_cdr.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v" type="Verilog" type_short="Verilog">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_api_ipu_streaming_internal.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net16_ipudata.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_CRC.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
-        <Source name="../../../trbnet/trb_net_onewire.vhd" type="VHDL" type_short="VHDL">
-            <Options/>
-        </Source>
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