*.kate-swp
*.html
*.xml
-source/serdes_4_sync_downstream.ipx
-source/serdes_4_sync_downstream.lpc
-source/serdes_sync_client_upstream.ipx
-source/serdes_sync_upstream.ipx
-source/serdes_sync_upstream.lpc
-source/serdes_sync_upstream.txt
-source/soda_client_synconstraints.fdc
-source/soda_hub_synconstraints.fdc
-source/soda_source_clock_constraints.sdc
-source/soda_source_syn_translated.fdc
-source/soda_source_synconstraints.fdc
+
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_4_sync_hub_downstream" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 16 12:16:55.909" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_4_sync_hub_downstream" module="serdes_4_sync_hub_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 05 06 15:48:36.454" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_4_sync_hub_downstream.lpc" type="lpc" modified="2014 04 16 12:16:52.000"/>
- <File name="serdes_4_sync_hub_downstream.pp" type="pp" modified="2014 04 16 12:16:52.000"/>
- <File name="serdes_4_sync_hub_downstream.sym" type="sym" modified="2014 04 16 12:16:52.000"/>
- <File name="serdes_4_sync_hub_downstream.tft" type="tft" modified="2014 04 16 12:16:52.000"/>
- <File name="serdes_4_sync_hub_downstream.txt" type="pcs_module" modified="2014 04 16 12:16:52.000"/>
- <File name="serdes_4_sync_hub_downstream.vhd" type="top_level_vhdl" modified="2014 04 16 12:16:52.000"/>
+ <File name="serdes_4_sync_hub_downstream.lpc" type="lpc" modified="2014 05 06 15:48:34.000"/>
+ <File name="serdes_4_sync_hub_downstream.pp" type="pp" modified="2014 05 06 15:48:34.000"/>
+ <File name="serdes_4_sync_hub_downstream.sym" type="sym" modified="2014 05 06 15:48:35.000"/>
+ <File name="serdes_4_sync_hub_downstream.tft" type="tft" modified="2014 05 06 15:48:35.000"/>
+ <File name="serdes_4_sync_hub_downstream.txt" type="pcs_module" modified="2014 05 06 15:48:35.000"/>
+ <File name="serdes_4_sync_hub_downstream.vhd" type="top_level_vhdl" modified="2014 05 06 15:48:34.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_4_sync_hub_downstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=04/16/2014
-Time=12:16:52
+Date=05/06/2014
+Time=15:48:34
[Parameters]
Verilog=0
_cc_match_mode1=1
_cc_match_mode2=1
_cc_match_mode3=1
-_k00=01
-_k01=01
-_k02=01
-_k03=01
+_k00=00
+_k01=00
+_k02=00
+_k03=00
_k10=00
_k11=00
_k12=00
_k32=01
_k33=01
_byten00=00011100
-_byten01=0000000000011100
-_byten02=0000000000011100
-_byten03=0000000000011100
+_byten01=00011100
+_byten02=00011100
+_byten03=00011100
_byten10=00000000
_byten11=00000000
_byten12=00000000
CH1_CTC "DISABLED"
CH2_CTC "DISABLED"
CH3_CTC "DISABLED"
-CH0_CC_MATCH4 "0100011100"
-CH1_CC_MATCH4 "010000000000011100"
-CH2_CC_MATCH4 "010000000000011100"
-CH3_CC_MATCH4 "010000000000011100"
+CH0_CC_MATCH4 "0000011100"
+CH1_CC_MATCH4 "0000011100"
+CH2_CC_MATCH4 "0000011100"
+CH3_CC_MATCH4 "0000011100"
CH0_CC_MATCH_MODE "1"
CH1_CC_MATCH_MODE "1"
CH2_CC_MATCH_MODE "1"
CH0_RX_EQ "DISABLED"
CH0_RTERM_RX "50"
CH0_RX_DCC "DC"
-CH0_LOS_THRESHOLD_LO "3"
+CH0_LOS_THRESHOLD_LO "2"
PLL_TERM "50"
PLL_DCC "AC"
PLL_LOL_SET "0"
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_source_downstream" module="serdes_sync_source_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 15 15:10:19.693" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_source_downstream" module="serdes_sync_source_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 29 08:57:47.690" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_source_downstream.lpc" type="lpc" modified="2014 04 15 15:10:18.000"/>
- <File name="serdes_sync_source_downstream.pp" type="pp" modified="2014 04 15 15:10:18.000"/>
- <File name="serdes_sync_source_downstream.sym" type="sym" modified="2014 04 15 15:10:18.000"/>
- <File name="serdes_sync_source_downstream.tft" type="tft" modified="2014 04 15 15:10:18.000"/>
- <File name="serdes_sync_source_downstream.txt" type="pcs_module" modified="2014 04 15 15:10:18.000"/>
- <File name="serdes_sync_source_downstream.vhd" type="top_level_vhdl" modified="2014 04 15 15:10:18.000"/>
+ <File name="serdes_sync_source_downstream.lpc" type="lpc" modified="2014 04 29 08:57:46.000"/>
+ <File name="serdes_sync_source_downstream.pp" type="pp" modified="2014 04 29 08:57:46.000"/>
+ <File name="serdes_sync_source_downstream.sym" type="sym" modified="2014 04 29 08:57:46.000"/>
+ <File name="serdes_sync_source_downstream.tft" type="tft" modified="2014 04 29 08:57:46.000"/>
+ <File name="serdes_sync_source_downstream.txt" type="pcs_module" modified="2014 04 29 08:57:46.000"/>
+ <File name="serdes_sync_source_downstream.vhd" type="top_level_vhdl" modified="2014 04 29 08:57:46.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_source_downstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=04/15/2014
-Time=15:10:18
+Date=04/29/2014
+Time=08:57:46
[Parameters]
Verilog=0
_rx_data_width1=8
_rx_data_width2=8
_rx_data_width3=8
-_rx_fifo0=DISABLED
+_rx_fifo0=ENABLED
_rx_fifo1=ENABLED
_rx_fifo2=ENABLED
_rx_fifo3=ENABLED
CH0_TX_DATA_WIDTH "8"
CH0_RX_DATA_WIDTH "8"
CH0_TX_FIFO "DISABLED"
-CH0_RX_FIFO "DISABLED"
+CH0_RX_FIFO "ENABLED"
CH0_TDRV "0"
#CH0_TX_FICLK_RATE 200
#CH0_RXREFCLK_RATE "200"
CH0_RX_EQ "DISABLED"
CH0_RTERM_RX "50"
CH0_RX_DCC "DC"
-CH0_LOS_THRESHOLD_LO "2"
+CH0_LOS_THRESHOLD_LO "3"
PLL_TERM "50"
PLL_DCC "AC"
PLL_LOL_SET "0"
hdinp_ch0, hdinn_ch0 : in std_logic;
hdoutp_ch0, hdoutn_ch0 : out std_logic;
sci_sel_ch0 : in std_logic;
+ rxiclk_ch0 : in std_logic;
txiclk_ch0 : in std_logic;
rx_full_clk_ch0 : out std_logic;
rx_half_clk_ch0 : out std_logic;
PCIE_PHYSTATUS_0 => open,
SCISELCH0 => sci_sel_ch0,
SCIENCH0 => fpsc_vhi,
- FF_RXI_CLK_0 => fpsc_vlo,
+ FF_RXI_CLK_0 => rxiclk_ch0,
FF_TXI_CLK_0 => txiclk_ch0,
FF_EBRD_CLK_0 => fpsc_vlo,
FF_RX_F_CLK_0 => rx_full_clk_ch0,
<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 03 20 10:34:14.620" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_upstream" module="serdes_sync_upstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 05 06 11:35:19.966" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
<Package>
- <File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 02 25 13:39:52.000"/>
- <File name="serdes_sync_upstream.pp" type="pp" modified="2014 02 25 13:39:52.000"/>
- <File name="serdes_sync_upstream.sym" type="sym" modified="2014 02 25 13:39:53.000"/>
- <File name="serdes_sync_upstream.tft" type="tft" modified="2014 02 25 13:39:52.000"/>
- <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 02 25 13:39:52.000"/>
- <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 02 25 13:39:52.000"/>
+ <File name="serdes_sync_upstream.lpc" type="lpc" modified="2014 05 06 11:35:18.000"/>
+ <File name="serdes_sync_upstream.pp" type="pp" modified="2014 05 06 11:35:18.000"/>
+ <File name="serdes_sync_upstream.sym" type="sym" modified="2014 05 06 11:35:18.000"/>
+ <File name="serdes_sync_upstream.tft" type="tft" modified="2014 05 06 11:35:18.000"/>
+ <File name="serdes_sync_upstream.txt" type="pcs_module" modified="2014 05 06 11:35:18.000"/>
+ <File name="serdes_sync_upstream.vhd" type="top_level_vhdl" modified="2014 05 06 11:35:18.000"/>
</Package>
</DiamondModule>
ModuleName=serdes_sync_upstream
SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=02/25/2014
-Time=13:39:52
+Date=05/06/2014
+Time=11:35:18
[Parameters]
Verilog=0
_ldr1=DISABLED
_ldr2=DISABLED
_ldr3=DISABLED
-_datarange=2.0
+_datarange=2
_pll_txsrc=INTERNAL
_refclk_mult=10X
-_refclk_rate=200.0
+_refclk_rate=200
_tx_protocol0=DISABLED
_tx_protocol1=DISABLED
_tx_protocol2=DISABLED
_tx_data_width1=8
_tx_data_width2=8
_tx_data_width3=8
-_tx_fifo0=ENABLED
+_tx_fifo0=DISABLED
_tx_fifo1=ENABLED
_tx_fifo2=ENABLED
-_tx_fifo3=ENABLED
-_tx_ficlk_rate0=200.0
-_tx_ficlk_rate1=200.0
-_tx_ficlk_rate2=200.0
-_tx_ficlk_rate3=200.0
+_tx_fifo3=DISABLED
+_tx_ficlk_rate0=200
+_tx_ficlk_rate1=200
+_tx_ficlk_rate2=200
+_tx_ficlk_rate3=200
_pll_rxsrc0=INTERNAL
_pll_rxsrc1=EXTERNAL
_pll_rxsrc2=EXTERNAL
Multiplier1=
Multiplier2=
Multiplier3=
-_rx_datarange0=2.0
+_rx_datarange0=2
_rx_datarange1=2.5
_rx_datarange2=2.5
_rx_datarange3=2
_rx_data_rate1=FULL
_rx_data_rate2=FULL
_rx_data_rate3=FULL
-_rxrefclk_rate0=200.0
+_rxrefclk_rate0=200
_rxrefclk_rate1=250.0
_rxrefclk_rate2=250.0
_rxrefclk_rate3=200
_rx_fifo1=ENABLED
_rx_fifo2=ENABLED
_rx_fifo3=DISABLED
-_rx_ficlk_rate0=200.0
+_rx_ficlk_rate0=200
_rx_ficlk_rate1=250.0
_rx_ficlk_rate2=250.0
_rx_ficlk_rate3=200
_rterm_rx1=50
_rterm_rx2=50
_rterm_rx3=50
-_rx_dcc0=AC
+_rx_dcc0=DC
_rx_dcc1=AC
_rx_dcc2=AC
_rx_dcc3=DC
_cc_match_mode3=1
_k00=01
_k01=00
-_k02=01
+_k02=00
_k03=01
_k10=00
_k11=00
_k33=01
_byten00=00011100
_byten01=00000000
-_byten02=00011100
+_byten02=00000000
_byten03=00011100
_byten10=00000000
_byten11=00000000
_rx_los_port2=Internal
_rx_los_port3=Internal
_sci_ports=ENABLED
-_sci_int_port=ENABLED
-_refck2core=DISABLED
+_sci_int_port=DISABLED
+_refck2core=ENABLED
Regen=module
PAR1=0
PARTrace1=0
sci_sel_quad : in std_logic;
sci_rd : in std_logic;
sci_wrn : in std_logic;
- sci_int : out std_logic;
fpga_txrefclk : in std_logic;
tx_serdes_rst_c : in std_logic;
tx_pll_lol_qd_s : out std_logic;
rst_qd_c : in std_logic;
+ refclk2fpga : out std_logic;
serdes_rst_qd_c : in std_logic);
end serdes_sync_upstream;
attribute CH3_CDR_SRC: string;
attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE";
attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200.000";
+ attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000";
attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string;
attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100.000";
+ attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000";
attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string;
attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200.000";
+ attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200";
attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100";
attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string;
- attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100.000";
+ attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100";
+ attribute FREQUENCY_PIN_REFCK2CORE: string;
+ attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200";
attribute black_box_pad_pin: string;
attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN";
vlo_inst : VLO port map(Z => fpsc_vlo);
vhi_inst : VHI port map(Z => fpsc_vhi);
+ refclk2fpga <= refclk2fpga_sig;
rx_los_low_ch3_s <= rx_los_low_ch3_sig;
rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig;
tx_pll_lol_qd_s <= tx_pll_lol_qd_sig;
SCIRD => sci_rd,
SCIWSTN => sci_wrn,
CYAWSTN => fpsc_vlo,
- SCIINT => sci_int,
+ SCIINT => open,
FFC_CK_CORE_TX => fpga_txrefclk,
FFC_MACRO_RST => serdes_rst_qd_c,
FFC_QUAD_RST => rst_qd_c,
hdinn_ch0 => SD_RXD_N_IN,
hdoutp_ch0 => SD_TXD_P_OUT,
hdoutn_ch0 => SD_TXD_N_OUT,
--- rxiclk_ch0 => clk_200_i, -- read fifo is no longer present! PL!
+ rxiclk_ch0 => clk_200_i, -- read fifo is no longer present! PL!
txiclk_ch0 => clk_200_i,
rx_full_clk_ch0 => clk_rx_full,
rx_half_clk_ch0 => clk_rx_half,
-------------------------------------------------
-- Serdes
-------------------------------------------------
-THE_SERDES : entity work.serdes_sync_client_upstream
+THE_SERDES : entity work.serdes_sync_upstream
port map(
- hdinp_ch0 => SD_RXD_P_IN,
- hdinn_ch0 => SD_RXD_N_IN,
- hdoutp_ch0 => SD_TXD_P_OUT,
- hdoutn_ch0 => SD_TXD_N_OUT,
--- rxiclk_ch0 => clk_200_i, -- no more RX-fifo
- txiclk_ch0 => clk_200_i,
- rx_full_clk_ch0 => clk_rx_full,
- rx_half_clk_ch0 => clk_rx_half,
- tx_full_clk_ch0 => clk_tx_full,
- tx_half_clk_ch0 => clk_tx_half,
- fpga_rxrefclk_ch0 => clk_200_internal,
- txdata_ch0 => tx_data,
- tx_k_ch0 => tx_k,
- tx_force_disp_ch0 => '0',
- tx_disp_sel_ch0 => '0',
- rxdata_ch0 => rx_data,
- rx_k_ch0 => rx_k,
- rx_disp_err_ch0 => open,
- rx_cv_err_ch0 => rx_error,
- rx_serdes_rst_ch0_c => rx_serdes_rst,
- sb_felb_ch0_c => '0',
- sb_felb_rst_ch0_c => '0',
- tx_pcs_rst_ch0_c => tx_pcs_rst,
- tx_pwrup_ch0_c => '1',
- rx_pcs_rst_ch0_c => rx_pcs_rst,
- rx_pwrup_ch0_c => '1',
- rx_los_low_ch0_s => rx_los_low,
- lsm_status_ch0_s => lsm_status,
- rx_cdr_lol_ch0_s => rx_cdr_lol,
- tx_div2_mode_ch0_c => '0',
- rx_div2_mode_ch0_c => '0',
+ hdinp_ch3 => SD_RXD_P_IN,
+ hdinn_ch3 => SD_RXD_N_IN,
+ hdoutp_ch3 => SD_TXD_P_OUT,
+ hdoutn_ch3 => SD_TXD_N_OUT,
+-- rxiclk_ch3 => clk_200_i, -- no more RX-fifo
+ txiclk_ch3 => clk_200_i,
+ rx_full_clk_ch3 => clk_rx_full,
+ rx_half_clk_ch3 => clk_rx_half,
+ tx_full_clk_ch3 => clk_tx_full,
+ tx_half_clk_ch3 => clk_tx_half,
+ fpga_rxrefclk_ch3 => clk_200_internal,
+ txdata_ch3 => tx_data,
+ tx_k_ch3 => tx_k,
+ tx_force_disp_ch3 => '0',
+ tx_disp_sel_ch3 => '0',
+ rxdata_ch3 => rx_data,
+ rx_k_ch3 => rx_k,
+ rx_disp_err_ch3 => open,
+ rx_cv_err_ch3 => rx_error,
+ rx_serdes_rst_ch3_c => rx_serdes_rst,
+ sb_felb_ch3_c => '0',
+ sb_felb_rst_ch3_c => '0',
+ tx_pcs_rst_ch3_c => tx_pcs_rst,
+ tx_pwrup_ch3_c => '1',
+ rx_pcs_rst_ch3_c => rx_pcs_rst,
+ rx_pwrup_ch3_c => '1',
+ rx_los_low_ch3_s => rx_los_low,
+ lsm_status_ch3_s => lsm_status,
+ rx_cdr_lol_ch3_s => rx_cdr_lol,
+ tx_div2_mode_ch3_c => '0',
+ rx_div2_mode_ch3_c => '0',
SCI_WRDATA => sci_data_in_i,
SCI_RDDATA => sci_data_out_i,
SCI_ADDR => sci_addr_i(5 downto 0),
SCI_SEL_QUAD => sci_qd_i,
- SCI_SEL_ch0 => sci_ch_i(0),
+ SCI_SEL_ch3 => sci_ch_i(0),
SCI_RD => sci_read_i,
SCI_WRN => sci_write_i,
THE_RX_FSM : rx_reset_fsm
port map(
RST_N => rst_n,
- RX_REFCLK => clk_200_i, --nternal, -- allways running PL!
+ RX_REFCLK => clk_200_internal, -- allways running PL!
TX_PLL_LOL_QD_S => tx_pll_lol,
RX_SERDES_RST_CH_C => rx_serdes_rst,
RX_CDR_LOL_CH_S => rx_cdr_lol,
--SODA
- signal soda_rx_clock_half : std_logic;
- signal soda_rx_clock_full : std_logic;
- signal tx_dlm_i : std_logic;
- signal rx_dlm_i : std_logic;
- signal tx_dlm_word : std_logic_vector(7 downto 0);
- signal rx_dlm_word : std_logic_vector(7 downto 0);
- signal make_reset : std_logic;
- signal tx_dlm_preview_S : std_logic; --PL!
- signal link_phase_S : std_logic; --PL!
+signal soda_rx_clock_half : std_logic;
+signal soda_rx_clock_full : std_logic;
+signal tx_dlm_i : std_logic;
+signal rx_dlm_i : std_logic;
+signal tx_dlm_word : std_logic_vector(7 downto 0);
+signal rx_dlm_word : std_logic_vector(7 downto 0);
+signal make_reset : std_logic;
+signal tx_dlm_preview_S : std_logic; --PL!
+signal link_phase_S : std_logic; --PL!
-- SODA slow controll
signal soda_ack : std_logic;
attribute syn_keep of soda_rx_clock_full : signal is true;
attribute syn_preserve of soda_rx_clock_half : signal is true;
attribute syn_keep of soda_rx_clock_half : signal is true;
--- attribute syn_preserve of soda_tx_clock_full : signal is true;
--- attribute syn_keep of soda_tx_clock_full : signal is true;
--- attribute syn_preserve of soda_tx_clock_half : signal is true;
--- attribute syn_keep of soda_tx_clock_half : signal is true;
attribute syn_preserve of clk_sys_internal : signal is true;
attribute syn_keep of clk_sys_internal : signal is true;
attribute syn_preserve of clk_raw_internal : signal is true;
---------------------------------------------------------------------------
- TEST_LINE <= (others => '0'); -- otherwise it is floating
LED_RX <= (others => '0'); -- otherwise it is floating
LED_TX <= (others => '0'); -- otherwise it is floating
LED_LINKOK <= (others => '0'); -- otherwise it is floating
THE_SYNC_LINK : med_ecp3_sfp_sync_up
generic map(
- SERDES_NUM => 0, --number of serdes in quad
+ SERDES_NUM => 1, --number of serdes in quad
IS_SYNC_SLAVE => c_YES
)
port map(
TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!
LINK_PHASE_OUT => link_phase_S, --PL!
--SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(0),
- SD_RXD_N_IN => SERDES_ADDON_RX(1),
- SD_TXD_P_OUT => SERDES_ADDON_TX(0),
- SD_TXD_N_OUT => SERDES_ADDON_TX(1),
+ SD_RXD_P_IN => SERDES_ADDON_RX(4), --(0),
+ SD_RXD_N_IN => SERDES_ADDON_RX(5), --(1),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(4), --(0),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(5), --(1),
SD_REFCLK_P_IN => '0',
SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => SFP_MOD0(1),
- SD_LOS_IN => SFP_LOS(1),
- SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1),
+ SD_PRSNT_N_IN => SFP_MOD0(3), --(1),
+ SD_LOS_IN => SFP_LOS(3), --(1),
+ SD_TXDIS_OUT => sfp_txdis_S(3), --(1), --SFP_TXDIS(1),
SCI_DATA_IN => sci1_data_in,
SCI_DATA_OUT => sci1_data_out,
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
- LED_ORANGE <= SFP_LOS(1); --med_stat_op(8);
- LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10);
+ LED_ORANGE <= SFP_LOS(3); --med_stat_op(8);
+ LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10);
LED_GREEN <= med_stat_op(12); --tx_pll_lol
LED_RED <= med_stat_op(11); --rx_cdr_lol
-- LED_ORANGE <= not reset_i when rising_edge(clk_sys_internal);
soda_counter_i <= soda_counter_i+1;
end if;
end process;
+ \r
+ TEST_LINE(0) <= time_counter(1);\r
+ TEST_LINE(1) <= '0';
+ TEST_LINE(2) <= '0';
+ TEST_LINE(3) <= soda_counter_i(2);
+ TEST_LINE(4) <= '0';
+ TEST_LINE(5) <= '0';\r
+ TEST_LINE(6) <= soda_rx_clock_half;
+ TEST_LINE(7) <= '0';
+ TEST_LINE(8) <= '0';
+\r
+ TEST_LINE(15 downto 9) <= (others => '0'); -- otherwise it is floating
-
+
end trb3_periph_sodaclient_arch;
\ No newline at end of file
signal rxup_dlm_word : std_logic_vector(7 downto 0);
signal txup_dlm_preview_S : std_logic; --PL!
signal uplink_phase_S : std_logic; --PL!
- signal uplink_disable_S : std_logic;
+ signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
--SODA downlink
signal txdn_dlm_i : t_HUB_BIT;
-- fix signal names for constraining
attribute syn_preserve of soda_rxup_clock_full : signal is true;
attribute syn_keep of soda_rxup_clock_full : signal is true;
- \r
+
attribute syn_preserve of clk_sys_internal : signal is true;
attribute syn_keep of clk_sys_internal : signal is true;
attribute syn_preserve of clk_raw_internal : signal is true;
TX_DLM_PREVIEW_IN => txup_dlm_preview_S, --PL!
LINK_PHASE_OUT => uplink_phase_S, --PL!
--SFP Connection -- PL!: these are for SIM-only !?! Makes no difference how they are connected; The ip-wizzard does the actual connecting
- SD_RXD_P_IN => SERDES_ADDON_RX(8),
- SD_RXD_N_IN => SERDES_ADDON_RX(9),
- SD_TXD_P_OUT => SERDES_ADDON_TX(8),
- SD_TXD_N_OUT => SERDES_ADDON_TX(9),
+ SD_RXD_P_IN => SERDES_ADDON_RX(4),
+ SD_RXD_N_IN => SERDES_ADDON_RX(5),
+ SD_TXD_P_OUT => SERDES_ADDON_TX(4),
+ SD_TXD_N_OUT => SERDES_ADDON_TX(5),
SD_REFCLK_P_IN => '0',
SD_REFCLK_N_IN => '0',
SD_PRSNT_N_IN => SFP_MOD0(3), -- = A3, was 1 = B0
SD_LOS_IN => SFP_LOS(3),
- SD_TXDIS_OUT => uplink_disable_S, --SFP_TXDIS(3), this signal is now used to release downlinks
+ SD_TXDIS_OUT => sfp_txdis_S(3), --SFP_TXDIS(3), this signal is now used to release downlinks
SCI_DATA_IN => sci1_data_in,
SCI_DATA_OUT => sci1_data_out,
CTRL_DEBUG => (others => '0')
);
- SFP_TXDIS(3) <= uplink_disable_S;
+-- SFP_TXDIS(3) <= sfp_txdis_S;
+ SFP_TXDIS <= sfp_txdis_S;
---------------------------------------------------------------------------
-- The Soda Central
RESET => reset_i,
CLEAR => clear_i,
---------------------------------------------------------------------------------------------------------------------------------------------------------
- LINK_DISABLE_IN => uplink_disable_S,-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
+ LINK_DISABLE_IN => sfp_txdis_S(3),-- downlinks must behave as slaves to uplink connection. Downlinks are released once unlink is established.
---------------------------------------------------------------------------------------------------------------------------------------------------------
-- MED_DATA_IN(0*16+15 downto 0*16) => med_data_out(1*16+15 downto 1*16),
MED_DATA_IN(0) => med_data_out(1*16+15 downto 1*16),
SD_LOS_IN(1) => SFP_LOS(6),
SD_LOS_IN(2) => SFP_LOS(2),
SD_LOS_IN(3) => SFP_LOS(4),
- SD_TXDIS_OUT(0) => SFP_TXDIS(1),
- SD_TXDIS_OUT(1) => SFP_TXDIS(6),
- SD_TXDIS_OUT(2) => SFP_TXDIS(2),
- SD_TXDIS_OUT(3) => SFP_TXDIS(4),
+ SD_TXDIS_OUT(0) => sfp_txdis_S(1),
+ SD_TXDIS_OUT(1) => sfp_txdis_S(6),
+ SD_TXDIS_OUT(2) => sfp_txdis_S(2),
+ SD_TXDIS_OUT(3) => sfp_txdis_S(4),
SCI_DATA_IN => sci2_data_in,
SCI_DATA_OUT => sci2_data_out,
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
- LED_ORANGE <= '1'; --med_stat_op(8);
- LED_YELLOW <= '0'; --med_stat_op(10);
- LED_GREEN <= '0'; --med_stat_op(9);
- LED_RED <= '1'; --med_stat_op(6);
+ LED_ORANGE <= SFP_LOS(1); --med_stat_op(8);
+ LED_YELLOW <= sfp_txdis_S(1); --med_stat_op(10);
+ LED_GREEN <= med_stat_op(12); --tx_pll_lol
+ LED_RED <= med_stat_op(11); --rx_cdr_lol
+-- LED_ORANGE <= '1'; --med_stat_op(8);
+-- LED_YELLOW <= '0'; --med_stat_op(10);
+-- LED_GREEN <= '0'; --med_stat_op(9);
+-- LED_RED <= '1'; --med_stat_op(6);
---------------------------------------------------------------------------
-- DEBUG
<Source name="code/soda_superburst_gen.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="code/med_ecp3_sfp_sync_up.vhd" type="VHDL" type_short="VHDL">
+ <Source name="code/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="code/serdes_sync_client_upstream.vhd" type="VHDL" type_short="VHDL" excluded="TRUE">
+ <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="code/serdes_sync_client_upstream.lpc" type="LPC_Module" type_short="LPC" excluded="TRUE">
+ <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="code/serdes_sync_client_upstream.ipx" type="IPX_Module" type_short="IPX">
+ <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="code/soda_SOB_faker.vhd" type="VHDL" type_short="VHDL">
+ <Source name="code/med_ecp3_sfp_sync_up.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="code/soda_calibration_timer.vhd" type="VHDL" type_short="VHDL">
+ <Source name="code/ip/serdes_sync_upstream.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
- <Source name="code/soda_reply_handler.vhd" type="VHDL" type_short="VHDL">
+ <Source name="code/ip/serdes_sync_upstream.lpc" type="LPC_Module" type_short="LPC">
<Options/>
</Source>
- <Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
+ <Source name="code/ip/serdes_sync_upstream.ipx" type="IPX_Module" type_short="IPX">
<Options/>
</Source>
<Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
<Source name="code/trb3_periph_sodaclient.vhd" type="VHDL" type_short="VHDL">
<Options top_module="trb3_periph_sodaclient"/>
</Source>
- <Source name="soda_client.lpf" type="Logic Preference" type_short="LPF">
+ <Source name="code/soda_client_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC">
<Options/>
</Source>
- <Source name="soda_client_probe.rvl" type="Reveal" type_short="Reveal">
+ <Source name="soda_client.lpf" type="Logic Preference" type_short="LPF">
<Options/>
</Source>
- <Source name="code/soda_client_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC">
+ <Source name="soda_client_probe.rvl" type="Reveal" type_short="Reveal">
<Options/>
</Source>
<Source name="trb3_soda_client.xcf" type="Programming Project File" type_short="Programming">
-rvl_alias "soda_rx_clock_full" "soda_rx_clock_full";
+rvl_alias "clk_soda_i" "clk_soda_i";
RVL_ALIAS "reveal_ist_260" "the_sync_link/the_serdes/rx_full_clk_ch0";
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ;
#LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_200/PCSD_INST" SITE "PCSA" ;
-LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSB" ;
+LOCATE COMP "THE_SYNC_LINK/THE_SERDES/PCSD_INST" SITE "PCSA" ;
#REGION "UPLINK_REGION" "R90C45D" 25 35 DEVSIZE; # Uplink is now fiber !
#REGION "SPI_REGION" "R3C77D" 15 16 DEVSIZE; #"R13C150D" 15 18 DEVSIZE;
#REGION "IOBUF_REGION" "R10C43D" 88 86 DEVSIZE;
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2014-04-14">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_client_probe.rvl" Date="2014-05-06">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_client"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2031949050" Name="trb3_periph_sodaclient_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2035069901" Name="trb3_periph_sodaclient_LA0" ID="0">
<Setting>
- <Clock SampleClk="soda_rx_clock_full" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
+ <Clock SampleClk="clk_soda_i" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="1024"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
</Setting>
<Dataset Name="Base">
<Trace>
- <Bus Name="sfp_los">
- <Sig Type="SIG" Name="sfp_los:1"/>
- <Sig Type="SIG" Name="sfp_los:2"/>
- <Sig Type="SIG" Name="sfp_los:3"/>
- <Sig Type="SIG" Name="sfp_los:4"/>
- <Sig Type="SIG" Name="sfp_los:5"/>
- <Sig Type="SIG" Name="sfp_los:6"/>
- </Bus>
- <Bus Name="the_sync_link/watchdog_timer">
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:0"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:1"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:2"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:3"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:4"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:5"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:6"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:7"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:8"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:9"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:10"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:11"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:12"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:13"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:14"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:15"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:16"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:17"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:18"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:19"/>
- <Sig Type="SIG" Name="the_sync_link/watchdog_timer:20"/>
- </Bus>
- <Bus Name="sfp_txdis">
- <Sig Type="SIG" Name="sfp_txdis:1"/>
- <Sig Type="SIG" Name="sfp_txdis:2"/>
- <Sig Type="SIG" Name="sfp_txdis:3"/>
- <Sig Type="SIG" Name="sfp_txdis:4"/>
- <Sig Type="SIG" Name="sfp_txdis:5"/>
- <Sig Type="SIG" Name="sfp_txdis:6"/>
- </Bus>
- <Sig Type="SIG" Name="tx_dlm_i"/>
- <Sig Type="SIG" Name="tx_dlm_preview_s"/>
- <Bus Name="tx_dlm_word">
- <Sig Type="SIG" Name="tx_dlm_word:0"/>
- <Sig Type="SIG" Name="tx_dlm_word:1"/>
- <Sig Type="SIG" Name="tx_dlm_word:2"/>
- <Sig Type="SIG" Name="tx_dlm_word:3"/>
- <Sig Type="SIG" Name="tx_dlm_word:4"/>
- <Sig Type="SIG" Name="tx_dlm_word:5"/>
- <Sig Type="SIG" Name="tx_dlm_word:6"/>
- <Sig Type="SIG" Name="tx_dlm_word:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/rst"/>
- <Sig Type="SIG" Name="the_sync_link/rst_n"/>
- <Sig Type="SIG" Name="the_sync_link/rst_qd"/>
- <Sig Type="SIG" Name="the_sync_link/rx_allow"/>
- <Sig Type="SIG" Name="the_sync_link/rx_allow_q"/>
<Sig Type="SIG" Name="the_sync_link/rx_cdr_lol"/>
<Bus Name="the_sync_link/rx_data">
<Sig Type="SIG" Name="the_sync_link/rx_data:0"/>
<Sig Type="SIG" Name="the_sync_link/rx_dlm_word:7"/>
</Bus>
<Sig Type="SIG" Name="the_sync_link/rx_error"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/tx_pll_lol_qd_s_int"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_los_low_int"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_lol_los"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_cdr_lol_ch_s"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/rx_los_low_ch_s"/>
<Bus Name="the_sync_link/rx_fsm_state">
<Sig Type="SIG" Name="the_sync_link/rx_fsm_state:0"/>
<Sig Type="SIG" Name="the_sync_link/rx_fsm_state:1"/>
<Sig Type="SIG" Name="the_sync_link/rx_los_low"/>
<Sig Type="SIG" Name="the_sync_link/rx_pcs_rst"/>
<Sig Type="SIG" Name="the_sync_link/rx_serdes_rst"/>
+ <Bus Name="the_sync_link/the_rx_fsm/state_out">
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:0"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:1"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:2"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/state_out:3"/>
+ </Bus>
+ <Bus Name="the_sync_link/the_rx_fsm/cs">
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/cs:0"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/cs:1"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/cs:2"/>
+ </Bus>
+ <Bus Name="the_sync_link/the_rx_fsm/ns">
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/ns:0"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/ns:1"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/ns:2"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_sync_link/sd_los_in"/>
+ <Sig Type="SIG" Name="the_sync_link/sd_txdis_out"/>
<Sig Type="SIG" Name="the_sync_link/tx_allow"/>
<Sig Type="SIG" Name="the_sync_link/tx_allow_q"/>
<Bus Name="the_sync_link/tx_data">
<Sig Type="SIG" Name="the_sync_link/tx_pcs_rst"/>
<Sig Type="SIG" Name="the_sync_link/tx_pll_lol"/>
<Sig Type="SIG" Name="the_sync_link/tx_serdes_rst"/>
- <Sig Type="SIG" Name="the_sync_link/sd_los_in"/>
- <Sig Type="SIG" Name="the_sync_link/sysclk"/>
- <Bus Name="the_sync_link/the_rx_control/rx_state_bits">
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state_bits:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state_bits:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state_bits:2"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state_bits:3"/>
- </Bus>
- <Bus Name="the_sync_link/the_rx_control/rx_state">
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_state:2"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_k_in"/>
- <Bus Name="the_sync_link/the_rx_control/reg_rx_data_in">
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_data_in:0"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_data_in:1"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_data_in:2"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_data_in:3"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_data_in:4"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_data_in:5"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_data_in:6"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/reg_rx_data_in:7"/>
- </Bus>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/got_link_ready_i"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/got_link_ready"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/make_reset_i"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/rx_dlm_i"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/send_link_reset_i"/>
- <Sig Type="SIG" Name="the_sync_link/the_rx_control/start_retr_i"/>
- <Sig Type="SIG" Name="the_sync_link/lsm_status"/>
- <Sig Type="SIG" Name="a_soda_client/start_of_superburst_s"/>
- <Bus Name="a_soda_client/super_burst_nr_s">
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:0"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:1"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:2"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:3"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:4"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:5"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:6"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:7"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:8"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:9"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:10"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:11"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:12"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:13"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:14"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:15"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:16"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:17"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:18"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:19"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:20"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:21"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:22"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:23"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:24"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:25"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:26"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:27"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:28"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:29"/>
- <Sig Type="SIG" Name="a_soda_client/super_burst_nr_s:30"/>
+ <Bus Name="the_sync_link/wa_position">
+ <Sig Type="SIG" Name="the_sync_link/wa_position:0"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:1"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:2"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:3"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:4"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:5"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:6"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:7"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:8"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:9"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:10"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:11"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:12"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:13"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:14"/>
+ <Sig Type="SIG" Name="the_sync_link/wa_position:15"/>
</Bus>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="the_sync_link/watchdog_trigger,"/>
- <TU Serialbits="0" Type="0" ID="2" Sig="the_sync_link/tx_k,"/>
- <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/start_timer:18,"/>
- <TU Serialbits="0" Type="0" ID="4" Sig="the_sync_link/rx_error,"/>
- <TU Serialbits="0" Type="0" ID="5" Sig="the_sync_link/rx_serdes_rst,"/>
- <TU Serialbits="0" Type="0" ID="6" Sig="the_sync_link/rx_los_low,"/>
- <TU Serialbits="0" Type="0" ID="7" Sig="the_sync_link/lsm_status,"/>
- <TU Serialbits="0" Type="0" ID="8" Sig="the_sync_link/rx_cdr_lol,"/>
- <TU Serialbits="0" Type="0" ID="9" Sig="the_sync_link/rst_qd,"/>
- <TU Serialbits="0" Type="0" ID="10" Sig="the_sync_link/serdes_rst_qd,"/>
+ <TU Serialbits="0" Type="0" ID="2" Sig="the_sync_link/rx_error,"/>
+ <TU Serialbits="0" Type="0" ID="3" Sig="the_sync_link/rx_cdr_lol,"/>
+ <TU Serialbits="0" Type="0" ID="4" Sig="the_sync_link/rx_los_low,"/>
+ <TU Serialbits="0" Type="0" ID="5" Sig="(BUS)the_sync_link/rx_fsm_state[3:0],"/>
+ <TU Serialbits="0" Type="0" ID="6" Sig="the_sync_link/tx_pll_lol,"/>
<TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
<TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="6" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="7" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="8" Resource="0"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="9" Resource="0"/>
</Trigger>
</Dataset>
</Core>
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-03-27">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_hub_probe.rvl" Date="2014-05-06">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_hub"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2029450704" Name="trb3_periph_sodahub_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2035084698" Name="trb3_periph_sodahub_LA0" ID="0">
<Setting>
<Clock SampleClk="clk_soda_i" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
<TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
</Setting>
<Dataset Name="Base">
<Trace>
- <Sig Type="SIG" Name="the_hub_sync_uplink/clk_rx_half_out"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/clk_tx_half"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/link_phase_out"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/lsm_status"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rst"/>
+ <Bus Name="sfp_los">
+ <Sig Type="SIG" Name="sfp_los:1"/>
+ <Sig Type="SIG" Name="sfp_los:2"/>
+ <Sig Type="SIG" Name="sfp_los:3"/>
+ <Sig Type="SIG" Name="sfp_los:4"/>
+ <Sig Type="SIG" Name="sfp_los:5"/>
+ <Sig Type="SIG" Name="sfp_los:6"/>
+ </Bus>
+ <Bus Name="sfp_txdis">
+ <Sig Type="SIG" Name="sfp_txdis:1"/>
+ <Sig Type="SIG" Name="sfp_txdis:2"/>
+ <Sig Type="SIG" Name="sfp_txdis:3"/>
+ <Sig Type="SIG" Name="sfp_txdis:4"/>
+ <Sig Type="SIG" Name="sfp_txdis:5"/>
+ <Sig Type="SIG" Name="sfp_txdis:6"/>
+ </Bus>
<Sig Type="SIG" Name="the_hub_sync_uplink/rst_n"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rst_qd"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_allow"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_allow_q"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_cdr_lol"/>
<Bus Name="the_hub_sync_uplink/rx_data">
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:6"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_dlm_word:7"/>
</Bus>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_error"/>
<Bus Name="the_hub_sync_uplink/rx_fsm_state">
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:0"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:1"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_fsm_state:3"/>
</Bus>
<Sig Type="SIG" Name="the_hub_sync_uplink/rx_k"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_los_low"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_pcs_rst"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/rx_serdes_rst"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_allow"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/tx_allow_q"/>
<Bus Name="the_hub_sync_uplink/tx_data">
<Sig Type="SIG" Name="the_hub_sync_uplink/tx_data:0"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/tx_pcs_rst"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/tx_pll_lol"/>
<Sig Type="SIG" Name="the_hub_sync_uplink/tx_serdes_rst"/>
- <Bus Name="sfp_los">
- <Sig Type="SIG" Name="sfp_los:1"/>
- <Sig Type="SIG" Name="sfp_los:2"/>
- <Sig Type="SIG" Name="sfp_los:3"/>
- <Sig Type="SIG" Name="sfp_los:4"/>
- <Sig Type="SIG" Name="sfp_los:5"/>
- <Sig Type="SIG" Name="sfp_los:6"/>
+ <Bus Name="a_soda_hub/super_burst_nr_s">
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:0"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:1"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:2"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:3"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:4"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:5"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:6"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:7"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:8"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:9"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:10"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:11"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:12"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:13"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:14"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:15"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:16"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:17"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:18"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:19"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:20"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:21"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:22"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:23"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:24"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:25"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:26"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:27"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:28"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:29"/>
+ <Sig Type="SIG" Name="a_soda_hub/super_burst_nr_s:30"/>
</Bus>
- <Bus Name="sfp_txdis">
- <Sig Type="SIG" Name="sfp_txdis:1"/>
- <Sig Type="SIG" Name="sfp_txdis:2"/>
- <Sig Type="SIG" Name="sfp_txdis:3"/>
- <Sig Type="SIG" Name="sfp_txdis:4"/>
- <Sig Type="SIG" Name="sfp_txdis:5"/>
- <Sig Type="SIG" Name="sfp_txdis:6"/>
+ <Bus Name="a_soda_hub/rxdn_dlm_in">
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_in:0"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_in:1"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_in:2"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_in:3"/>
+ </Bus>
+ <Bus Name="a_soda_hub/rxdn_dlm_word_in[3:0]">
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:0"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:1"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:2"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:3"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:4"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:5"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:6"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:0:7"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:0"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:1"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:2"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:3"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:4"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:5"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:6"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:1:7"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:0"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:1"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:2"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:3"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:4"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:5"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:6"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:2:7"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:0"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:1"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:2"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:3"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:4"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:5"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:6"/>
+ <Sig Type="SIG" Name="a_soda_hub/rxdn_dlm_word_in:3:7"/>
+ </Bus>
+ <Bus Name="a_soda_hub/txdn_dlm_out">
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_out:0"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_out:1"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_out:2"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_out:3"/>
+ </Bus>
+ <Bus Name="a_soda_hub/txdn_dlm_word_out[3:0]">
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:0"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:1"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:2"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:3"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:4"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:5"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:6"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:0:7"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:0"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:1"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:2"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:3"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:4"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:5"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:6"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:1:7"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:0"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:1"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:2"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:3"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:4"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:5"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:6"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:2:7"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:0"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:1"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:2"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:3"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:4"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:5"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:6"/>
+ <Sig Type="SIG" Name="a_soda_hub/txdn_dlm_word_out:3:7"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/rx_data[3:0]">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:0:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:1:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:2:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_data:3:7"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/rx_k">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/rx_k:3"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/tx_data[3:0]">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:0:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:1:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:2:7"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:3"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:4"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:5"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:6"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_data:3:7"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/tx_k">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/tx_k:3"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/watchdog_trigger">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/watchdog_trigger:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/watchdog_trigger:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/watchdog_trigger:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/watchdog_trigger:3"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/sd_los_in">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/sd_los_in:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/sd_los_in:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/sd_los_in:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/sd_los_in:3"/>
+ </Bus>
+ <Bus Name="the_hub_sync_downlink/sd_txdis_out">
+ <Sig Type="SIG" Name="the_hub_sync_downlink/sd_txdis_out:0"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/sd_txdis_out:1"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/sd_txdis_out:2"/>
+ <Sig Type="SIG" Name="the_hub_sync_downlink/sd_txdis_out:3"/>
</Bus>
- <Sig Type="SIG" Name="uplink_disable_s"/>
- <Sig Type="SIG" Name="uplink_phase_s"/>
</Trace>
<Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="the_hub_sync_uplink/watchdog_trigger,"/>
+ <TU Serialbits="0" Type="0" ID="1" Sig="the_hub_sync_uplink/lsm_status,"/>
+ <TU Serialbits="0" Type="0" ID="2" Sig="the_hub_sync_uplink/watchdog_trigger,"/>
+ <TU Serialbits="0" Type="0" ID="3" Sig="the_hub_sync_uplink/start_timer:18,"/>
+ <TU Serialbits="0" Type="0" ID="4" Sig="the_hub_sync_uplink/rx_error,"/>
+ <TU Serialbits="0" Type="0" ID="5" Sig="the_hub_sync_uplink/got_link_ready_i,"/>
+ <TU Serialbits="0" Type="0" ID="6" Sig="a_soda_hub/start_of_superburst_s,"/>
<TE MaxSequence="1" MaxEvnCnt="1" ID="1" Resource="1"/>
- </Trigger>
- </Dataset>
- </Core>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2029450705" Name="trb3_periph_sodahub_LA1" ID="1">
- <Setting>
- <Clock SampleClk="clk_raw_internal" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
- <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
- <Capture Mode="0" MinSamplesPerTrig="8"/>
- <Event CntEnable="0" MaxEventCnt="8"/>
- <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_trb3_periph_sodahub_LA1_net"/>
- </Setting>
- <Dataset Name="Base">
- <Trace>
- <Sig Type="SIG" Name="the_hub_sync_uplink/got_link_ready_i"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/clk_rx_half_out"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/clk_tx_half"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/link_phase_out"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/lsm_status"/>
- <Sig Type="SIG" Name="the_hub_sync_uplink/tx_pll_lol"/>
- </Trace>
- <Trigger>
- <TU Serialbits="0" Type="0" ID="1" Sig="gsr_n,"/>
- <TE MaxSequence="2" MaxEvnCnt="1" ID="1" Resource="0"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="2" Resource="0"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="3" Resource="0"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="4" Resource="0"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="5" Resource="0"/>
+ <TE MaxSequence="2" MaxEvnCnt="1" ID="6" Resource="0"/>
</Trigger>
</Dataset>
</Core>
<Source name="code/soda_tx_control.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
+ <Source name="code/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="code/ip/serdes_sync_source_downstream.ipx" type="IPX_Module" type_short="IPX">
+ <Options/>
+ </Source>
<Source name="../trb3/base/cores/pll_in200_out100.vhd" type="VHDL" type_short="VHDL">
<Options/>
</Source>
<Source name="code/trb3_periph_sodasource.vhd" type="VHDL" type_short="VHDL">
<Options top_module="trb3_periph_sodasource"/>
</Source>
- <Source name="code/soda_packet_builder.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/posedge_to_pulse.vhd" type="VHDL" type_short="VHDL">
- <Options/>
- </Source>
- <Source name="code/serdes_sync_source_downstream.ipx" type="IPX_Module" type_short="IPX">
- <Options/>
- </Source>
<Source name="code/soda_source_synconstraints.fdc" type="Synplify Design Constraints File" type_short="SDC">
<Options/>
</Source>
+++ /dev/null
-#-- Synopsys, Inc.
-#-- Version I-2013.09L
-#-- Project file /local/lemmens/lattice/soda/soda_source/soda_source_syn.prj
-#-- Written on Tue Apr 15 15:02:27 2014
-
-
-#project files
-add_file -fpga_constraint "/local/lemmens/lattice/soda/code/soda_source_synconstraints.fdc"
-add_file -vhdl -lib work "/usr/local/diamond/3.1_x64/cae_library/synthesis/vhdl/ecp3.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/version.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_components.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_source.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_d8crc8.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_packet_handler.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_superburst_gen.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/med_ecp3_sfp_sync_down.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_SOB_faker.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_calibration_timer.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_reply_handler.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_tx_control.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/cores/pll_in200_out100.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trb3/base/trb3_components.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_CRC8.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_lvl1.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_data.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_ipu.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/handler_trigger_and_data.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/trb_net_reset_handler.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/fpga_reboot.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_slim.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_master.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_ltc2600.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/rom_16x8.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/ram.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/pulse_sync.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/state_sync.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/ram_16x8_dp.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/ram_dp.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/signal_sync.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/ram_dp_rw.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/basics/pulse_stretch.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf5.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf6.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_regio_bus_handler.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_dummy_fifo.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_dummy_fifo.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_term_ibuf.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_obuf_nodata.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_trigger.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_endpoint_hades_full_handler.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/med_sync_define.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/rx_control.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_base.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_func.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/trb_net16_hub_logic.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/trbnet/special/spi_flash_and_fpga_reload.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/trb3_periph_sodasource.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/soda_packet_builder.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/posedge_to_pulse.vhd"
-add_file -vhdl -lib work "/local/lemmens/lattice/soda/code/serdes_sync_source_downstream.vhd"
-
-
-
-#implementation: "soda_source"
-impl -add soda_source -type fpga
-
-#
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -project_relative_includes 1
-
-#device options
-set_option -technology LATTICE-ECP3
-set_option -part LFE3_150EA
-set_option -package FN672C
-set_option -speed_grade -8
-set_option -part_companion ""
-
-#compilation/mapping options
-set_option -top_module "trb3_periph_sodasource"
-
-# mapper_options
-set_option -frequency 200
-set_option -write_verilog 0
-set_option -write_vhdl 0
-set_option -srs_instrumentation 1
-
-# Lattice XP
-set_option -maxfan 1000
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 1
-set_option -forcegsr auto
-set_option -fix_gated_and_generated_clocks 1
-set_option -RWCheckOnRam 1
-set_option -update_models_cp 0
-set_option -syn_edif_array_rename 1
-
-# sequential_optimization_options
-set_option -symbolic_fsm_compiler 1
-
-# Compiler Options
-set_option -compiler_compatible 0
-set_option -resource_sharing 1
-set_option -multi_file_compilation_unit 1
-
-#automatic place and route (vendor) options
-set_option -write_apr_constraint 1
-
-#set result format/file last
-project -result_file "./soda_source.edi"
-impl -active "soda_source"
-<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2014-04-15">
+<Project ModBy="Inserter" SigType="0" Name="/local/lemmens/lattice/soda/soda_source_probe.rvl" Date="2014-04-30">
<IP Version="1_5_062609"/>
<Design DesignEntry="Schematic/VHDL" Synthesis="synplify" DeviceFamily="LatticeECP3" DesignName="soda_source"/>
- <Core InsertDataset="0" Insert="1" Reveal_sig="2032063262" Name="trb3_periph_sodasource_LA0" ID="0">
+ <Core InsertDataset="0" Insert="1" Reveal_sig="2034025010" Name="trb3_periph_sodasource_LA0" ID="0">
<Setting>
<Clock SampleClk="clk_raw_internal" SampleEnable="0" EnableClk="" EnableClk_Pri="0"/>
- <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="256"/>
+ <TraceBuffer Implementation="0" BitTimeStamp="0" hasTimeStamp="0" IncTrigSig="1" BufferDepth="1024"/>
<Capture Mode="0" MinSamplesPerTrig="8"/>
<Event CntEnable="0" MaxEventCnt="8"/>
- <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="0" TrigOutNet="reveal_debug_soda_source_LA0_net"/>
+ <TrigOut Polarity="0" MinPulseWidth="0" TrigOutNetType="1" EnableTrigOut="1" TrigOutNet="reveal_debug_soda_source_LA0_net"/>
</Setting>
<Dataset Name="Base">
<Trace>
<Sig Type="SIG" Name="the_sync_link/tx_fsm_state:3"/>
</Bus>
<Sig Type="SIG" Name="the_sync_link/tx_pll_lol"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_los_low"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_pcs_rst"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_serdes_rst"/>
<Sig Type="SIG" Name="the_sync_link/link_phase_out"/>
<Sig Type="SIG" Name="the_sync_link/tx_dlm_preview_in"/>
<Bus Name="the_sync_link/tx_data">
<Sig Type="SIG" Name="the_sync_link/tx_dlm_word:7"/>
</Bus>
<Sig Type="SIG" Name="the_sync_link/tx_k"/>
+ <Sig Type="SIG" Name="the_sync_link/rx_cdr_lol"/>
<Sig Type="SIG" Name="the_sync_link/rx_k"/>
<Sig Type="SIG" Name="the_sync_link/rx_dlm"/>
<Bus Name="the_sync_link/rx_data">
<Sig Type="SIG" Name="the_soda_source/start_calibration_s"/>
<Sig Type="SIG" Name="the_soda_source/start_of_superburst_s"/>
<Sig Type="SIG" Name="the_soda_source/tx_dlm_preview_out"/>
+ <Bus Name="the_sync_link/the_rx_fsm/counter2">
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:0"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:1"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:2"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:3"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:4"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:5"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:6"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:7"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:8"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:9"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:10"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:11"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:12"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:13"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:14"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:15"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:16"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:17"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:18"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/counter2:19"/>
+ </Bus>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/reset_timer2"/>
+ <Sig Type="SIG" Name="the_sync_link/the_rx_fsm/timer2"/>
</Trace>
<Trigger>
<TU Serialbits="0" Type="0" ID="1" Sig="the_sync_link/start_timer:18,"/>
+++ /dev/null
-<?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 04 07 16:16:02.152" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
- <Package>
- <File name="serdes_sync_downstream.lpc" type="lpc" modified="2014 04 07 16:16:00.000"/>
- <File name="serdes_sync_downstream.pp" type="pp" modified="2014 04 07 16:16:00.000"/>
- <File name="serdes_sync_downstream.sym" type="sym" modified="2014 04 07 16:16:00.000"/>
- <File name="serdes_sync_downstream.tft" type="tft" modified="2014 04 07 16:16:00.000"/>
- <File name="serdes_sync_downstream.txt" type="pcs_module" modified="2014 04 07 16:16:00.000"/>
- <File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2014 04 07 16:16:00.000"/>
- </Package>
-</DiamondModule>
+++ /dev/null
-[Device]
-Family=latticeecp3
-PartType=LFE3-150EA
-PartName=LFE3-150EA-8FN672C
-SpeedGrade=8
-Package=FPBGA672
-OperatingCondition=COM
-Status=P
-
-[IP]
-VendorName=Lattice Semiconductor Corporation
-CoreType=LPM
-CoreStatus=Demo
-CoreName=PCS
-CoreRevision=8.1
-ModuleName=serdes_sync_downstream
-SourceFormat=VHDL
-ParameterFileVersion=1.0
-Date=04/07/2014
-Time=16:16:00
-
-[Parameters]
-Verilog=0
-VHDL=1
-EDIF=1
-Destination=Synplicity
-Expression=BusA(0 to 7)
-Order=Big Endian [MSB:LSB]
-IO=0
-_mode0=RXTX
-_mode1=DISABLED
-_mode2=DISABLED
-_mode3=DISABLED
-_protocol0=G8B10B
-_protocol1=G8B10B
-_protocol2=G8B10B
-_protocol3=G8B10B
-_ldr0=DISABLED
-_ldr1=DISABLED
-_ldr2=DISABLED
-_ldr3=DISABLED
-_datarange=2
-_pll_txsrc=INTERNAL
-_refclk_mult=10X
-_refclk_rate=200
-_tx_protocol0=G8B10B
-_tx_protocol1=DISABLED
-_tx_protocol2=DISABLED
-_tx_protocol3=DISABLED
-_tx_data_rate0=FULL
-_tx_data_rate1=FULL
-_tx_data_rate2=FULL
-_tx_data_rate3=FULL
-_tx_data_width0=8
-_tx_data_width1=8
-_tx_data_width2=8
-_tx_data_width3=8
-_tx_fifo0=DISABLED
-_tx_fifo1=DISABLED
-_tx_fifo2=DISABLED
-_tx_fifo3=DISABLED
-_tx_ficlk_rate0=200
-_tx_ficlk_rate1=200
-_tx_ficlk_rate2=200
-_tx_ficlk_rate3=200
-_pll_rxsrc0=INTERNAL
-_pll_rxsrc1=INTERNAL
-_pll_rxsrc2=INTERNAL
-_pll_rxsrc3=INTERNAL
-Multiplier0=
-Multiplier1=
-Multiplier2=
-Multiplier3=
-_rx_datarange0=2
-_rx_datarange1=2.5
-_rx_datarange2=2.5
-_rx_datarange3=2.5
-_rx_protocol0=G8B10B
-_rx_protocol1=DISABLED
-_rx_protocol2=DISABLED
-_rx_protocol3=DISABLED
-_rx_data_rate0=FULL
-_rx_data_rate1=FULL
-_rx_data_rate2=FULL
-_rx_data_rate3=FULL
-_rxrefclk_rate0=200
-_rxrefclk_rate1=250.0
-_rxrefclk_rate2=250.0
-_rxrefclk_rate3=250.0
-_rx_data_width0=8
-_rx_data_width1=8
-_rx_data_width2=8
-_rx_data_width3=8
-_rx_fifo0=DISABLED
-_rx_fifo1=DISABLED
-_rx_fifo2=DISABLED
-_rx_fifo3=DISABLED
-_rx_ficlk_rate0=200
-_rx_ficlk_rate1=250.0
-_rx_ficlk_rate2=250.0
-_rx_ficlk_rate3=250.0
-_tdrv_ch0=0
-_tdrv_ch1=0
-_tdrv_ch2=0
-_tdrv_ch3=0
-_tx_pre0=DISABLED
-_tx_pre1=DISABLED
-_tx_pre2=DISABLED
-_tx_pre3=DISABLED
-_rterm_tx0=50
-_rterm_tx1=50
-_rterm_tx2=50
-_rterm_tx3=50
-_rx_eq0=DISABLED
-_rx_eq1=DISABLED
-_rx_eq2=DISABLED
-_rx_eq3=DISABLED
-_rterm_rx0=50
-_rterm_rx1=50
-_rterm_rx2=50
-_rterm_rx3=50
-_rx_dcc0=DC
-_rx_dcc1=DC
-_rx_dcc2=DC
-_rx_dcc3=DC
-_los_threshold_mode0=LOS_E
-_los_threshold_mode1=LOS_E
-_los_threshold_mode2=LOS_E
-_los_threshold_mode3=LOS_E
-_los_threshold_lo0=2
-_los_threshold_lo1=2
-_los_threshold_lo2=2
-_los_threshold_lo3=2
-_los_threshold_hi0=7
-_los_threshold_hi1=7
-_los_threshold_hi2=7
-_los_threshold_hi3=7
-_pll_term=50
-_pll_dcc=AC
-_pll_lol_set=0
-_tx_sb0=DISABLED
-_tx_sb1=DISABLED
-_tx_sb2=DISABLED
-_tx_sb3=DISABLED
-_tx_8b10b0=ENABLED
-_tx_8b10b1=ENABLED
-_tx_8b10b2=ENABLED
-_tx_8b10b3=ENABLED
-_rx_sb0=DISABLED
-_rx_sb1=DISABLED
-_rx_sb2=DISABLED
-_rx_sb3=DISABLED
-_ird0=DISABLED
-_ird1=DISABLED
-_ird2=DISABLED
-_ird3=DISABLED
-_rx_8b10b0=ENABLED
-_rx_8b10b1=ENABLED
-_rx_8b10b2=ENABLED
-_rx_8b10b3=ENABLED
-_rxwa0=ENABLED
-_rxwa1=ENABLED
-_rxwa2=ENABLED
-_rxwa3=ENABLED
-_ilsm0=ENABLED
-_ilsm1=ENABLED
-_ilsm2=ENABLED
-_ilsm3=ENABLED
-_scomma0=K28P157
-_scomma1=K28P157
-_scomma2=K28P157
-_scomma3=K28P157
-_comma_a0=1100000101
-_comma_a1=1100000101
-_comma_a2=1100000101
-_comma_a3=1100000101
-_comma_b0=0011111010
-_comma_b1=0011111010
-_comma_b2=0011111010
-_comma_b3=0011111010
-_comma_m0=1111111100
-_comma_m1=1111111100
-_comma_m2=1111111100
-_comma_m3=1111111100
-_ctc0=DISABLED
-_ctc1=DISABLED
-_ctc2=DISABLED
-_ctc3=DISABLED
-_cc_match_mode0=1
-_cc_match_mode1=1
-_cc_match_mode2=1
-_cc_match_mode3=1
-_k00=01
-_k01=00
-_k02=00
-_k03=00
-_k10=00
-_k11=00
-_k12=00
-_k13=00
-_k20=01
-_k21=01
-_k22=01
-_k23=01
-_k30=01
-_k31=01
-_k32=01
-_k33=01
-_byten00=00011100
-_byten01=00000000
-_byten02=00000000
-_byten03=00000000
-_byten10=00000000
-_byten11=00000000
-_byten12=00000000
-_byten13=00000000
-_byten20=00011100
-_byten21=00011100
-_byten22=00011100
-_byten23=00011100
-_byten30=00011100
-_byten31=00011100
-_byten32=00011100
-_byten33=00011100
-_cc_min_ipg0=3
-_cc_min_ipg1=3
-_cc_min_ipg2=3
-_cc_min_ipg3=3
-_cchmark=9
-_cclmark=7
-_loopback=DISABLED
-_lbtype0=DISABLED
-_lbtype1=DISABLED
-_lbtype2=DISABLED
-_lbtype3=DISABLED
-_teidle_ch0=DISABLED
-_teidle_ch1=DISABLED
-_teidle_ch2=DISABLED
-_teidle_ch3=DISABLED
-_rst_gen=DISABLED
-_rx_los_port0=Internal
-_rx_los_port1=Internal
-_rx_los_port2=Internal
-_rx_los_port3=Internal
-_sci_ports=ENABLED
-_sci_int_port=DISABLED
-_refck2core=ENABLED
-Regen=module
-PAR1=0
-PARTrace1=0
-PAR3=0
-PARTrace3=0
-
-[FilesGenerated]
-serdes_sync_downstream.pp=pp
-serdes_sync_downstream.tft=tft
-serdes_sync_downstream.txt=pcs_module
-serdes_sync_downstream.sym=sym
+++ /dev/null
-# This file is used by the simulation model as well as the ispLEVER bitstream
-# generation process to automatically initialize the PCSD quad to the mode
-# selected in the IPexpress. This file is expected to be modified by the
-# end user to adjust the PCSD quad to the final design requirements.
-
-DEVICE_NAME "LFE3-150EA"
-CH0_PROTOCOL "G8B10B"
-CH0_MODE "RXTX"
-CH1_MODE "DISABLED"
-CH2_MODE "DISABLED"
-CH3_MODE "DISABLED"
-CH0_CDR_SRC "REFCLK_CORE"
-PLL_SRC "REFCLK_CORE"
-TX_DATARATE_RANGE "MEDHIGH"
-CH0_RX_DATARATE_RANGE "MEDHIGH"
-REFCK_MULT "10X"
-#REFCLK_RATE 200
-CH0_RX_DATA_RATE "FULL"
-CH0_TX_DATA_RATE "FULL"
-CH0_TX_DATA_WIDTH "8"
-CH0_RX_DATA_WIDTH "8"
-CH0_TX_FIFO "DISABLED"
-CH0_RX_FIFO "DISABLED"
-CH0_TDRV "0"
-#CH0_TX_FICLK_RATE 200
-#CH0_RXREFCLK_RATE "200"
-#CH0_RX_FICLK_RATE 200
-CH0_TX_PRE "DISABLED"
-CH0_RTERM_TX "50"
-CH0_RX_EQ "DISABLED"
-CH0_RTERM_RX "50"
-CH0_RX_DCC "DC"
-CH0_LOS_THRESHOLD_LO "2"
-PLL_TERM "50"
-PLL_DCC "AC"
-PLL_LOL_SET "0"
-CH0_TX_SB "DISABLED"
-CH0_RX_SB "DISABLED"
-CH0_TX_8B10B "ENABLED"
-CH0_RX_8B10B "ENABLED"
-CH0_COMMA_A "1100000101"
-CH0_COMMA_B "0011111010"
-CH0_COMMA_M "1111111100"
-CH0_RXWA "ENABLED"
-CH0_ILSM "ENABLED"
-CH0_CTC "DISABLED"
-CH0_CC_MATCH4 "0100011100"
-CH0_CC_MATCH_MODE "1"
-CH0_CC_MIN_IPG "3"
-CCHMARK "9"
-CCLMARK "7"
-CH0_SSLB "DISABLED"
-CH0_SPLBPORTS "DISABLED"
-CH0_PCSLBPORTS "DISABLED"
-INT_ALL "DISABLED"
-QD_REFCK2CORE "ENABLED"
-
-
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
---library work;
---use work.trb_net_std.all;
---use work.trb_net_components.all;
---use work.trb3_components.all;
---use work.med_sync_define.all;
---use work.version.all;
-
-entity TB_soda_source is
-end entity;
-\r
-architecture TestBench of TB_soda_source is\r
-\r
- -- Clock period definitions
- constant clk_period : time := 4ns;
-\r
-\r
-component super_burst_generator
- generic(
- BURST_COUNT : integer range 1 to 64 := 16 -- number of bursts to be counted between super-bursts
- );
-port(
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
- --Internal Connection
- SODA_BURST_PULSE_IN : in std_logic := '0'; --
- START_OF_SUPERBURST : out std_logic := '0';
- SUPER_BURST_NR_OUT : out std_logic_vector(30 downto 0) := (others => '0')\r
- );
-end component;\r\r
-
-component soda_packet_builder
- port(
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
- --Internal Connection
- SODA_CMD_STROBE_IN : in std_logic := '0'; --
- START_OF_SUPERBURST : in std_logic := '0';
- SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0');
- SODA_CMD_WORD_IN : in std_logic_vector(31 downto 0) := (others => '0'); --REGIO_CTRL_REG in trbnet handler is 32 bit
- TX_DLM_OUT : out std_logic := '0'; --
- TX_DLM_WORD_OUT : out std_logic_vector(7 downto 0) := (others => '0')\r
- );
-end component;\r
-\r
-component soda_packet_handler
-port(
- SYSCLK : in std_logic; -- fabric clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- CLK_EN : in std_logic;
- --Internal Connection
- RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0');
- RX_DLM_IN : in std_logic
- );
-end component;
-\r
---Inputs
- signal rst_S : std_logic;
- signal clk_S : std_logic;
- signal enable_S : std_logic := '0';
- signal soda_cmd_word_S : std_logic_vector(31 downto 0) := (others => '0');
- signal soda_cmd_strobe_S : std_logic := '0';
- signal SOS_S : std_logic := '0';
- signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator
- signal SOB_S : std_logic := '0';
- signal dlm_word_S : std_logic_vector(7 downto 0) := (others => '0');\r
- signal dlm_valid_S : std_logic;\r
-\r
-begin\r
-\r
- superburst_gen : super_burst_generator
- generic map(BURST_COUNT => 16)
- port map(
- SYSCLK => clk_S,
- RESET => rst_S,
- CLEAR => '0',
- CLK_EN => '0',
- --Internal Connection
- SODA_BURST_PULSE_IN => SOB_S,
- START_OF_SUPERBURST => SOS_S,
- SUPER_BURST_NR_OUT => super_burst_nr_S
- );
-\r
- packet_builder : soda_packet_builder\r
- port map(\r
- SYSCLK => clk_S,
- RESET => rst_S,
- CLEAR => '0',
- CLK_EN => '0',
- --Internal Connection
- SODA_CMD_STROBE_IN => soda_cmd_strobe_S,
- START_OF_SUPERBURST => SOS_S,
- SUPER_BURST_NR_IN => super_burst_nr_S,
- SODA_CMD_WORD_IN => soda_cmd_word_S,
- TX_DLM_OUT => dlm_valid_S,
- TX_DLM_WORD_OUT => dlm_word_S
- \r
- );\r
-
- packet_handler : soda_packet_handler
- port map(
- SYSCLK => clk_S,
- RESET => rst_S,
- CLEAR => '0',
- CLK_EN => '0',
- --Internal Connection
- RX_DLM_IN => dlm_valid_S,
- RX_DLM_WORD_IN => dlm_word_S
- );
-\r
-------------------------------------------------------------------------------------------------------------
- -- SODA command packet
-------------------------------------------------------------------------------------------------------------
- cmd_proc :process
- begin
- wait for 2us;
- soda_cmd_word_S <= x"40000000";
- soda_cmd_strobe_S <= '1';
- wait for clk_period;
- soda_cmd_strobe_S <= '0';
- wait;
- end process;
-
-------------------------------------------------------------------------------------------------------------
- -- Clock process definitions
-------------------------------------------------------------------------------------------------------------
- clk_proc :process
- begin
- clk_S <= '0';
- wait for clk_period/2;
- clk_S <= '1';
- wait for clk_period/2;
- end process;
-
- -- reset process
- reset_proc: process
- begin
- rst_S <= '1';
- wait for clk_period * 5;
- rst_S <= '0';
- wait;
- end process;
-\r
- burst_proc :process
- begin
- SOB_S <= '0';
- wait for 2.35us;
- SOB_S <= '1';
- wait for 50ns;
- end process;
-
-\r
-end TestBench;\r
-\r
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140325.bit</File>
- <FileTime>03/26/14 14:07:54</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140506.bit</File>
+ <FileTime>05/06/14 09:58:37</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140325.bit</File>
- <FileTime>03/26/14 09:09:00</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140506.bit</File>
+ <FileTime>05/06/14 09:54:42</FileTime>
<JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140121.bit</File>
- <FileTime>01/21/14 11:21:53</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140506.bit</File>
+ <FileTime>05/06/14 11:55:27</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140121.bit</File>
- <FileTime>01/21/14 11:21:53</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140506.bit</File>
+ <FileTime>05/06/14 11:55:27</FileTime>
<JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20140320.bit</File>
- <FileTime>03/20/14 12:21:09</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodahub_20140506.bit</File>
+ <FileTime>05/06/14 12:42:05</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140320.bit</File>
- <FileTime>03/18/14 15:42:08</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140506.bit</File>
+ <FileTime>05/06/14 12:04:36</FileTime>
<JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140415.bit</File>
- <FileTime>04/15/14 15:30:13</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodaclient_20140430.bit</File>
+ <FileTime>04/30/14 10:18:14</FileTime>
<Operation>Fast Program</Operation>
<Option>
<SVFVendor>JTAG STANDARD</SVFVendor>
<BScanLen>1</BScanLen>
<BScanVal>0</BScanVal>
</Bypass>
- <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140415.bit</File>
- <FileTime>04/15/14 15:17:23</FileTime>
+ <File>/local/lemmens/lattice/soda/trb3_periph_sodasource_20140430.bit</File>
+ <FileTime>04/30/14 10:16:11</FileTime>
<JedecChecksum>N/A</JedecChecksum>
<Operation>Fast Program</Operation>
<Option>
jspc29 / soda.git / commitdiff