--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA15EP1
+PartName=LFSCM3GA15EP1-5F256C
+SpeedGrade=-5
+Package=FPBGA256
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.3
+ModuleName=beam_structure_fifo
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=10/20/2010
+Time=07:05:38
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=512
+RWidth=36
+WDepth=512
+WWidth=36
+regout=1
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Sync
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.3
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n beam_structure_fifo -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 512 -width 36 -rwidth 36 -regout -no_enable -pe 10 -pf 508 -sync_reset -e
+
+-- Wed Oct 20 07:05:38 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity beam_structure_fifo is
+ port (
+ Data: in std_logic_vector(35 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(35 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end beam_structure_fifo;
+
+architecture Structure of beam_structure_fifo is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vhi: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of beam_structure_fifo_0_0 : label is "0b011111111000001";
+ attribute FULLPOINTER of beam_structure_fifo_0_0 : label is "0b011111111100001";
+ attribute AFPOINTER1 of beam_structure_fifo_0_0 : label is "0b011111101000001";
+ attribute AFPOINTER of beam_structure_fifo_0_0 : label is "0b011111101100001";
+ attribute AEPOINTER1 of beam_structure_fifo_0_0 : label is "0b000000101111111";
+ attribute AEPOINTER of beam_structure_fifo_0_0 : label is "0b000000101011111";
+ attribute RESETMODE of beam_structure_fifo_0_0 : label is "SYNC";
+ attribute REGMODE of beam_structure_fifo_0_0 : label is "OUTREG";
+ attribute CSDECODE_R of beam_structure_fifo_0_0 : label is "0b11";
+ attribute CSDECODE_W of beam_structure_fifo_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of beam_structure_fifo_0_0 : label is "36";
+ attribute DATA_WIDTH_W of beam_structure_fifo_0_0 : label is "36";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ beam_structure_fifo_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "011111111000001", FULLPOINTER=> "011111111100001",
+ AFPOINTER1=> "011111101000001", AFPOINTER=> "011111101100001",
+ AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111",
+ RESETMODE=> "SYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>Data(34), DI35=>Data(35),
+ FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
+ EMPTYI=>Empty_int, CSR0=>RdEn, CSR1=>scuba_vhi, WE=>WrEn,
+ RE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset,
+ RPRST=>RPReset, DO0=>Q(18), DO1=>Q(19), DO2=>Q(20),
+ DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), DO7=>Q(25),
+ DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
+ DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33),
+ DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
+ DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
+ DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
+ DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
+ DO34=>Q(16), DO35=>Q(17), EF=>Empty_int, AEF=>AlmostEmpty,
+ AFF=>AlmostFull, FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of beam_structure_fifo is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+
+
+entity cts_align_signals is
+ generic (
+ DELAY : natural;
+ VECTOR_WIDTH : natural
+ );
+ port (
+ CLK : in std_logic;
+ SIGNAL_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ SIGNAL_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0)
+ );
+end cts_align_signals;
+
+architecture cts_align_signals of cts_align_signals is
+
+ type delayed_signals_type is array (0 to 15) of std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ signal delayed_signals : delayed_signals_type;
+
+begin
+
+ MAKE_DELAYS: for i in 0 to 15 generate
+
+ FIRST: if i = 0 generate
+ FIRST_MAKE_DELAYS_PROC : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ delayed_signals(i) <= SIGNAL_VECTOR_IN;
+ end if;
+ end process FIRST_MAKE_DELAYS_PROC;
+ end generate FIRST;
+
+ REST: if i > 0 generate
+ REST_MAKE_DELAYS_PROC : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ delayed_signals(i) <= delayed_signals(i - 1);
+ end if;
+ end process REST_MAKE_DELAYS_PROC;
+ end generate REST;
+
+ end generate MAKE_DELAYS;
+
+ FIRST_OUT: if DELAY = 0 generate
+ SIGNAL_VECTOR_OUT <= SIGNAL_VECTOR_IN;
+ end generate FIRST_OUT;
+
+ REST_OUT: if DELAY > 0 generate
+ SIGNAL_VECTOR_OUT <= delayed_signals(DELAY - 1);
+ end generate REST_OUT;
+
+
+
+end cts_align_signals;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+
+entity cts_beam_structure is
+
+ generic (
+ START_SAMPLE_NUMBER : natural;
+ HOW_MANY_HISTOGRAMS : natural
+ );
+ port (
+ RESET : in std_logic;
+ TRIGGER_CLK : in std_logic; --200MHz
+ LOCAL_CLK : in std_logic; --100MHz
+ START_TIME_OFFSET_IN : in std_logic_vector(31 downto 0);
+ START_TIME_SAMPLE_IN : in std_logic_vector(31 downto 0);
+ START_BEAM_IN : in std_logic;
+ BEAM_INHIBIT_LENGTH_IN : in std_logic_vector(31 downto 0);
+ BEAM_INHIBIT_OUT : out std_logic;
+ BEAM_STRUCTURE_SIGNAL_IN : in std_logic_vector(1 downto 0);
+ BEAM_START_VETO_STRUCKTURE_IN : in std_logic_vector(25 downto 0);
+ STRUCTURE_DATA_OUT : out std_logic_vector(31 downto 0);
+ READ_STRUCTURE_IN : in std_logic;
+ READ_STRUCTURE_FINISHED_OUT : out std_logic;
+ READ_STRUCTURE_START_IN : in std_logic;
+ CTS_BEAM_STRUCTURE_DEBUG : out std_logic_vector(15 downto 0)
+ );
+end cts_beam_structure;
+
+architecture cts_beam_structure of cts_beam_structure is
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+ component beam_structure_fifo
+ port (
+ Data : in std_logic_vector(35 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(35 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+ --basic
+ signal basic_100ns_cntr : std_logic_vector(4 downto 0);
+ signal basic_100ns_pulse : std_logic;
+ signal not_beam_inhibit_in, beam_inhibit_pulse : std_logic;
+ signal fifo_rst : std_logic;
+
+ signal beam_inhibit_cntr_up, beam_inhibit_cntr_rst, internal_beam_inhibit : std_logic;
+ signal beam_inhibit_cntr,beam_inhibit_length_in_buf : std_logic_vector(31 downto 0);
+
+ signal reset_length : std_logic;
+ signal reset_cntr_after_enable : std_logic;
+
+ --start
+ signal start_delay_cntr : std_logic_vector(31 downto 0);
+ signal enable_start_sampling : std_logic;
+ signal start_sample_counter_individual, start_sample_counter : std_logic_vector(31 downto 0);
+ signal start_sample_counter_rst : std_logic;
+ type start_cntr_array is array (0 to 25) of std_logic_vector(31 downto 0);
+ signal start_cntr : start_cntr_array;
+ type start_data_array is array (0 to 25) of std_logic_vector(35 downto 0);
+ signal start_data,start_q : start_data_array;
+ signal start_data_rd_en, start_data_rd_en_fsm, start_empty, start_full : std_logic_vector(25 downto 0);
+ signal beam_start_veto_struckture_in_pulse : std_logic_vector(25 downto 0);
+
+ --data sending
+
+ signal read_structure_finished_out_fsm, read_structure_finished_out_i : std_logic;
+ signal structure_data_out_fsm, structure_data_out_i : std_logic_vector(31 downto 0);
+ signal structure_finished : std_logic;
+ signal special_data_rst, special_data_rst_fsm, special_data_up, special_data_up_fsm : std_logic;
+ signal special_data_cntr : std_logic_vector(12 downto 0);
+ signal individual_cntrs_reset : std_logic;
+
+ signal fifo_cntr : std_logic_vector(4 downto 0);
+ --reseting the counters
+ signal old_beam_structure_length, old_FIne_time_offset_in, old_coarse_time_offset_in, old_start_time_offset_in, old_fine_time_sample_in, old_coarse_time_sample_in, old_start_time_sample_in : std_logic_vector(31 downto 0);
+ signal readout_active : std_logic;
+
+
+begin
+
+-------------------------------------------------------------------------------
+-- basic
+-------------------------------------------------------------------------------
+ BASIC_100ns_COUNTER : process (TRIGGER_CLK, RESET)
+ begin
+ if rising_edge(TRIGGER_CLK) then
+ if RESET = '1' or basic_100ns_cntr = 19 then
+ basic_100ns_cntr <= (others => '0');
+ basic_100ns_pulse <= '1';
+ else
+ basic_100ns_pulse <= '0';
+ basic_100ns_cntr <= basic_100ns_cntr + 1;
+ end if;
+ end if;
+ end process BASIC_100ns_COUNTER;
+
+ SYNC_OLD_LENGTH : process (TRIGGER_CLK, RESET)
+ begin
+ if rising_edge(TRIGGER_CLK) then
+ if RESET = '1' then
+ old_beam_structure_length <= (others => '0');
+ old_start_time_offset_in <= (others => '0');
+ old_start_time_sample_in <= (others => '0');
+ else
+ old_beam_structure_length <= BEAM_INHIBIT_LENGTH_IN;
+ old_start_time_offset_in <= START_TIME_OFFSET_IN;
+ old_start_time_sample_in <= START_TIME_SAMPLE_IN;
+ end if;
+ end if;
+ end process SYNC_OLD_LENGTH;
+
+ RESET_LENGTH_PROC : process (TRIGGER_CLK, RESET) --in case of changes whole
+ --structuer has to be
+ --reseted - counters can be
+ --above the new limits
+ begin
+ if rising_edge(TRIGGER_CLK) then
+ if RESET = '1' then
+ reset_length <= '1';
+ elsif old_beam_structure_length /= BEAM_INHIBIT_LENGTH_IN or
+ old_start_time_offset_in /= START_TIME_OFFSET_IN or
+ old_start_time_sample_in /= START_TIME_SAMPLE_IN
+ then
+ reset_length <= '1';
+ else
+ reset_length <= '0';
+ end if;
+ end if;
+ end process RESET_LENGTH_PROC;
+
+ THE_BEAM_INHIBIT_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 32)
+ port map (
+ CLK => TRIGGER_CLK,
+ RESET => beam_inhibit_cntr_rst,
+ COUNT_OUT => beam_inhibit_cntr,
+ UP_IN => beam_inhibit_cntr_up,
+ DOWN_IN => '0');
+
+ SYNCH_SIGNALS : process (TRIGGER_CLK, RESET)
+ begin
+ if rising_edge(TRIGGER_CLK) then
+ if RESET = '1' then
+ beam_inhibit_length_in_buf <= (others => '0');
+ else
+ beam_inhibit_length_in_buf <= BEAM_INHIBIT_LENGTH_IN;
+ end if;
+ end if;
+ end process SYNCH_SIGNALS;
+
+ SET_BEAM_INHIBIT_CNTR_UP : process (TRIGGER_CLK, RESET)
+ begin
+ if rising_edge(TRIGGER_CLK) then
+ if RESET = '1' or beam_inhibit_cntr = beam_inhibit_length_in_buf or reset_length = '1' or beam_inhibit_length_in_buf = 0 then
+ beam_inhibit_cntr_up <= '0';
+ beam_inhibit_cntr_rst <= '1';
+ elsif START_BEAM_IN = '1' then
+ beam_inhibit_cntr_up <= '0';
+ beam_inhibit_cntr_rst <= '0';
+ else
+ beam_inhibit_cntr_up <= basic_100ns_pulse;
+ beam_inhibit_cntr_rst <= beam_inhibit_cntr_rst;
+ end if;
+ end if;
+ end process SET_BEAM_INHIBIT_CNTR_UP;
+
+
+ SET_BEAM_INHIBIT_SIGNAL : process (TRIGGER_CLK, RESET)
+ begin
+ if rising_edge(TRIGGER_CLK) then
+ if RESET = '1' or START_BEAM_IN = '1' or BEAM_INHIBIT_LENGTH_IN = 0 or reset_length = '1' then
+ internal_beam_inhibit <= '0';
+ elsif beam_inhibit_cntr = BEAM_INHIBIT_LENGTH_IN then
+ internal_beam_inhibit <= '1';
+ else
+ internal_beam_inhibit <= internal_beam_inhibit;
+ end if;
+ end if;
+ end process SET_BEAM_INHIBIT_SIGNAL;
+
+ BEAM_INHIBIT_OUT <= internal_beam_inhibit;
+
+ SYNC_LOCAL_SIGNALS : process (TRIGGER_CLK, RESET)
+ begin
+ if rising_edge(TRIGGER_CLK) then
+ not_beam_inhibit_in <= not internal_beam_inhibit;
+ end if;
+ end process SYNC_LOCAL_SIGNALS;
+
+ BEAM_ON_PULSE: edge_to_pulse
+ port map (
+ clock => TRIGGER_CLK,
+ en_clk => '1',
+ signal_in => not_beam_inhibit_in,
+ pulse => beam_inhibit_pulse);
+
+ FIFO_RST_PULSE: edge_to_pulse
+ port map (
+ clock => TRIGGER_CLK,--LOCAL_CLK,
+ en_clk => '1',
+ signal_in => not_beam_inhibit_in,
+ pulse => fifo_rst);
+
+ CNTR_SATRT_RST_AFTER_ENABLE_SAMPLING_PULSE: edge_to_pulse
+ port map (
+ clock => TRIGGER_CLK,
+ en_clk => '1',
+ signal_in => enable_start_sampling,
+ pulse => reset_cntr_after_enable);
+
+ SET_CNTRS_RESET : process (TRIGGER_CLK, RESET)
+ begin
+ if rising_edge(TRIGGER_CLK) then
+ if RESET = '1' then
+ individual_cntrs_reset <= '0';
+ else
+ individual_cntrs_reset <= beam_inhibit_pulse or start_sample_counter_rst or reset_cntr_after_enable;
+ end if;
+ end if;
+ end process SET_CNTRS_RESET;
+
+ -----------------------------------------------------------------------------
+ -- start individual
+ -----------------------------------------------------------------------------
+
+ START_DELAY_PROC : process (TRIGGER_CLK, RESET)
+ begin
+ if rising_edge(TRIGGER_CLK) then
+ if RESET = '1' or beam_inhibit_pulse = '1' or reset_length = '1' then
+ start_delay_cntr <= (others => '0');
+ elsif start_delay_cntr < START_TIME_OFFSET_IN and basic_100ns_pulse = '1' then
+ start_delay_cntr <= start_delay_cntr + 1;
+ else
+ start_delay_cntr <= start_delay_cntr;
+ end if;
+ end if;
+ end process START_DELAY_PROC;
+
+ ENABLE_SAVING_START_SAMPLES : process (TRIGGER_CLK, RESET)
+ begin
+ if rising_edge(TRIGGER_CLK) then
+ if RESET = '1' or start_sample_counter = START_SAMPLE_NUMBER or reset_length = '1' then
+ enable_start_sampling <= '0';
+ elsif start_delay_cntr = START_TIME_OFFSET_IN and structure_finished = '0' then
+ enable_start_sampling <= '1';
+ end if;
+ end if;
+ end process ENABLE_SAVING_START_SAMPLES;
+
+ THE_START_SAMPLE_COUNTER_INDIVIDUAL : process (TRIGGER_CLK, RESET)
+ begin
+ if rising_edge(TRIGGER_CLK) then
+ if RESET = '1' or start_sample_counter_individual = START_TIME_SAMPLE_IN or reset_length = '1' then
+ start_sample_counter_individual <= (others => '0');
+ elsif basic_100ns_pulse = '1' and enable_start_sampling = '1' then
+ start_sample_counter_individual <= start_sample_counter_individual + 1;
+ else
+ start_sample_counter_individual <= start_sample_counter_individual;
+ end if;
+ end if;
+ end process THE_START_SAMPLE_COUNTER_INDIVIDUAL;
+
+ THE_START_SAMPLE_COUNTER_ALL : process (TRIGGER_CLK, RESET)
+ begin
+ if rising_edge(TRIGGER_CLK) then
+ if RESET = '1' or beam_inhibit_pulse = '1' or reset_length = '1' then
+ start_sample_counter <= (others => '0');
+ start_sample_counter_rst <= '0';
+ elsif start_sample_counter_individual = START_TIME_SAMPLE_IN and start_sample_counter < START_SAMPLE_NUMBER then
+ start_sample_counter_rst <= '1';
+ start_sample_counter <= start_sample_counter + 1;
+ else
+ start_sample_counter <= start_sample_counter;
+ start_sample_counter_rst <= '0';
+ end if;
+ end if;
+ end process THE_START_SAMPLE_COUNTER_ALL;
+
+
+
+
+ MAKE_BEAM_STRUCTURE_FOR_START_INDIVIDUAL: for i in 0 to 25 generate
+ HIST_PULSES: edge_to_pulse
+ port map (
+ clock => TRIGGER_CLK,
+ en_clk => '1',
+ signal_in => BEAM_START_VETO_STRUCKTURE_IN(i),
+ pulse => beam_start_veto_struckture_in_pulse(i));
+
+ THE_START_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 32)
+ port map (
+ CLK => TRIGGER_CLK,
+ RESET => individual_cntrs_reset,--start_sample_counter_rst,
+ COUNT_OUT => start_cntr(i),
+ UP_IN => beam_start_veto_struckture_in_pulse(i),
+ DOWN_IN => '0');
+
+ start_data(i) <= x"0" & start_cntr(i);
+
+ START_FIFO: beam_structure_fifo
+ port map (
+ Data => start_data(i),
+ WrClock => TRIGGER_CLK,
+ RdClock => LOCAL_CLK,
+ WrEn => start_sample_counter_rst,
+ RdEn => start_data_rd_en(i),
+ Reset => fifo_rst,--RESET,
+ RPReset => fifo_rst,--RESET,
+ Q => start_q(i),
+ Empty => start_empty(i),
+ Full => start_full(i),
+ AlmostEmpty => open,
+ AlmostFull => open);
+ end generate MAKE_BEAM_STRUCTURE_FOR_START_INDIVIDUAL;
+
+ -----------------------------------------------------------------------------
+ -- data sending
+ -----------------------------------------------------------------------------
+
+
+ SET_SAMPLING_FINISHED : process (LOCAL_CLK, RESET)
+ begin
+ if rising_edge(LOCAL_CLK) then
+ if RESET = '1' then
+ structure_finished <= '0';
+-- elsif coarse_sample_counter = COARSE_SAMPLE_NUMBER and fine_sample_counter = FINE_SAMPLE_NUMBER and start_sample_counter = START_SAMPLE_NUMBER and fine_empty = '0' and coarse_empty = '0' and start_empty(0) = '0' then
+ elsif start_sample_counter = START_SAMPLE_NUMBER and start_empty(HOW_MANY_HISTOGRAMS-1) = '0' then
+ structure_finished <= '1';
+ else
+ structure_finished <= '0';
+ end if;
+ end if;
+ end process SET_SAMPLING_FINISHED;
+
+ COUNTER_FOR_SPECIAL_DATA: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 13)
+ port map (
+ CLK => LOCAL_CLK,
+ RESET => special_data_rst,
+ COUNT_OUT => special_data_cntr,
+ UP_IN => special_data_up,
+ DOWN_IN => '0');
+
+ CHECK_FOR_SAMPLE_NUMBER : process (LOCAL_CLK, RESET)
+ begin
+ if rising_edge(LOCAL_CLK) then
+ if RESET = '1' or fifo_cntr = HOW_MANY_HISTOGRAMS then
+ special_data_rst <= '1';
+ fifo_cntr <= (others => '0');
+ STRUCTURE_DATA_OUT <= start_q(0)(31 downto 0);
+ elsif special_data_cntr = START_SAMPLE_NUMBER then
+ special_data_rst <= '1';
+ fifo_cntr <= fifo_cntr + 1;
+ STRUCTURE_DATA_OUT <= start_q(conv_integer(fifo_cntr+1))(31 downto 0);
+ else
+ special_data_rst <= '0';
+ fifo_cntr <= fifo_cntr;
+ STRUCTURE_DATA_OUT <= start_q(conv_integer(fifo_cntr))(31 downto 0);
+ end if;
+ end if;
+ end process CHECK_FOR_SAMPLE_NUMBER;
+
+ SET_READOUT_ACTIVE : process (LOCAL_CLK, RESET)
+ begin
+ if rising_edge(LOCAL_CLK) then
+ if RESET = '1' or fifo_cntr = HOW_MANY_HISTOGRAMS then
+ readout_active <= '0';
+ elsif READ_STRUCTURE_START_IN = '1' then
+ readout_active <= '1';
+ else
+ readout_active <= readout_active;
+ end if;
+ end if;
+ end process SET_READOUT_ACTIVE;
+
+ SPECIAL_DATA_UP_CNTR_PROC : process (LOCAL_CLK, RESET)
+ begin
+ if rising_edge(LOCAL_CLK) then
+ if RESET = '1' then
+ special_data_up <= '0';
+ read_structure_finished_out_i <= '0';
+ elsif fifo_cntr = HOW_MANY_HISTOGRAMS then
+ special_data_up <= '0';
+ read_structure_finished_out_i <= '1';
+ elsif READ_STRUCTURE_START_IN = '1' and structure_finished = '1' then
+ special_data_up <= READ_STRUCTURE_IN;
+ read_structure_finished_out_i <= '0';
+ elsif READ_STRUCTURE_START_IN = '1' and structure_finished = '0' then
+ read_structure_finished_out_i <= '1';
+ special_data_up <= '0';
+ else
+ special_data_up <= special_data_up;
+ read_structure_finished_out_i <= '0';
+ end if;
+ end if;
+ end process SPECIAL_DATA_UP_CNTR_PROC;
+
+ SELECT_FIFO_TO_READ: for i in 0 to 25 generate
+ SPECIAL_DATA_UP_CNTR_PROC : process (LOCAL_CLK, RESET)
+ begin
+ if rising_edge(LOCAL_CLK) then
+ if RESET = '1' or fifo_cntr = HOW_MANY_HISTOGRAMS then
+ start_data_rd_en(i) <= '0';
+ elsif structure_finished = '1' and fifo_cntr = i then
+ start_data_rd_en(i) <= READ_STRUCTURE_IN;
+ else
+ start_data_rd_en(i) <= '0';
+ end if;
+ end if;
+ end process SPECIAL_DATA_UP_CNTR_PROC;
+ end generate SELECT_FIFO_TO_READ;
+end cts_beam_structure;
+
+
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity cts_cal_screset_gen is
+ port
+ (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ GLOBAL_INHIBIT_IN : in std_logic;
+ -- gen
+ GEN_FREQ_IN : in std_logic_vector(27 downto 0);
+ GEN_OUT : out std_logic;
+ -- scalers reset
+ SCALER_RESET_OUT : out std_logic;
+ --mdc cal
+ MDC_CAL_ENABLE_IN : in std_logic;
+ --shower cal
+ SHOWER_PED_DISABLE_IN : in std_logic; --in each spill off
+ SHOWER_PED_UPDATE_IN : in std_logic;
+ SHOWER_CAL_ENABLE_IN : in std_logic;
+ --special trigger "e"
+ CAL_DEBUG_ENABLE_IN : in std_logic;
+ --cal out
+ CAL_INHIBIT_OUT : out std_logic;
+ CAL_TRIGGERS_OUT : out std_logic;
+ CAL_CODE_OUT : out std_logic_vector;
+ --beam
+ BEAM_OFF_IN : in std_logic;
+ --debug
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
+end cts_cal_screset_gen;
+
+architecture cts_cal_screset_gen of cts_cal_screset_gen is
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ signal mdc_cal_mark, shower_cal_mark, shower_ped_mark,debug_cal_mark : std_logic:='0';
+ signal gen_cntr : std_logic_vector(31 downto 0):=(others => '0');
+ signal reg_freq : integer range 0 to 15 :=15;
+ signal freq_save : std_logic_vector(3 downto 0):=(others => '0');
+ signal count : std_logic;
+ signal one_second_reset,one_second_cntr_reset : std_logic:='0';
+ signal one_second_cntr : std_logic_vector(27 downto 0):=(others => '0');
+ signal cal_trigger_out_i, cal_trigger_out_fsm, cal_inhibit_out_i, cal_inhibit_out_fsm : std_logic:='0';
+ signal cal_code_out_i, cal_code_out_fsm : std_logic_vector(3 downto 0):=x"0";
+--signal one_day_reset : std_logic:='0';
+--signal one_day_cntr : std_logic_vector(16 downto 0):=(others => '0');
+ signal beam_off_pulse,shower_ped_reg_start : std_logic;
+ type SEND_CAL is (IDLE, SEND_CAL_WAIT_1, SEND_CAL_WAIT_2, SEND_CAL_MDC, SEND_CAL_SHOWER, SEND_PED_SHOWER, SEND_CAL_DEBUG);
+ signal SEND_CAL_CURRENT, SEND_CAL_NEXT : SEND_CAL;
+ signal cal_wait_up, cal_wait_up_fsm, cal_wait_clr, cal_wait_clr_fsm : std_logic;
+ signal cal_wait_cntr : std_logic_vector(3 downto 0);
+
+ --lvl1 self trigger
+ signal lvl1_self_trigger : std_logic;
+ signal self_trigg_cntr : std_logic_vector(27 downto 0):=x"0000000";
+
+
+begin
+
+
+-----------------------------------------------------------------------------
+-- LVL1 self trigger
+-----------------------------------------------------------------------------
+ LVL1_SELF_TRIGGER_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 28)
+ port map (
+ CLK => CLK,
+ RESET => lvl1_self_trigger,
+ COUNT_OUT => self_trigg_cntr,
+ UP_IN => '1',
+ DOWN_IN => '0');
+
+ SET_LVL1_SELF_TRIGGER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or GEN_FREQ_IN = 0 then
+ lvl1_self_trigger <= '0';
+ elsif self_trigg_cntr = GEN_FREQ_IN then
+ lvl1_self_trigger <= '1';
+ else
+ lvl1_self_trigger <= '0';
+ end if;
+ end if;
+ end process SET_LVL1_SELF_TRIGGER;
+
+ GEN_OUT_PULSE: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl1_self_trigger,
+ pulse => GEN_OUT);
+
+-- GEN_OUT <= lvl1_self_trigger;
+
+
+--send generator trigger
+
+-- FREQ_CNTR : process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- gen_cntr <= gen_cntr + 1;
+-- freq_save <= GEN_FREQ_IN;
+-- reg_freq <= conv_integer(freq_save);
+-- count <= gen_cntr(6+reg_freq); --no_sim--
+--sikkkm-- count <= gen_cntr(1+reg_freq);
+-- end if;
+-- end process FREQ_CNTR;
+
+-- GEN_OUT_PULSE: edge_to_pulse
+-- port map (
+-- clock => CLK,
+-- en_clk => '1',
+-- signal_in => count,
+-- pulse => GEN_OUT);
+
+--reset for each one sec for scalers and mdc cal
+one_second_cntr_reset <= RESET or one_second_reset;
+ ONE_SECOND_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 28)
+ port map (
+ CLK => CLK,
+ RESET => one_second_cntr_reset,
+ COUNT_OUT => one_second_cntr,
+ UP_IN => '1',
+ DOWN_IN => '0');
+
+ SET_RESET_ONE_SECOND : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ one_second_reset <= '0';
+-- elsif one_second_cntr = x"5F5E100" then --no_sim--
+ elsif one_second_cntr = x"BEBC200" then --no_sim--
+--sim-- elsif one_second_cntr = x"0010fff" then
+ one_second_reset <= '1';
+ else
+ one_second_reset <= '0';
+ end if;
+ end if;
+ end process SET_RESET_ONE_SECOND;
+--sim-- SCALER_RESET_OUT <= one_second_reset or RESET;
+ SCALER_RESET_OUT <= one_second_reset; --no_sim--
+
+
+--mdc calibration trigger each second (with mdc trigger all scalers are send)
+
+ SET_MDC_CAL_MARK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if one_second_reset = '1' and MDC_CAL_ENABLE_IN = '1' then
+ mdc_cal_mark <= '1';
+ elsif SEND_CAL_CURRENT = SEND_CAL_MDC or RESET = '1' then
+ mdc_cal_mark <= '0';
+ end if;
+ end if;
+ end process SET_MDC_CAL_MARK;
+
+
+--debug trigger
+ SET_MDC_DEBUG_MARK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if one_second_reset = '1' and CAL_DEBUG_ENABLE_IN = '1' then
+ debug_cal_mark <= '1';
+ elsif SEND_CAL_CURRENT = SEND_CAL_DEBUG or RESET = '1' then
+ debug_cal_mark <= '0';
+ end if;
+ end if;
+ end process SET_MDC_DEBUG_MARK;
+
+--shower callibration mode
+ --pedestals
+ GEN_BEAM_OFF_PULSE: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => BEAM_OFF_IN,
+ pulse => beam_off_pulse);
+
+ shower_ped_reg_start <= SHOWER_PED_UPDATE_IN;
+
+ SET_SHOWER_PED_MARK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if SEND_CAL_CURRENT = SEND_PED_SHOWER or reset = '1' then
+ shower_ped_mark <= '0';
+ elsif (shower_ped_reg_start = '1' or beam_off_pulse = '1') and SHOWER_PED_DISABLE_IN = '0' then
+ shower_ped_mark <= '1';
+ end if;
+ end if;
+ end process SET_SHOWER_PED_MARK;
+ --cal
+ SET_SHOWER_CAL_MARK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if SEND_CAL_CURRENT = SEND_CAL_SHOWER or reset = '1' then
+ shower_cal_mark <= '0';
+ elsif SHOWER_CAL_ENABLE_IN = '1' then
+ shower_cal_mark <= '1';
+ end if;
+ end if;
+ end process SET_SHOWER_CAL_MARK;
+
+--cal out
+
+ CAL_WAIT_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 4)
+ port map (
+ CLK => CLK,
+ RESET => cal_wait_clr,
+ COUNT_OUT => cal_wait_cntr,
+ UP_IN => cal_wait_up,
+ DOWN_IN => '0');
+
+ SEND_CAL_CLK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ SEND_CAL_CURRENT <= IDLE;
+ cal_inhibit_out_i <= '0';
+ cal_trigger_out_i <= '0';
+ cal_code_out_i <= x"9";
+ cal_wait_up <= '0';
+ cal_wait_clr <= '1';
+ else
+ SEND_CAL_CURRENT <= SEND_CAL_NEXT;
+ cal_inhibit_out_i <= cal_inhibit_out_fsm;
+ cal_trigger_out_i <= cal_trigger_out_fsm;
+ cal_code_out_i <= cal_code_out_fsm;
+ cal_wait_up <= cal_wait_up_fsm;
+ cal_wait_clr <= cal_wait_clr_fsm;
+ end if;
+ end if;
+ end process SEND_CAL_CLK;
+
+ CAL_INHIBIT_OUT <= cal_inhibit_out_i;
+ CAL_TRIGGERS_OUT <= cal_trigger_out_i;
+ CAL_CODE_OUT <= cal_code_out_i;
+
+ SEND_CAL_PROC : process (CLK)
+ begin
+
+ cal_inhibit_out_fsm <= '1';
+ cal_trigger_out_fsm <= '0';
+ cal_code_out_fsm <= x"8";
+ cal_wait_clr_fsm <= '1';
+ cal_wait_up_fsm <= '0';
+
+ case (SEND_CAL_CURRENT) is
+
+ when IDLE =>
+ cal_inhibit_out_fsm <= '0';
+ if mdc_cal_mark = '1' or shower_ped_mark = '1' or shower_cal_mark = '1' or debug_cal_mark = '1' then
+ SEND_CAL_NEXT <= SEND_CAL_WAIT_1;
+ else
+ SEND_CAL_NEXT <= IDLE;
+ end if;
+ when SEND_CAL_WAIT_1 => --wait additional time in case phys
+ --trigger was accepted
+ cal_wait_up_fsm <= '1';
+ cal_wait_clr_fsm <= '0';
+ if cal_wait_cntr = x"a" then
+ SEND_CAL_NEXT <= SEND_CAL_WAIT_2;
+ else
+ SEND_CAL_NEXT <= SEND_CAL_WAIT_1;
+ end if;
+ when SEND_CAL_WAIT_2 =>
+ if GLOBAL_INHIBIT_IN = '0' and mdc_cal_mark = '1' then
+ SEND_CAL_NEXT <= SEND_CAL_MDC;
+ elsif GLOBAL_INHIBIT_IN = '0' and shower_ped_mark = '1' then
+ SEND_CAL_NEXT <= SEND_PED_SHOWER;
+ elsif GLOBAL_INHIBIT_IN = '0' and shower_cal_mark = '1' then
+ SEND_CAL_NEXT <= SEND_CAL_SHOWER;
+ elsif GLOBAL_INHIBIT_IN = '0' and debug_cal_mark = '1' then
+ SEND_CAL_NEXT <= SEND_CAL_DEBUG;
+ else
+ SEND_CAL_NEXT <= SEND_CAL_WAIT_2;
+ end if;
+
+ when SEND_CAL_MDC =>
+ cal_trigger_out_fsm <= '1';
+ cal_code_out_fsm <= x"9";
+ SEND_CAL_NEXT <= IDLE;
+
+ when SEND_CAL_SHOWER =>
+ cal_trigger_out_fsm <= '1';
+ cal_code_out_fsm <= x"a";
+ SEND_CAL_NEXT <= IDLE;
+
+ when SEND_PED_SHOWER =>
+ cal_trigger_out_fsm <= '1';
+ cal_code_out_fsm <= x"b";
+ SEND_CAL_NEXT <= IDLE;
+
+ when SEND_CAL_DEBUG =>
+ cal_trigger_out_fsm <= '1';
+ cal_code_out_fsm <= x"e";
+ SEND_CAL_NEXT <= IDLE;
+
+ when others =>
+ SEND_CAL_NEXT <= IDLE;
+
+ end case;
+ end process SEND_CAL_PROC;
+
+end cts_cal_screset_gen;
+
+
+-- ONE_DAY_COUNTER: up_down_counter
+-- generic map (
+-- NUMBER_OF_BITS => 17)
+-- port map (
+-- CLK => CLK,
+-- RESET => one_day_reset,
+-- COUNT_OUT => one_day_cntr,
+-- UP_IN => one_second_reset,
+-- DOWN_IN => '0');
+
+-- SET_RESET_ONE_DAY : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- one_day_reset <= '1';
+-- elsif one_day_cntr = x"15180" then --one day 24*3600
+-- one_day_reset <= '1';
+-- else
+-- one_day_reset <= '0';
+-- end if;
+-- end if;
+-- end process SET_RESET_ONE_DAY;
--- /dev/null
+
+library ieee;
+use ieee.std_logic_1164.all;
+USE IEEE.numeric_std.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+library work;
+
+package cts_components is
+
+-- component pll_in200_out100
+-- generic (
+-- SMI_OFFSET : in String);
+-- port (
+-- clk : in std_logic;
+-- clkop : out std_logic;
+-- clkos : out std_logic;
+-- lock : out std_logic);
+-- end component;
+
+-- component trb_net_reset_handler
+-- generic (
+-- RESET_DELAY : std_logic_vector(15 downto 0));
+-- port (
+-- CLEAR_IN : in std_logic;
+-- CLEAR_N_IN : in std_logic;
+-- CLK_IN : in std_logic;
+-- SYSCLK_IN : in std_logic;
+-- PLL_LOCKED_IN : in std_logic;
+-- RESET_IN : in std_logic;
+-- TRB_RESET_IN : in std_logic;
+-- CLEAR_OUT : out std_logic;
+-- RESET_OUT : out std_logic;
+-- DEBUG_OUT : out std_logic_vector(15 downto 0));
+-- end component;
+
+ component pll_in200_out400
+
+ port (
+ clk : in std_logic;
+ clkop : out std_logic;
+ clkos : out std_logic;
+ lock : out std_logic);
+ end component;
+
+ component ddr2_busses
+ generic (
+ TRIGGER_INPUTS_NUMBER : natural);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ EDGE_CLK : in std_logic;
+ TRIG_IN : in std_logic_vector(63 downto 0);
+ TRIG_OUT : out std_logic_vector(TRIGGER_INPUTS_NUMBER*4-1 downto 0);
+ FAST_LVDS_TIMING_IN : in std_logic_vector(3 downto 0);
+ FAST_PECL_TIMING_IN : in std_logic_vector(3 downto 0);
+ FAST_MDCA_TIMING_IN : in std_logic_vector(3 downto 0);
+ FAST_MDCB_TIMING_IN : in std_logic_vector(3 downto 0);
+ MULTIPLEXER_IN : in std_logic_vector(7 downto 0);
+ LVDS_TIMING_OUT : out std_logic_vector(11 downto 0);
+ PECL_TIMING_OUT : out std_logic_vector(2 downto 0);
+ START_VETO_STRUCTURE_OUT : out std_logic_vector(23 downto 0);
+ TRIG_CNTRL_IN : in std_logic_vector(7 downto 0)
+ );
+ end component;
+
+ component dll_in400_out200
+ port (
+ clk : in std_logic;
+ aluhold : in std_logic;
+ clkop : out std_logic;
+ clkos : out std_logic;
+ lock : out std_logic);
+ end component;
+
+ component dll_in400_out100
+ port (
+ clk : in std_logic;
+ aluhold : in std_logic;
+ clkop : out std_logic;
+ clkos : out std_logic;
+ lock : out std_logic);
+ end component;
+
+ component pll_in200_out200
+ port (
+ clk : in std_logic;
+ clkop : out std_logic;
+ clkos : out std_logic;
+ lock : out std_logic);
+ end component;
+
+ component pll_in200_out40
+ port (
+ clk : in std_logic;
+ clkop : out std_logic;
+ clkos : out std_logic;
+ lock : out std_logic);
+ end component;
+
+ component cts_beam_structure
+ generic (
+ START_SAMPLE_NUMBER : natural;
+ HOW_MANY_HISTOGRAMS : natural
+ );
+ port (
+ RESET : in std_logic;
+ TRIGGER_CLK : in std_logic;
+ LOCAL_CLK : in std_logic;
+ START_TIME_OFFSET_IN : in std_logic_vector(31 downto 0);
+ START_TIME_SAMPLE_IN : in std_logic_vector(31 downto 0);
+ START_BEAM_IN : in std_logic;
+ BEAM_INHIBIT_LENGTH_IN : in std_logic_vector(31 downto 0);
+ BEAM_INHIBIT_OUT : out std_logic;
+ BEAM_STRUCTURE_SIGNAL_IN : in std_logic_vector(1 downto 0);
+ BEAM_START_VETO_STRUCKTURE_IN : in std_logic_vector(25 downto 0);
+ STRUCTURE_DATA_OUT : out std_logic_vector(31 downto 0);
+ READ_STRUCTURE_IN : in std_logic;
+ READ_STRUCTURE_FINISHED_OUT : out std_logic;
+ READ_STRUCTURE_START_IN : in std_logic;
+ CTS_BEAM_STRUCTURE_DEBUG : out std_logic_vector(15 downto 0));
+ end component;
+
+ component cts_simple_data_transport
+ generic (
+ UP_WIDTH : natural;
+ DOWN_WIDTH : natural;
+ UP_RW_REGISTERS_NUMBER : natural;
+ UP_R_REGISTERS_NUMBER : natural;
+ UP_SPECIAL_REGISTERS_NUMBER : natural;
+ DOWN_RW_REGISTERS_NUMBER : natural;
+ DOWN_R_REGISTERS_NUMBER : natural;
+ DOWN_SPECIAL_REGISTERS_NUMBER : natural;
+ UP_CLK_SELECT : natural;
+ FPGA_TYPE : natural);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ DOWN_RW_REGISTER_OUT : out std_logic_vector(DOWN_RW_REGISTERS_NUMBER*32-1 downto 0);
+ DOWN_R_REGISTER_OUT : out std_logic_vector(DOWN_R_REGISTERS_NUMBER*32-1 downto 0);
+ DOWN_SPECIAL_REGISTER_OUT : out std_logic_vector(DOWN_SPECIAL_REGISTERS_NUMBER*32-1 downto 0);
+ DOWN_CLK_IN : in std_logic;
+ DOWN_DATA_IN : in std_logic_vector(DOWN_WIDTH - 1 downto 0);
+ DOWN_DATA_VALID_IN : in std_logic;
+ DOWN_ADDRESS_OUT : out std_logic_vector(7 downto 0);
+ DOWN_DATA_VALID_OUT : out std_logic;
+ DOWN_DATA_OUT : out std_logic_vector(31 downto 0);
+ UP_RW_REGISTER_IN : in std_logic_vector(UP_RW_REGISTERS_NUMBER*32-1 downto 0);
+ UP_R_REGISTER_IN : in std_logic_vector(UP_R_REGISTERS_NUMBER*32-1 downto 0);
+ UP_SPECIAL_REGISTER_IN : in std_logic_vector(UP_SPECIAL_REGISTERS_NUMBER*32-1 downto 0);
+ UP_SPECIAL_REGISTER_FINISHED_IN : in std_logic_vector(UP_SPECIAL_REGISTERS_NUMBER-1 downto 0);
+ UP_START_READ_STRUCTURE_OUT : out std_logic_vector(UP_SPECIAL_REGISTERS_NUMBER-1 downto 0);
+ UP_RD_EN_STRUCTURE_OUT : out std_logic_vector(UP_SPECIAL_REGISTERS_NUMBER-1 downto 0);
+ UP_CLK_OUT : out std_logic;
+ UP_CLK_IN : in std_logic;
+ UP_DATA_OUT : out std_logic_vector(UP_WIDTH - 1 downto 0);
+ UP_DATA_VALID_OUT : out std_logic;
+ RW_ADDRESS_OUT : out std_logic_vector(31 downto 0);
+ RW_DATA_OUT : out std_logic_vector(31 downto 0);
+ RW_DATA_VALID_OUT : out std_logic
+ );
+ end component;
+
+ component cts_fpga1_to_fpga2
+ generic (
+ LVL1_SIZE_OF_DATA_BUS_OUT : natural;
+ LVL2_SIZE_OF_DATA_BUS_OUT : natural);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ SLOW_CLK_OUT : out std_logic;
+ DATA_IN : in std_logic_vector(31 downto 0);
+ LVL1_CTS_DATA_ACK_OUT : out std_logic;
+ LVL1_DATA_VALID_IN : in std_logic;
+ LVL1_FINISHED_IN : in std_logic;
+ LVL1_TRIGGER_TAG_IN : in std_logic_vector(15 downto 0);
+ LVL1_RND_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_CODE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRIGGER_IN : in std_logic;
+ LVL1_TRIGGER_OUT : out std_logic;
+ LVL1_DATA_OUT : out std_logic_vector(LVL1_SIZE_OF_DATA_BUS_OUT - 1 downto 0);
+ LVL1_DATA_VALID_OUT : out std_logic;
+ LVL2_TRIGGER_TAG_IN : in std_logic_vector(15 downto 0);
+ LVL2_RND_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL2_CODE_IN : in std_logic_vector(3 downto 0);
+ LVL2_TRIGGER_IN : in std_logic;
+ LVL2_TRIGGER_OUT : out std_logic;
+ LVL2_DATA_OUT : out std_logic_vector(LVL2_SIZE_OF_DATA_BUS_OUT - 1 downto 0);
+ LVL2_DATA_VALID_OUT : out std_logic;
+ IP_TABLE_IN : in std_logic_vector(15 downto 0);
+ EVENTS_NUMBER_IN : in std_logic_vector(23 downto 0);
+ LVL1_INFO_IN : in std_logic_vector(15 downto 0);
+ CTS_FPGA1_TO_FPGA2_DEBUG_OUT : out std_logic_vector(31 downto 0));
+ end component;
+
+ component cts_trigger_logic
+ generic (
+ TRIGGER_INPUTS_NUMBER : natural;
+ TRIGGER_OUTPUTS_NUMBER : natural;
+ CTS_NUMBER_IPU_DATA : natural;
+ SCALERS_NUMBER : natural;
+ VECTOR_WIDTH : natural;
+ CTS_MODE : natural;
+ RATE_MARKERS_NUMBER : natural
+ );
+ port (
+ CLK : in std_logic;
+ HIGH_FREQ_CLK : in std_logic;
+ CLK_100 : in std_logic;
+ RESET : in std_logic;
+ EMERGENCY_STOP : in std_logic;
+ TRIGGER_IN : in std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ INPUT_ENABLE_IN : in std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ DOWNSCALE_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
+ DELAY_TRIGGER_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
+ DELAY_LARGE_TRIGGER_REGISTER_IN : in std_logic_vector((8*(12)-1) downto 0);
+ WIDTH_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER+9)-1) downto 0);
+ WIDTH_REGISTER_LARGE_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER+9)-1) downto 0);
+ TS_GATING_DISABLE_IN : in std_logic_vector((TRIGGER_INPUTS_NUMBER-1) downto 0);
+ TRIGGER_OUT_EN_IN : in std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ MULTIPLEXER_SELECT_IN : in std_logic_vector(27 downto 0);
+ MULTIPLEXER_OUT : out std_logic_vector(7 downto 0);
+ SCALER_OUT : out std_logic_vector(SCALERS_NUMBER*32-1 downto 0);
+ SCALERS_FINISHED_IN : in std_logic;
+ SEND_SCALERS_OUT : out std_logic;
+ BEAM_INHIBIT_IN : in std_logic;
+ BEAM_START : in std_logic;
+ NO_TIMING_OUT : out std_logic;
+ LVL1_LOCAL_BUSY_IN : in std_logic;
+ LVL1_TRBNET_BUSY_IN : in std_logic;
+ LVL1_TRIGGER_ACCEPTED_IN : in std_logic;
+ LVL1_TRIGGER_CODE_OUT : out std_logic_vector(3 downto 0);
+ LVL1_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL1_RND_NUMBER_OUT : out std_logic_vector(7 downto 0);
+ LVL1_TRIGGER_OUT : out std_logic;
+ LVL1_BUSY_OUT : out std_logic;
+ LVL2_TRBNET_BUSY_IN : in std_logic;
+ LVL2_LOCAL_BUSY_IN : in std_logic;
+ LVL2_TRIGGER_OUT : out std_logic;
+ LVL2_TRIGGER_CODE_OUT : out std_logic_vector(3 downto 0);
+ LVL2_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL2_RND_NUMBER_OUT : out std_logic_vector(7 downto 0);
+ TRIGBOX_LVL1_TRIGGER_INFO_OUT : out std_logic_vector(3 downto 0);
+ TOKEN_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ DATA_VALID_OUT : out std_logic;
+ TOKEN_OUT : out std_logic;
+ SAVE_SCALERS_OUT : out std_logic;
+ SAVED_SCALERS_IN : in std_logic_vector(SCALERS_NUMBER*32 -1 downto 0);
+ FAST_TRIGGER_OUT_LVDS : out std_logic_vector(3 downto 0);
+ FAST_TRIGGER_OUT_PECL : out std_logic_vector(3 downto 0);
+ MDCA_TRIGGER_OUT : out std_logic_vector(3 downto 0);
+ MDCB_TRIGGER_OUT : out std_logic_vector(3 downto 0);
+
+ HIGH_RATE_MARKERS_OUT : out std_logic_vector(RATE_MARKERS_NUMBER - 1 downto 0);
+ LOW_RATE_MARKERS_OUT : out std_logic_vector(RATE_MARKERS_NUMBER - 1 downto 0);
+ HIGH_RATE_THRESHOLD_IN : in std_logic_vector(7 downto 0);
+ LOW_RATE_THRESHOLD_IN : in std_logic_vector(7 downto 0);
+ BEAM_STRUCTURE_OUT : out std_logic_vector(1 downto 0);
+ TRIGGER_POLARITY : out std_logic_vector(TRIGGER_INPUTS_NUMBER - 1 downto 0);
+ TRIGGER_LOGIC_CTRL_IN_0 : in std_logic_vector(31 downto 0);
+ TRIGGER_LOGIC_CTRL_IN_1 : in std_logic_vector(31 downto 0);
+ TRIGGER_LOGIC_CTRL_IN_2 : in std_logic_vector(31 downto 0);
+ TRIGGER_LOGIC_DEBUG_OUT_0 : out std_logic_vector(31 downto 0);
+ TRIGGER_LOGIC_DEBUG_OUT_1 : out std_logic_vector(31 downto 0);
+ TRIGGER_LOGIC_DEBUG_OUT_2 : out std_logic_vector(4 downto 0));
+ end component;
+
+ component trigger_buffer
+ port (
+ RESET : in std_logic;
+ HIGH_FREQ_CLK : in std_logic;
+ CLK : in std_logic;
+ CLK40_IN : in std_logic;
+ LVL1_TIMING_TRIGGER_OUT : out std_logic;
+ LVL1_APV_TRIGGER_OUT : out std_logic;
+ LVL1_TRIGBOX_TRIGGER_IN : in std_logic;
+ LVL1_TRIGBOX_TRIGGER_CODE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRIGBOX_BUSY_IN : in std_logic;
+ LVL1_LOCAL_BUSY_IN : in std_logic;
+ LVL1_TRBNET_BUSY_IN : in std_logic;
+ LVL1_TRIGGER_BUFFER_BUSY_OUT : out std_logic;
+ LVL1_TRIGGER_OUT : out std_logic;
+ LVL1_TRIGGER_CODE_OUT : out std_logic_vector(3 downto 0);
+ LVL1_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL1_RND_NUMBER_OUT : out std_logic_vector(7 downto 0);
+ LVL1_TRIGGER_INFO_OUT : out std_logic_vector(31 downto 0);
+ LVL2_LOCAL_TRIGGER_IN : in std_logic;
+ LVL2_LOCAL_TRIGGER_CODE_IN : in std_logic_vector(3 downto 0);
+ LVL2_LOCAL_TRIGGER_TAG_IN : in std_logic_vector(15 downto 0);
+ LVL2_LOCAL_BUSY_IN : in std_logic;
+ LVL2_TRBNET_BUSY_IN : in std_logic;
+ LVL2_TRIGGER_BUFFER_BUSY_OUT : out std_logic;
+ LVL2_TRIGGER_OUT : out std_logic;
+ LVL2_TRIGGER_CODE_OUT : out std_logic_vector(3 downto 0);
+ LVL2_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL2_RND_NUMBER_OUT : out std_logic_vector(7 downto 0);
+ LVL2_TRIGGER_INFO_OUT : out std_logic_vector(31 downto 0);
+ TRIGGER_BUFFER_STASUS_0UT_0 : out std_logic_vector(31 downto 0);
+ TRIGGER_BUFFER_STASUS_0UT_1 : out std_logic_vector(31 downto 0);
+ TRIGGER_BUFFER_STASUS_0UT_2 : out std_logic_vector(31 downto 0);
+ TRIGGER_BUFFER_CTRL_IN_0 : in std_logic_vector(31 downto 0);
+ TRIGGER_BUFFER_CTRL_IN_1 : in std_logic_vector(31 downto 0)
+ );
+end component;
+
+component cts_readout
+ generic (
+ CTS_TYPE : natural
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DATA_READY_IN : in std_logic;
+ DATA_IN : in std_logic_vector (31 downto 0);
+ SEND_DATA_TOKEN_OUT : out std_logic;
+ RECEIVED_DATA_TOKEN_IN : in std_logic;
+ LVL1_BUSY_OUT : out std_logic;
+ LVL1_TRBNET_TRIGGER_IN : in std_logic;
+ LVL1_TAG_IN : in std_logic_vector(15 downto 0);
+ LVL1_CODE_IN : in std_logic_vector(3 downto 0);
+ LVL1_FINISHED_OUT : out std_logic;
+ LVL2_TRIGGER_IN : in std_logic;
+ LVL2_FINISHED_OUT : out std_logic;
+ LVL2_BUSY_OUT : out std_logic;
+ IPU_READY_IN : in std_logic;
+ IPU_DATAREADY_OUT : out std_logic;
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0);
+ DEBUG_REGISTER_00 : out std_logic_vector(31 downto 0);
+ DEBUG_REGISTER_01 : out std_logic_vector(31 downto 0);
+ DEBUG_REGISTER_02 : out std_logic_vector(31 downto 0);
+ DATA_VERSION : in std_logic_vector(7 downto 0));
+end component;
+
+component etrax_reg
+ generic (
+ RW_REGISTERS_NUMBER : natural;
+ R_REGISTERS_NUMBER : natural);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ ETRAX_DATA_BUS_E : inout std_logic_vector(9 downto 8);
+ RW_REGISTER : out std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
+ R_REGISTER : in std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
+ REGIO_READ_ENABLE_IN : in std_logic;
+ REGIO_WRITE_ENABLE_IN : in std_logic;
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0);
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
+ REGIO_DATAREADY_OUT : out std_logic;
+ REGIO_NO_MORE_DATA_OUT : out std_logic;
+ REGIO_WRITE_ACK_OUT : out std_logic;
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_REGISTER_OO : out std_logic_vector(31 downto 0));
+end component;
+
+component etrax_reg_mem
+ generic (
+ RW_REGISTERS_NUMBER : natural;
+ R_REGISTERS_NUMBER : natural;
+ SCALERS_NUMBER : natural;
+ ENABLE_ETRAX_RW_INTERFACE : natural);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ ETRAX_DATA_BUS_E : inout std_logic_vector(9 downto 8);
+ RW_REGISTER_OUT : out std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
+ R_REGISTER_IN : in std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+ R_REGISTER_OUT : out std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+ R_REGISTER_IN_SAVE_1S_IN : in std_logic;
+ SAVED_SCALERS_OUT : out std_logic_vector(SCALERS_NUMBER*32 -1 downto 0);
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
+ REGIO_READ_ENABLE_IN : in std_logic;
+ REGIO_WRITE_ENABLE_IN : in std_logic;
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0);
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
+ REGIO_DATAREADY_OUT : out std_logic;
+ REGIO_NO_MORE_DATA_OUT : out std_logic;
+ REGIO_WRITE_ACK_OUT : out std_logic;
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_REGISTER_OO : out std_logic_vector(31 downto 0));
+end component;
+
+component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+end component;
+
+component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+end component;
+
+
+
+
+end package;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use work.version.all;
+use ieee.std_logic_arith.all;
+
+
+
+entity cts_delay is
+ generic (
+ VECTOR_WIDTH : natural
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ DELAY_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ DELAY_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ DELAY_VALUE_IN : in std_logic_vector(3 downto 0)
+ );
+end cts_delay;
+
+architecture cts_delay of cts_delay is
+
+ signal signal_memory : std_logic_vector(23 downto 0);
+ type signal_out_array_type is array (0 to 2) of std_logic_vector(23 downto 0);
+ signal signal_out_array : signal_out_array_type;
+ signal delayed_signal : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ signal reg_delay : integer range 0 to 31 :=0;
+ constant zero_signal : std_logic_vector(6 downto 0) := "0000000";
+begin
+
+ CONVERT_DELAY_TO_INTEGER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reg_delay <= 0;
+ else
+ reg_delay <= conv_integer(DELAY_VALUE_IN(3 downto 0));
+ end if;
+ end if;
+ end process CONVERT_DELAY_TO_INTEGER;
+
+-- SAVE_SIGNALS : process (CLK)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- signal_memory <= (others => '0');
+-- else
+-- signal_memory(VECTOR_WIDTH - 1 +reg_delay downto 0+reg_delay) <= DELAY_VECTOR_IN;
+-- end if;
+-- end if;
+-- end process SAVE_SIGNALS;
+
+ MAKE_OUT_SIGNAL : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+-- signal_out_array(0) <= signal_memory;
+ if RESET = '1' then
+ signal_out_array(0) <= (others => '0');
+ else
+ signal_out_array(0)(VECTOR_WIDTH - 1 +reg_delay downto 0+reg_delay) <= DELAY_VECTOR_IN;
+ signal_out_array(1) <= signal_out_array(0);
+ signal_out_array(2) <= signal_out_array(1);
+ end if;
+ end if;
+ end process MAKE_OUT_SIGNAL;
+
+ SEND_DELAYED_SIGNAL : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ DELAY_VECTOR_OUT <= signal_out_array(0)(VECTOR_WIDTH - 1 downto 0) or signal_out_array(1)(VECTOR_WIDTH*2-1 downto VECTOR_WIDTH) or signal_out_array(2)(VECTOR_WIDTH*3-1 downto VECTOR_WIDTH*2);
+ end if;
+ end process SEND_DELAYED_SIGNAL;
+
+end cts_delay;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use work.version.all;
+use ieee.std_logic_arith.all;
+
+entity cts_delay_large is
+
+ generic (
+ VECTOR_WIDTH : integer range 1 to 32
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ DELAY_IN : in std_logic_vector(7 downto 0);
+ DELAY_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ DELAY_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0)
+ );
+end cts_delay_large;
+
+architecture cts_delay_large of cts_delay_large is
+ component delay_fifo
+ port (
+ Data : in std_logic_vector(31 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ WCNT : out std_logic_vector(7 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+ end component;
+
+ signal delay_vector_out_i : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ signal delay_saved : std_logic_vector(7 downto 0);
+ signal reset_fifo : std_logic;
+
+ --fifo
+ signal data : std_logic_vector(31 downto 0);
+ signal clock : std_logic;
+ signal wren : std_logic;
+ signal rden : std_logic;
+ signal q : std_logic_vector(31 downto 0);
+ signal wcnt : std_logic_vector(7 downto 0);
+ signal empty : std_logic;
+ signal full : std_logic;
+
+begin
+
+ DELAY_VECTOR_OUT <= delay_vector_out_i;
+
+ data(VECTOR_WIDTH - 1 downto 0) <= DELAY_VECTOR_IN;
+
+ delay_fifo_1: delay_fifo
+ port map (
+ DATA => data,
+ CLOCK => CLK,
+ WREN => wren,
+ RDEN => rden,
+ RESET => reset_fifo,
+ Q => q,
+ WCNT => wcnt,
+ EMPTY => empty,
+ FULL => full);
+
+ DELAY_SAVE : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ delay_saved <= x"00";
+ else
+ delay_saved <= DELAY_IN;
+ end if;
+ end if;
+ end process DELAY_SAVE;
+
+ FIFO_RESET_PROC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reset_fifo <= '1';
+ wren <= '0';
+ elsif DELAY_IN /= delay_saved then
+ reset_fifo <= '1';
+ wren <= '0';
+ else
+ reset_fifo <= '0';
+ wren <= '1';
+ end if;
+ end if;
+ end process FIFO_RESET_PROC;
+
+-- SIGNAL_OUT : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- delay_vector_out_i <= (others => '0');
+-- else
+ delay_vector_out_i <= q(VECTOR_WIDTH - 1 downto 0);
+-- end if;
+-- end if;
+-- end process SIGNAL_OUT;
+
+ COUNT_FOR_DELAY : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or reset_fifo = '1' then
+ rden <= '0';
+ elsif (wcnt < DELAY_IN -1) and DELAY_IN > 0 then
+ rden <= '0';
+ else
+ rden <= '1';
+ end if;
+ end if;
+ end process COUNT_FOR_DELAY;
+
+end cts_delay_large;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use work.version.all;
+
+use ieee.std_logic_arith.all;
+
+
+entity cts_downscale is
+ generic (
+ VECTOR_WIDTH : natural
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DOWNSCALE_VALUE_IN : in std_logic_vector(3 downto 0);
+ DOWNSCALE_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ DOWNSCALE_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0)
+ );
+end cts_downscale;
+
+architecture cts_downscale of cts_downscale is
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ signal downscale_vector_in_a, downscale_vector_in_b,downscale_vector_in_c,downscale_vector_in_d : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ signal downscale_cntr : std_logic_vector(15 downto 0);
+ signal internal_signal : std_logic;
+ signal downscaled : std_logic;
+ signal case_out,internal : std_logic;
+begin
+
+ MAKE_SIGNAL : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if DOWNSCALE_VECTOR_IN > 0 then
+ internal_signal <= '1';
+ else
+ internal_signal <= '0';
+ end if;
+ end if;
+ end process MAKE_SIGNAL;
+
+ DOWNSCALE_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 16)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ COUNT_OUT => downscale_cntr,
+ UP_IN => internal_signal,
+ DOWN_IN => '0');
+
+ MAKE_PULSE : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ case DOWNSCALE_VALUE_IN is
+ when "0000" => case_out <= internal_signal; --bypass
+ when "0001" => case_out <= downscale_cntr(0);
+ when "0010" => case_out <= downscale_cntr(1);
+ when "0011" => case_out <= downscale_cntr(2);
+ when "0100" => case_out <= downscale_cntr(3);
+ when "0101" => case_out <= downscale_cntr(4);
+ when "0110" => case_out <= downscale_cntr(5);
+ when "0111" => case_out <= downscale_cntr(6);
+ when "1000" => case_out <= downscale_cntr(7);
+ when "1001" => case_out <= downscale_cntr(8);
+ when "1010" => case_out <= downscale_cntr(9);
+ when "1011" => case_out <= downscale_cntr(10);
+ when "1100" => case_out <= downscale_cntr(11);
+ when "1101" => case_out <= downscale_cntr(12);
+ when "1110" => case_out <= downscale_cntr(13);
+ when "1111" => case_out <= downscale_cntr(14);
+ when others => case_out <= 'X';
+ end case;
+ internal <= case_out;
+-- downscaled <= (not internal) and case_out;
+ end if;
+ end process MAKE_PULSE;
+
+ MAKE_SYNC : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ downscale_vector_in_a <= DOWNSCALE_VECTOR_IN;
+ downscale_vector_in_b <= downscale_vector_in_a;
+ downscale_vector_in_c <= downscale_vector_in_b;
+ downscale_vector_in_d <= downscale_vector_in_c;
+ end if;
+ end process MAKE_SYNC;
+
+ SEND_DATA_OUT : process (CLK)
+ begin
+ if rising_edge(CLK) then
+-- if downscaled = '1' or DOWNSCALE_VALUE_IN = x"0" then
+ if (case_out = '1' and internal = '0') or DOWNSCALE_VALUE_IN = x"0" then
+-- DOWNSCALE_VECTOR_OUT <= downscale_vector_in_d;
+ DOWNSCALE_VECTOR_OUT <= downscale_vector_in_c;
+ else
+ DOWNSCALE_VECTOR_OUT <= (others => '0');
+ end if;
+ end if;
+ end process SEND_DATA_OUT;
+end cts_downscale;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+
+entity cts_eb_ip_switch is
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ LVL2_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL2_TRIGGER_IN : in std_logic;
+ IP_TABLE_IN : in std_logic_vector(15 downto 0);
+ NUMBER_OF_EVENTS_IN : in std_logic_vector(23 downto 0);
+ EB_IP_SWITCH_OUT : out std_logic_vector(3 downto 0);
+ EB_IP_SWITCH_STATUS_OUT : out std_logic_vector(3 downto 0)
+ );
+end cts_eb_ip_switch;
+
+architecture cts_eb_ip_switch of cts_eb_ip_switch is
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ signal ip_cntr : std_logic_vector(3 downto 0);
+ signal ip_cntr_up, ip_cntr_up_fsm : std_logic;
+ signal event_cntr : std_logic_vector(23 downto 0);
+ signal event_cntr_rst, event_cntr_rst_fsm : std_logic;
+ signal ip_cntr_integer : integer := 0;
+ signal cts_eb_switch_status_out_i, cts_eb_switch_status_out_fsm : std_logic_vector(3 downto 0);
+ type EVENT_IP_CHANGE is (START, EVENT_IP_CHANGE_0, EVENT_IP_CHANGE_1, EVENT_IP_CHANGE_2, EVENT_IP_CHANGE_3, EVENT_IP_CHANGE_4, EVENT_IP_CHANGE_5,
+ EVENT_IP_CHANGE_6, EVENT_IP_CHANGE_7, EVENT_IP_CHANGE_8, EVENT_IP_CHANGE_9, EVENT_IP_CHANGE_A, EVENT_IP_CHANGE_B,
+ EVENT_IP_CHANGE_C, EVENT_IP_CHANGE_D, EVENT_IP_CHANGE_E, EVENT_IP_CHANGE_F);
+ signal EVENT_IP_CHANGE_CURRENT, EVENT_IP_CHANGE_NEXT : EVENT_IP_CHANGE;
+begin
+
+ EVENT_COUNTER : up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 24)
+ port map (
+ CLK => CLK,
+ RESET => event_cntr_rst,
+ COUNT_OUT => event_cntr,
+ UP_IN => LVL2_TRIGGER_IN,
+ DOWN_IN => '0');
+
+ IP_COUNTER : up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 4)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ COUNT_OUT => ip_cntr,
+ UP_IN => ip_cntr_up,
+ DOWN_IN => '0');
+
+ EB_IP_SWITCH_OUT <= ip_cntr;
+
+ EVENT_IP_CHANGE_CLK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or IP_TABLE_IN = x"0000" or (event_cntr > NUMBER_OF_EVENTS_IN) then
+ EVENT_IP_CHANGE_CURRENT <= START;
+ ip_cntr_up <= '0';
+ event_cntr_rst <= '1';
+ ip_cntr_integer <= 0;
+ cts_eb_switch_status_out_i <= x"0";
+ else
+ EVENT_IP_CHANGE_CURRENT <= EVENT_IP_CHANGE_NEXT;
+ ip_cntr_up <= ip_cntr_up_fsm;
+ event_cntr_rst <= event_cntr_rst_fsm;
+ ip_cntr_integer <= conv_integer(ip_cntr(3 downto 0));
+ cts_eb_switch_status_out_i <= cts_eb_switch_status_out_fsm;
+ end if;
+ end if;
+ end process EVENT_IP_CHANGE_CLK;
+
+ EVENT_IP_CHANGE_PROC : process (CLK)
+ begin
+ ip_cntr_up_fsm <= '0';
+ event_cntr_rst_fsm <= '0';
+ cts_eb_switch_status_out_fsm <= x"0";
+
+ case (EVENT_IP_CHANGE_CURRENT) is
+
+ when START =>
+ cts_eb_switch_status_out_fsm <= x"1";
+ if IP_TABLE_IN(ip_cntr_integer) = '1' and NUMBER_OF_EVENTS_IN > 0 then
+ EVENT_IP_CHANGE_NEXT <= EVENT_IP_CHANGE_A;
+ else
+ EVENT_IP_CHANGE_NEXT <= EVENT_IP_CHANGE_B;
+ end if;
+
+ when EVENT_IP_CHANGE_A =>
+ cts_eb_switch_status_out_fsm <= x"2";
+ if event_cntr = NUMBER_OF_EVENTS_IN and NUMBER_OF_EVENTS_IN > 0 then
+ EVENT_IP_CHANGE_NEXT <= EVENT_IP_CHANGE_B;
+ else
+ EVENT_IP_CHANGE_NEXT <= EVENT_IP_CHANGE_A;
+ end if;
+
+ when EVENT_IP_CHANGE_B =>
+ cts_eb_switch_status_out_fsm <= x"3";
+ ip_cntr_up_fsm <= '1';
+ event_cntr_rst_fsm <= '1';
+ EVENT_IP_CHANGE_NEXT <= EVENT_IP_CHANGE_C;
+
+ when EVENT_IP_CHANGE_C =>
+ cts_eb_switch_status_out_fsm <= x"4";
+ EVENT_IP_CHANGE_NEXT <= EVENT_IP_CHANGE_D;
+
+ when EVENT_IP_CHANGE_D =>
+ cts_eb_switch_status_out_fsm <= x"5";
+ EVENT_IP_CHANGE_NEXT <= START;
+
+ when others =>
+ cts_eb_switch_status_out_fsm <= x"0";
+ EVENT_IP_CHANGE_NEXT <= START;
+
+ end case;
+ end process EVENT_IP_CHANGE_PROC;
+
+
+
+
+end cts_eb_ip_switch;
--- /dev/null
+
+#################################################################
+# Basic Constraints
+#################################################################
+COMMERCIAL ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+
+IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+
+#################################################################
+# Clock I/O
+#################################################################
+LOCATE COMP "ADO_CLKOUT" SITE "M30";
+LOCATE COMP "CLK_200_IN" SITE "L1";
+
+IOBUF PORT "ADO_CLKOUT" IO_TYPE=LVDS ;
+IOBUF PORT "CLK_200_IN" IO_TYPE=LVDS ;
+
+FREQUENCY PORT CLK_200_IN 200.000000 MHz;
+
+#USE PRIMARY NET "";
+#################################################################
+# Reset
+#################################################################
+#LOCATE COMP "ADDON_RESET" SITE "AM7";
+#LOCATE COMP "RESET_FPGA_1" SITE "AG11";
+
+#IOBUF PORT "ADDON_RESET" IO_TYPE=LVTTL33 PULLMODE=UP ;
+#IOBUF PORT "RESET_FPGA_1" IO_TYPE=LVTTL33 PULLMODE=UP ;
+
+
+#################################################################
+# To TRB
+#################################################################
+LOCATE COMP "ADO_TTL_0" SITE "AM16";
+LOCATE COMP "ADO_TTL_1" SITE "AL16";
+LOCATE COMP "ADO_TTL_2" SITE "AF16";
+LOCATE COMP "ADO_TTL_3" SITE "AE16";
+LOCATE COMP "ADO_TTL_4" SITE "AM15";
+LOCATE COMP "ADO_TTL_5" SITE "AL15";
+LOCATE COMP "ADO_TTL_6" SITE "AD16";
+LOCATE COMP "ADO_TTL_7" SITE "AC16";
+LOCATE COMP "ADO_TTL_8" SITE "AM14";
+LOCATE COMP "ADO_TTL_9" SITE "AL14";
+LOCATE COMP "ADO_TTL_10" SITE "AG16";
+LOCATE COMP "ADO_TTL_11" SITE "AH16";
+LOCATE COMP "ADO_TTL_12" SITE "AK15";
+LOCATE COMP "ADO_TTL_13" SITE "AJ15";
+LOCATE COMP "ADO_TTL_14" SITE "AH15";
+LOCATE COMP "ADO_TTL_15" SITE "AH14";
+LOCATE COMP "ADO_TTL_16" SITE "AM13";
+LOCATE COMP "ADO_TTL_17" SITE "AM12";
+LOCATE COMP "ADO_TTL_18" SITE "AH13";
+LOCATE COMP "ADO_TTL_19" SITE "AH12";
+LOCATE COMP "ADO_TTL_20" SITE "AK14";
+LOCATE COMP "ADO_TTL_21" SITE "AJ14";
+LOCATE COMP "ADO_TTL_22" SITE "AE15";
+LOCATE COMP "ADO_TTL_23" SITE "AD15";
+LOCATE COMP "ADO_TTL_24" SITE "AL13";
+LOCATE COMP "ADO_TTL_25" SITE "AL12";
+LOCATE COMP "ADO_TTL_26" SITE "AG14";
+LOCATE COMP "ADO_TTL_27" SITE "AG13";
+LOCATE COMP "ADO_TTL_28" SITE "AM11";
+LOCATE COMP "ADO_TTL_29" SITE "AM10";
+LOCATE COMP "ADO_TTL_30" SITE "AH11";
+LOCATE COMP "ADO_TTL_31" SITE "AH10";
+LOCATE COMP "ADO_TTL_32" SITE "AK12";
+LOCATE COMP "ADO_TTL_33" SITE "AJ12";
+LOCATE COMP "ADO_TTL_34" SITE "AF14";
+LOCATE COMP "ADO_TTL_35" SITE "AE14";
+LOCATE COMP "ADO_TTL_36" SITE "AL11";
+LOCATE COMP "ADO_TTL_37" SITE "AL10";
+LOCATE COMP "ADO_TTL_38" SITE "AH9";
+LOCATE COMP "ADO_TTL_39" SITE "AH8";
+LOCATE COMP "ADO_TTL_40" SITE "AK11";
+LOCATE COMP "ADO_TTL_41" SITE "AJ11";
+LOCATE COMP "ADO_TTL_42" SITE "AH7";
+LOCATE COMP "ADO_TTL_43" SITE "AH6";
+LOCATE COMP "ADO_TTL_44" SITE "AM9";
+LOCATE COMP "ADO_TTL_45" SITE "AM8";
+LOCATE COMP "ADO_TTL_46" SITE "AF13";
+DEFINE PORT GROUP "ADOTTL_group" "ADO_TTL*" ;
+IOBUF GROUP "ADOTTL_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16;
+
+#LOCATE COMP "FS_PE_5" SITE "AE13";
+#LOCATE COMP "FS_PE_6" SITE "AL9";
+#LOCATE COMP "FS_PE_7" SITE "AL8";
+LOCATE COMP "FS_PE_8" SITE "AG6";
+LOCATE COMP "FS_PE_9" SITE "AK9";
+#LOCATE COMP "FS_PE_10" SITE "AJ9";
+#LOCATE COMP "FS_PE_11" SITE "AG10";
+DEFINE PORT GROUP "FSPE_group" "FS_PE*" ;
+IOBUF GROUP "FSPE_group" IO_TYPE=LVTTL33 PULLMODE=NONE DRIVE=16;
+
+#################################################################
+# Debug
+#################################################################
+LOCATE COMP "TEST_LINE_0" SITE "AL6";
+LOCATE COMP "TEST_LINE_1" SITE "AL5";
+LOCATE COMP "TEST_LINE_2" SITE "AG7";
+LOCATE COMP "TEST_LINE_3" SITE "AG8";
+LOCATE COMP "TEST_LINE_4" SITE "AK6";
+LOCATE COMP "TEST_LINE_5" SITE "AJ6";
+LOCATE COMP "TEST_LINE_6" SITE "AF10";
+LOCATE COMP "TEST_LINE_7" SITE "AE11";
+LOCATE COMP "TEST_LINE_8" SITE "AM4";
+LOCATE COMP "TEST_LINE_9" SITE "AM3";
+LOCATE COMP "TEST_LINE_10" SITE "AH5";
+LOCATE COMP "TEST_LINE_11" SITE "AH4";
+LOCATE COMP "TEST_LINE_12" SITE "AK5";
+LOCATE COMP "TEST_LINE_13" SITE "AJ5";
+LOCATE COMP "TEST_LINE_14" SITE "AF8";
+LOCATE COMP "TEST_LINE_15" SITE "AF7";
+LOCATE COMP "TEST_LINE_16" SITE "AL4";
+LOCATE COMP "TEST_LINE_17" SITE "AL3";
+LOCATE COMP "TEST_LINE_18" SITE "AG5";
+LOCATE COMP "TEST_LINE_19" SITE "AF6";
+LOCATE COMP "TEST_LINE_20" SITE "AK3";
+LOCATE COMP "TEST_LINE_21" SITE "AJ3";
+LOCATE COMP "TEST_LINE_22" SITE "AE10";
+LOCATE COMP "TEST_LINE_23" SITE "AD10";
+LOCATE COMP "TEST_LINE_24" SITE "AL2";
+LOCATE COMP "TEST_LINE_25" SITE "AK2";
+LOCATE COMP "TEST_LINE_26" SITE "AE9";
+LOCATE COMP "TEST_LINE_27" SITE "AE8";
+LOCATE COMP "TEST_LINE_28" SITE "AJ1";
+LOCATE COMP "TEST_LINE_29" SITE "AK1";
+LOCATE COMP "TEST_LINE_30" SITE "AJ2";
+LOCATE COMP "TEST_LINE_31" SITE "AH3";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVTTL33 PULLMODE=DOWN DRIVE=16;
+
+#################################################################
+# To second FPGA
+#################################################################
+
+LOCATE COMP "FFC_0" SITE "AJ19"; #"FFC_P__0"
+LOCATE COMP "FFC_1" SITE "AK19"; #"FFC_N__0"
+LOCATE COMP "FFC_2" SITE "AD18"; #"FFC_P__1"
+LOCATE COMP "FFC_3" SITE "AE18"; #"FFC_N__1"
+LOCATE COMP "FFC_4" SITE "AM21"; #"FFC_P__2"
+LOCATE COMP "FFC_5" SITE "AM20"; #"FFC_N__2"
+LOCATE COMP "FFC_6" SITE "AH21"; #"FFC_P__3"
+LOCATE COMP "FFC_7" SITE "AH20"; #"FFC_N__3"
+LOCATE COMP "FFC_8" SITE "AJ18"; #"FFC_P__4"
+LOCATE COMP "FFC_9" SITE "AK18"; #"FFC_N__4"
+LOCATE COMP "FFC_10" SITE "AH19"; #"FFC_P__5"
+LOCATE COMP "FFC_11" SITE "AH18"; #"FFC_N__5"
+LOCATE COMP "FFC_12" SITE "AL19"; #"FFC_P__6"
+LOCATE COMP "FFC_13" SITE "AM19"; #"FFC_N__6"
+LOCATE COMP "FFC_14" SITE "AH17"; #"FFC_P__7"
+LOCATE COMP "FFC_15" SITE "AG17"; #"FFC_N__7"
+LOCATE COMP "FFC_16" SITE "AL18"; #"FFC_P__8"
+LOCATE COMP "FFC_17" SITE "AM18"; #"FFC_N__8"
+LOCATE COMP "FFC_18" SITE "AC17"; #"FFC_P__9"
+LOCATE COMP "FFC_19" SITE "AD17"; #"FFC_N__9"
+LOCATE COMP "FFC_20" SITE "AL17"; #"FFC_P__10"
+LOCATE COMP "FFC_21" SITE "AM17"; #"FFC_N__10"
+LOCATE COMP "FFC_22" SITE "AE17"; #"FFC_P__11"
+#LOCATE COMP "FFC_23" SITE "AF17"; #"FFC_N__11"
+LOCATE COMP "ONEWIRE_MONITOR_IN" SITE "AF17"; #"FFC_N__11"
+
+DEFINE PORT GROUP "FFC_group" "FFC*" ;
+IOBUF GROUP "FFC_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=16;
+IOBUF PORT "ONEWIRE_MONITOR_IN" IO_TYPE=LVCMOS25 PULLMODE=UP ;
+
+#################################################################
+# Display / LED
+#################################################################
+LOCATE COMP "LED_GREEN" SITE "E17";
+LOCATE COMP "LED_ORANGE" SITE "B20";
+LOCATE COMP "LED_RED" SITE "C20";
+LOCATE COMP "LED_YELLOW" SITE "E18";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=8;
+
+LOCATE COMP "DIS1_0" SITE "F20";
+LOCATE COMP "DIS1_1" SITE "E20";
+LOCATE COMP "DIS1_2" SITE "K18";
+LOCATE COMP "DIS2_0" SITE "G20";
+LOCATE COMP "DIS2_1" SITE "H20";
+LOCATE COMP "DIS2_2" SITE "D19";
+DEFINE PORT GROUP "DIS_group" "DIS*" ;
+IOBUF GROUP "DIS_group" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;
+
+#################################################################
+# Flash
+#################################################################
+LOCATE COMP "SPI_CLK_OUT" SITE "A19";
+LOCATE COMP "SPI_CS_OUT" SITE "A20";
+LOCATE COMP "SPI_SI_OUT" SITE "H18";
+LOCATE COMP "SPI_SO_IN" SITE "H17";
+LOCATE COMP "PROGRAMN_OUT" SITE "B17";
+DEFINE PORT GROUP "SPI_group" "SPI*" ;
+IOBUF GROUP "SPI_group" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;
+IOBUF PORT "PROGRAMN_OUT" IO_TYPE=LVTTL33 PULLMODE=UP;
+
+#################################################################
+# Output signals
+#################################################################
+
+LOCATE COMP "LVDS_OUT_0" SITE "P30";
+LOCATE COMP "LVDS_OUT_1" SITE "P32";
+LOCATE COMP "LVDS_OUT_2" SITE "R30";
+LOCATE COMP "LVDS_OUT_3" SITE "R31";
+LOCATE COMP "LVDS_OUT_4" SITE "T31";
+LOCATE COMP "LVDS_OUT_5" SITE "U32";
+LOCATE COMP "LVDS_OUT_6" SITE "V32";
+LOCATE COMP "LVDS_OUT_7" SITE "V29";
+LOCATE COMP "LVDS_OUT_8" SITE "W30";
+LOCATE COMP "LVDS_OUT_9" SITE "W31";
+LOCATE COMP "LVDS_OUT_10" SITE "W28";
+LOCATE COMP "LVDS_OUT_11" SITE "W32";
+LOCATE COMP "LVDS_OUT_12" SITE "AA29";
+LOCATE COMP "LVDS_OUT_13" SITE "AB31";
+LOCATE COMP "LVDS_OUT_14" SITE "AB29";
+#LOCATE COMP "LVDS_OUT_15" SITE "AB32";
+
+LOCATE COMP "LVDS_IN" SITE "AB32";
+IOBUF PORT "LVDS_IN" IO_TYPE=LVDS25;
+
+DEFINE PORT GROUP "LVDS_group" "LVDS*" ;
+IOBUF GROUP "LVDS_group" IO_TYPE=LVDS;
+
+LOCATE COMP "PECL_OUT_0" SITE "M4";
+LOCATE COMP "PECL_OUT_1" SITE "M3";
+LOCATE COMP "PECL_OUT_2" SITE "L2";
+DEFINE PORT GROUP "PECL_group" "PECL*" ;
+IOBUF GROUP "PECL_group" IO_TYPE=LVDS;
+
+LOCATE COMP "RICH_CLK_OUT" SITE "AD31";
+LOCATE COMP "RICH_RESERVED_OUT" SITE "AC32";
+LOCATE COMP "RICH_TIMING_OUT_0" SITE "AC28";
+LOCATE COMP "RICH_TRIGGER_OUT" SITE "AD29";
+DEFINE PORT GROUP "RICH_group" "RICH*" ;
+IOBUF GROUP "RICH_group" IO_TYPE=LVDS;
+
+#################################################################
+# Switches
+#################################################################
+LOCATE COMP "RS1_0" SITE "AL7";
+LOCATE COMP "RS1_1" SITE "AD13";
+LOCATE COMP "RS1_2" SITE "AC13";
+LOCATE COMP "RS1_3" SITE "AK8";
+LOCATE COMP "RS2_0" SITE "AJ8";
+LOCATE COMP "RS2_1" SITE "AF11";
+LOCATE COMP "RS2_2" SITE "AD12";
+LOCATE COMP "RS2_3" SITE "AE12";
+DEFINE PORT GROUP "RS_group" "RS*" ;
+IOBUF GROUP "RS_group" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;
+
+#################################################################
+# SFP
+#################################################################
+
+LOCATE COMP "TRB2_LOS" SITE "J16";
+LOCATE COMP "TRB2_MOD_0" SITE "H16";
+LOCATE COMP "TRB2_MOD_1" SITE "A14";
+LOCATE COMP "TRB2_MOD_2" SITE "A13";
+LOCATE COMP "TRB2_TX_DIS" SITE "H15";
+
+LOCATE COMP "TRB2_RX_LED" SITE "D18";
+LOCATE COMP "TRB2_OK_LED" SITE "B19";
+LOCATE COMP "TRB2_TX_LED" SITE "C18";
+
+LOCATE COMP "TRB3_LOS" SITE "A16";
+LOCATE COMP "TRB3_MOD_0" SITE "A17";
+LOCATE COMP "TRB3_MOD_1" SITE "A18";
+LOCATE COMP "TRB3_MOD_2" SITE "F17";
+LOCATE COMP "TRB3_TX_DIS" SITE "L17";
+
+LOCATE COMP "TRB3_OK_LED" SITE "K17";
+LOCATE COMP "TRB3_RX_LED" SITE "J17";
+LOCATE COMP "TRB3_TX_LED" SITE "L20";
+DEFINE PORT GROUP "TRB_group" "TRB*" ;
+IOBUF GROUP "TRB_group" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=16;
+
+#################################################################
+# Serdes
+#################################################################
+
+#LOCATE COMP "THE_MEDIA_INTERFACE_0/gen_serdes_0_200_THE_SERDES/PCSA_INST" SITE "PCS36000";
+
+#################################################################
+# Input signals
+#################################################################
+LOCATE COMP "TRIG_IN_0" SITE "K8";
+LOCATE COMP "TRIG_IN_1" SITE "D1";
+LOCATE COMP "TRIG_IN_2" SITE "E1";
+LOCATE COMP "TRIG_IN_3" SITE "F1";
+LOCATE COMP "TRIG_IN_4" SITE "G2";
+LOCATE COMP "TRIG_IN_5" SITE "H2";
+LOCATE COMP "TRIG_IN_6" SITE "J4";
+LOCATE COMP "TRIG_IN_7" SITE "J3";
+LOCATE COMP "TRIG_IN_8" SITE "J1";
+LOCATE COMP "TRIG_IN_9" SITE "K2";
+LOCATE COMP "TRIG_IN_10" SITE "N2";
+LOCATE COMP "TRIG_IN_11" SITE "P3";
+LOCATE COMP "TRIG_IN_12" SITE "P1";
+LOCATE COMP "TRIG_IN_13" SITE "R3";
+LOCATE COMP "TRIG_IN_14" SITE "R2";
+LOCATE COMP "TRIG_IN_15" SITE "T2";
+LOCATE COMP "TRIG_IN_16" SITE "U1";
+LOCATE COMP "TRIG_IN_17" SITE "V1";
+LOCATE COMP "TRIG_IN_18" SITE "V4";
+LOCATE COMP "TRIG_IN_19" SITE "W3";
+LOCATE COMP "TRIG_IN_20" SITE "W2";
+LOCATE COMP "TRIG_IN_21" SITE "W5";
+LOCATE COMP "TRIG_IN_22" SITE "W1";
+LOCATE COMP "TRIG_IN_23" SITE "AB2";
+LOCATE COMP "TRIG_IN_24" SITE "AB4";
+LOCATE COMP "TRIG_IN_25" SITE "AB1";
+LOCATE COMP "TRIG_IN_26" SITE "AD2";
+LOCATE COMP "TRIG_IN_27" SITE "AD4";
+LOCATE COMP "TRIG_IN_28" SITE "AC5";
+LOCATE COMP "TRIG_IN_29" SITE "AC1";
+LOCATE COMP "TRIG_IN_30" SITE "AE3";
+LOCATE COMP "TRIG_IN_31" SITE "AE2";
+LOCATE COMP "TRIG_IN_32" SITE "AJ32";
+LOCATE COMP "TRIG_IN_33" SITE "AK31";
+LOCATE COMP "TRIG_IN_34" SITE "AK30";
+LOCATE COMP "TRIG_IN_35" SITE "AK29";
+LOCATE COMP "TRIG_IN_36" SITE "AM30";
+LOCATE COMP "TRIG_IN_37" SITE "AJ27";
+LOCATE COMP "TRIG_IN_38" SITE "AL28";
+LOCATE COMP "TRIG_IN_39" SITE "AM28";
+LOCATE COMP "TRIG_IN_40" SITE "AL26";
+LOCATE COMP "TRIG_IN_41" SITE "AJ24";
+LOCATE COMP "TRIG_IN_42" SITE "AL25";
+LOCATE COMP "TRIG_IN_43" SITE "AJ22";
+LOCATE COMP "TRIG_IN_44" SITE "AL23";
+LOCATE COMP "TRIG_IN_45" SITE "AJ21";
+LOCATE COMP "TRIG_IN_46" SITE "AM23";
+LOCATE COMP "TRIG_IN_47" SITE "AL21";
+LOCATE COMP "TRIG_IN_48" SITE "AG32";
+LOCATE COMP "TRIG_IN_49" SITE "AF32";
+LOCATE COMP "TRIG_IN_50" SITE "AE31";
+LOCATE COMP "TRIG_IN_51" SITE "AE30";
+LOCATE COMP "TRIG_IN_52" SITE "N31";
+LOCATE COMP "TRIG_IN_53" SITE "L32";
+LOCATE COMP "TRIG_IN_54" SITE "K31";
+LOCATE COMP "TRIG_IN_55" SITE "J32";
+LOCATE COMP "TRIG_IN_56" SITE "J30";
+LOCATE COMP "TRIG_IN_57" SITE "J29";
+LOCATE COMP "TRIG_IN_58" SITE "H31";
+LOCATE COMP "TRIG_IN_59" SITE "G31";
+LOCATE COMP "TRIG_IN_60" SITE "F32";
+LOCATE COMP "TRIG_IN_61" SITE "E32";
+LOCATE COMP "TRIG_IN_62" SITE "D32";
+LOCATE COMP "TRIG_IN_63" SITE "K25";
+DEFINE PORT GROUP "TRIG_group" "TRIG*" ;
+IOBUF GROUP "TRIG_group" IO_TYPE=LVDS;
+INPUT "TRIG_group" SETUP 1 ns CLKPORT="clk_400"
+#################################################################
+# Pins not needed in lpf
+#################################################################
+# LOCATE COMP "PECL_OUT_N__0" SITE "L4";
+# LOCATE COMP "PECL_OUT_N__1" SITE "L3";
+# LOCATE COMP "PECL_OUT_N__2" SITE "M2";
+
+# LOCATE COMP "TRIG_IN_N__0" SITE "J8";
+# LOCATE COMP "TRIG_IN_N__1" SITE "D2";
+# LOCATE COMP "TRIG_IN_N__2" SITE "E2";
+# LOCATE COMP "TRIG_IN_N__3" SITE "F2";
+# LOCATE COMP "TRIG_IN_N__4" SITE "G1";
+# LOCATE COMP "TRIG_IN_N__5" SITE "H1";
+# LOCATE COMP "TRIG_IN_N__6" SITE "H4";
+# LOCATE COMP "TRIG_IN_N__7" SITE "H3";
+# LOCATE COMP "TRIG_IN_N__8" SITE "J2";
+# LOCATE COMP "TRIG_IN_N__9" SITE "K1";
+# LOCATE COMP "TRIG_IN_N__10" SITE "N1";
+# LOCATE COMP "TRIG_IN_N__11" SITE "P4";
+# LOCATE COMP "TRIG_IN_N__12" SITE "P2";
+# LOCATE COMP "TRIG_IN_N__13" SITE "R4";
+# LOCATE COMP "TRIG_IN_N__14" SITE "R1";
+# LOCATE COMP "TRIG_IN_N__15" SITE "T1";
+# LOCATE COMP "TRIG_IN_N__16" SITE "U2";
+# LOCATE COMP "TRIG_IN_N__17" SITE "V2";
+# LOCATE COMP "TRIG_IN_N__18" SITE "V3";
+# LOCATE COMP "TRIG_IN_N__19" SITE "W4";
+# LOCATE COMP "TRIG_IN_N__20" SITE "Y2";
+# LOCATE COMP "TRIG_IN_N__21" SITE "Y5";
+# LOCATE COMP "TRIG_IN_N__22" SITE "Y1";
+# LOCATE COMP "TRIG_IN_N__23" SITE "AA2";
+# LOCATE COMP "TRIG_IN_N__24" SITE "AB3";
+# LOCATE COMP "TRIG_IN_N__25" SITE "AA1";
+# LOCATE COMP "TRIG_IN_N__26" SITE "AC2";
+# LOCATE COMP "TRIG_IN_N__27" SITE "AD3";
+# LOCATE COMP "TRIG_IN_N__28" SITE "AD5";
+# LOCATE COMP "TRIG_IN_N__29" SITE "AD1";
+# LOCATE COMP "TRIG_IN_N__30" SITE "AE4";
+# LOCATE COMP "TRIG_IN_N__31" SITE "AE1";
+# LOCATE COMP "TRIG_IN_N__32" SITE "AK32";
+# LOCATE COMP "TRIG_IN_N__33" SITE "AL31";
+# LOCATE COMP "TRIG_IN_N__34" SITE "AL30";
+# LOCATE COMP "TRIG_IN_N__35" SITE "AL29";
+# LOCATE COMP "TRIG_IN_N__36" SITE "AM29";
+# LOCATE COMP "TRIG_IN_N__37" SITE "AK27";
+# LOCATE COMP "TRIG_IN_N__38" SITE "AL27";
+# LOCATE COMP "TRIG_IN_N__39" SITE "AM27";
+# LOCATE COMP "TRIG_IN_N__40" SITE "AM26";
+# LOCATE COMP "TRIG_IN_N__41" SITE "AK24";
+# LOCATE COMP "TRIG_IN_N__42" SITE "AL24";
+# LOCATE COMP "TRIG_IN_N__43" SITE "AK22";
+# LOCATE COMP "TRIG_IN_N__44" SITE "AL22";
+# LOCATE COMP "TRIG_IN_N__45" SITE "AK21";
+# LOCATE COMP "TRIG_IN_N__46" SITE "AM22";
+# LOCATE COMP "TRIG_IN_N__47" SITE "AL20";
+# LOCATE COMP "TRIG_IN_N__48" SITE "AG31";
+# LOCATE COMP "TRIG_IN_N__49" SITE "AF31";
+# LOCATE COMP "TRIG_IN_N__50" SITE "AE32";
+# LOCATE COMP "TRIG_IN_N__51" SITE "AE29";
+# LOCATE COMP "TRIG_IN_N__52" SITE "N32";
+# LOCATE COMP "TRIG_IN_N__53" SITE "M32";
+# LOCATE COMP "TRIG_IN_N__54" SITE "K32";
+# LOCATE COMP "TRIG_IN_N__55" SITE "J31";
+# LOCATE COMP "TRIG_IN_N__56" SITE "H30";
+# LOCATE COMP "TRIG_IN_N__57" SITE "H29";
+# LOCATE COMP "TRIG_IN_N__58" SITE "H32";
+# LOCATE COMP "TRIG_IN_N__59" SITE "G32";
+# LOCATE COMP "TRIG_IN_N__60" SITE "F31";
+# LOCATE COMP "TRIG_IN_N__61" SITE "E31";
+# LOCATE COMP "TRIG_IN_N__62" SITE "D31";
+# LOCATE COMP "TRIG_IN_N__63" SITE "J25";
+# LOCATE COMP "LVDS_OUT_N__0" SITE "P29";
+# LOCATE COMP "LVDS_OUT_N__1" SITE "P31";
+# LOCATE COMP "LVDS_OUT_N__2" SITE "R29";
+# LOCATE COMP "LVDS_OUT_N__3" SITE "R32";
+# LOCATE COMP "LVDS_OUT_N__4" SITE "T32";
+# LOCATE COMP "LVDS_OUT_N__5" SITE "U31";
+# LOCATE COMP "LVDS_OUT_N__6" SITE "V31";
+# LOCATE COMP "LVDS_OUT_N__7" SITE "V30";
+# LOCATE COMP "LVDS_OUT_N__8" SITE "W29";
+# LOCATE COMP "LVDS_OUT_N__9" SITE "Y31";
+# LOCATE COMP "LVDS_OUT_N__10" SITE "Y28";
+# LOCATE COMP "LVDS_OUT_N__11" SITE "Y32";
+# LOCATE COMP "LVDS_OUT_N__12" SITE "AA30";
+# LOCATE COMP "LVDS_OUT_N__13" SITE "AA31";
+# LOCATE COMP "LVDS_OUT_N__14" SITE "AB30";
+# LOCATE COMP "LVDS_OUT_N__15" SITE "AA32";
+# LOCATE COMP "ADO_CLKOUTN" SITE "M30";
+# LOCATE COMP "SPI_CLK" SITE "F16";
+# LOCATE COMP "SPI_CS" SITE "K15";
+# LOCATE COMP "SPI_IN" SITE "J15";
+# LOCATE COMP "SPI_OUT" SITE "B14";
+# LOCATE COMP "RICH_TRIGGER_N" SITE "AD30";
+# LOCATE COMP "RICH_CLK_N" SITE "AC31";
+# LOCATE COMP "RICH_RESERVED_N" SITE "AD32";
+# LOCATE COMP "RICH_TIMING_N" SITE "AD28";
+# LOCATE COMP "RDCFGN" SITE "J20";
+# LOCATE COMP "RESETN" SITE "J21";
+# LOCATE COMP "TDO_F_1" SITE "J9";
+# LOCATE COMP "FS_PE_0" SITE "J13";
+# LOCATE COMP "FS_PE_1" SITE "K9";
+# LOCATE COMP "FS_PE_2" SITE "J12";
+# LOCATE COMP "TRB3_RXN" SITE "G25";
+# LOCATE COMP "TRB3_RXP" SITE "F25";
+# LOCATE COMP "TRB3_TXN" SITE "B25";
+# LOCATE COMP "TRB3_TXP" SITE "A25";
+# LOCATE COMP "TRB2_RXN" SITE "C31";
+# LOCATE COMP "TRB2_RXP" SITE "C32";
+# LOCATE COMP "TRB2_TXN" SITE "B30";
+# LOCATE COMP "TRB2_TXP" SITE "A30";
+# LOCATE COMP "TRB2_RATE_SEL" SITE "G16";
+# LOCATE COMP "TRB3_RATE_SEL" SITE "G17";
+# LOCATE COMP "TRB2_TX_FAULT" SITE "K16";
+# LOCATE COMP "TRB3_TX_FAULT" SITE "A15";
+#-- Synplicity, Inc.
+#-- Version 9.0
+#-- Project file ../ctsaddon/cts_fpga1.prj
+
+
#add_file options
add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd"
-add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd"
-add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd"
-add_file -vhdl -lib work "../trbnet/basics/ram.vhd"
-add_file -vhdl -lib work "../trbnet/basics/ram_16x8_dp.vhd"
-add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../trbnet/basics/ram_dp.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_term.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_dummy_fifo.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_dummy_fifo.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_term_ibuf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net_onewire_listener.vhd"
-add_file -vhdl -lib work "../trbnet/special/spi_master.vhd"
-add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd"
-add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../trbnet/special/handler_data.vhd"
-add_file -vhdl -lib work "../trbnet/special/handler_ipu.vhd"
-add_file -vhdl -lib work "../trbnet/special/handler_trigger_and_data.vhd"
-add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
-add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net_std.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net_components.vhd"
+
+#add_file -vhdl -lib work "../trbnet/trb_net16_term_buf.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net_CRC.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net_onewire.vhd"
+#add_file -vhdl -lib work "../trbnet/basics/rom_16x8.vhd"
+#add_file -vhdl -lib work "../trbnet/basics/ram.vhd"
+#add_file -vhdl -lib work "../trbnet/basics/ram_16x8_dp.vhd"
+#add_file -vhdl -lib work "../trbnet/basics/ram_16x16_dp.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_addresses.vhd"
+#add_file -vhdl -lib work "../trbnet/basics/ram_dp.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_term.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net_sbuf.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_sbuf.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_regIO.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_regio_bus_handler.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net_priority_encoder.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net_dummy_fifo.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_dummy_fifo.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_term_ibuf.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net_priority_arbiter.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net_pattern_gen.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_obuf_nodata.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_obuf.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_ibuf.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_api_base.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_iobuf.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_io_multiplexer.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_trigger.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_ipudata.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net_onewire_listener.vhd"
+#add_file -vhdl -lib work "../trbnet/basics/signal_sync.vhd"
+#add_file -vhdl -lib work "../trbnet/basics/ram_dp_rw.vhd"
+#add_file -vhdl -lib work "../trbnet/special/spi_master.vhd"
+#add_file -vhdl -lib work "../trbnet/special/spi_slim.vhd"
+#add_file -vhdl -lib work "../trbnet/special/spi_databus_memory.vhd"
+#add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
+#add_file -vhdl -lib work "../trbnet/special/trb_net_reset_handler.vhd"
+#
+#add_file -vhdl -lib work "../trbnet/special/handler_data.vhd"
+#add_file -vhdl -lib work "../trbnet/special/handler_ipu.vhd"
+#add_file -vhdl -lib work "../trbnet/special/handler_trigger_and_data.vhd"
+#add_file -vhdl -lib work "../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
+
+#add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd"
+#add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_gbe_0_200.vhd"
#Lattice SCM files
-add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in200_out100.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_ecp2m_fifo.vhd"
-
-#############################
-add_file -vhdl -lib work "../trbnet/lattice/scm/spi_dpram_32_to_8.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_scm_fifo_18x1k.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "../trbnet/special/trb_net_reset_handler.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x256_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x512_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x1k_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x2k_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x4k_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x8k_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x16k_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_36x32k_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x256_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x512_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x1k_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_18x2k_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/fifo/fifo_var_oreg.vhd"
-add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_scm_sfp_gbe.vhd"
-add_file -vhdl -lib work "../trbnet/media_interfaces/scm_sfp/serdes_gbe_0_200.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd"
-#############################
+#add_file -vhdl -lib work "../trbnet/lattice/scm/pll_in200_out100.vhd"
+#add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_ecp2m_fifo.vhd"
+#Wrong filename, but hard to change now...
+#cts files - top entity and its main components
add_file -vhdl -lib work "cts_fpga1.vhd"
+add_file -vhdl -lib work "cts_components.vhd"
+
+add_file -vhdl -lib work "pll_in200_out400.vhd"
+add_file -vhdl -lib work "dll_in400_out200.vhd"
+add_file -vhdl -lib work "pll_in200_out40.vhd"
+add_file -vhdl -lib work "../trbv2/f_divider.vhd"
+add_file -vhdl -lib work "../trbv2/up_down_counter.vhd"
+add_file -vhdl -lib work "ddr2_busses.vhd"
+add_file -vhdl -lib work "cts_trigger_logic.vhd"
+add_file -vhdl -lib work "cts_fpga1_to_fpga2.vhd"
+add_file -vhdl -lib work "cts_readout.vhd"
+add_file -vhdl -lib work "etrax_reg_mem.vhd"
+add_file -vhdl -lib work "cts_beam_structure.vhd"
+add_file -vhdl -lib work "cts_simple_data_transport.vhd"
+ #ddr2_busses components
+ add_file -vhdl -lib work "dll_edge.vhd"
+ add_file -vhdl -lib work "ddr2_16inputs.vhd"
+ add_file -vhdl -lib work "fifo16bit_synch.vhd"
+ add_file -vhdl -lib work "ddr2_12out_clkdiv.vhd"
+ add_file -vhdl -lib work "ddr2_3out_clkdiv.vhd"
+ #cts_trigger_logic.vhd
+ add_file -vhdl -lib work "cts_one_clock.vhd"
+ add_file -vhdl -lib work "cts_polarity_check.vhd"
+ add_file -vhdl -lib work "cts_delay_large.vhd"
+ #next level
+ add_file -vhdl -lib work "delay_fifo.vhd"
+ add_file -vhdl -lib work "cts_delay.vhd"
+ add_file -vhdl -lib work "multiplicity.vhd"
+ add_file -vhdl -lib work "cts_set_width.vhd"
+ #next level
+ add_file -vhdl -lib work "cts_width_rom.vhd"
+ add_file -vhdl -lib work "cts_set_width_large.vhd"
+ add_file -vhdl -lib work "cts_downscale.vhd"
+ add_file -vhdl -lib work "cts_align_signals.vhd"
+ add_file -vhdl -lib work "ddr_lvl1_trigger.vhd"
+ add_file -vhdl -lib work "cts_cal_screset_gen.vhd"
+ #ddr_lvl1_trigger components none
+ #cts_fpga1_to_fpga2 comp
+ add_file -vhdl -lib work "cts_eb_ip_switch.vhd"
+ #cts_readout comp
+ add_file -vhdl -lib work "cts_readout_data_buff.vhd"
+ #etrax_reg_mem comp
+ add_file -vhdl -lib work "ram_register.vhd"
+ #cts beam struct comp
+ add_file -vhdl -lib work "beam_structure_fifo.vhd"
+ #cts_simple_data_transport comp
+ add_file -vhdl -lib work "cts_fpga2_lvl1_lvl2_fifo.vhd"
+ #next level
+ add_file -vhdl -lib work "scm_fifo_1bit_to_32bit.vhd"
+ add_file -vhdl -lib work "scm_fifo_2bit_to_32bit.vhd"
+ add_file -vhdl -lib work "scm_fifo_4bit_to_32bit.vhd"
+ add_file -vhdl -lib work "scm_fifo_8bit_to_32bit.vhd"
+ add_file -vhdl -lib work "scm_fifo_16bit_to_32bit.vhd"
+
+
+
+
+
+#Some of these files have to be regenerated
+# add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/scm/trb_net_fifo_16bit_bram_dualport.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd"
+# add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/ddr_off.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd"
+# add_file -vhdl -lib work "../trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd"
+# add_file -vhdl -lib work "../trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_clock_generator.vhd"
+# add_file -vhdl -lib work "../trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd"
-####################
-# implementation: "workdir"
+
+
+
+
+
+#implementation: "workdir"
impl -add workdir -type fpga
-# device options
+#device options
set_option -technology LATTICE-SCM
set_option -part LFSCM3GA40EP1
set_option -package FF1020C
-set_option -speed_grade -5
+set_option -speed_grade -7
set_option -part_companion ""
-# compilation/mapping options
-set_option -default_enum_encoding sequential
-set_option -symbolic_fsm_compiler 1
+#compilation/mapping options
+#set_option -default_enum_encoding sequential
+#set_option -symbolic_fsm_compiler 1
+#set_option -resource_sharing 0
set_option -top_module "cts_fpga1"
-# map options
-set_option -frequency 100
+#map options
+set_option -frequency 220
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -pipe 0
-# set_option -force_gsr auto
-set_option -force_gsr false
+set_option -force_gsr auto
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
-# simulation options
+
+
+#simulation options
set_option -write_verilog 0
-set_option -write_vhdl 1
+set_option -write_vhdl 0
-# automatic place and route (vendor) options
+#automatic place and route (vendor) options
set_option -write_apr_constraint 0
-# set result format/file last
+#set result format/file last
project -result_format "edif"
project -result_file "workdir/cts_fpga1.edf"
+
+#
#implementation attributes
set_option -vlog_std v2001
set_option -project_relative_includes 1
impl -active "workdir"
-
-LIBRARY ieee;
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_1164.all;
-USE IEEE.numeric_std.ALL;
+use ieee.numeric_std.all;
library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
+--use work.trb_net_std.all;
+--use work.trb_net_components.all;
-- use work.trb_net16_hub_func.all;
use work.version.all;
+use work.cts_components.all;
+library SC;
+use SC.COMPONENTS.all;
+use ieee.std_logic_arith.all;
entity cts_fpga1 is
generic(
NUM_STAT_REGS : integer range 0 to 6 := 2;
NUM_CTRL_REGS : integer range 0 to 6 := 2;
REGIO_INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FF01";
- REGIO_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"
+ REGIO_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001";
+ CTS_NUMBER_IPU_DATA: integer range 0 to 9 :=2;
+ RW_REGISTERS_NUMBER : integer range 0 to 49 := 36;
+ R_REGISTERS_NUMBER : integer range 0 to 105 := 103;
+ TRIGGER_INPUTS_NUMBER : integer range 0 to 64 := 36;
+ TRIGGER_OUTPUTS_NUMBER : integer range 0 to 64 := 19;
+ SCALERS_NUMBER : integer range 0 to 127 := 95; --36 input scalers,
+ --19 after dsc,
+ --17 after coincidence,
+ --19 accepted
+
+ VECTOR_WIDTH : integer range 1 to 8 := 4;
+ CTS_MODE : integer range 0 to 1 :=1;
+ CTS_TYPE : integer range 0 to 4 :=1; --0 --see cts readout
+ --and ipu_ready_in !
+ --1 -- the ipu_readout
+ --is on other fpga !
+ LVL1_SIZE_OF_DATA_BUS_OUT : integer range 0 to 16 :=8;
+ LVL2_SIZE_OF_DATA_BUS_OUT : integer range 0 to 16 :=8;
+ RATE_MARKERS_NUMBER : integer range 0 to 16 :=8;
+ ENABLE_ETRAX_RW_INTERFACE : integer range 0 to 1 :=0 --no_sim--
+--sim-- ENABLE_ETRAX_RW_INTERFACE : integer range 0 to 1 :=1
+
);
port(
--Clocks
CLK_200_IN : in std_logic;
--- ADO_CLKOUT : out std_logic;
- FAKE_SERDES_RXD_P_IN : in std_logic;
- FAKE_SERDES_RXD_N_IN : in std_logic;
- FAKE_SERDES_TXD_P_OUT : out std_logic;
- FAKE_SERDES_TXD_N_OUT : out std_logic;
- FAKE_SERDES_REFCLK_P_IN : in std_logic;
- FAKE_SERDES_REFCLK_N_IN : in std_logic;
- --Resets
+ ADO_CLKOUT : out std_logic;
+ --Resets
RESET_FPGA_1 : in std_logic;
ADDON_RESET : in std_logic;
--To TRB
ADO_TTL : inout std_logic_vector(46 downto 0);
- FS_PE : inout std_logic_vector(11 downto 5);
+ FS_PE : inout std_logic_vector(9 downto 8);
--To 2nd FPGA
FFC : inout std_logic_vector(22 downto 0);
--Trigger IO
- LVDS_IN : in std_logic_vector(63 downto 0);
- LVDS_OUT : out std_logic_vector(15 downto 0);
+ TRIG_IN : in std_logic_vector(63 downto 0);
+ LVDS_OUT : out std_logic_vector(14 downto 0);
+ LVDS_IN : in std_logic;
PECL_OUT : out std_logic_vector(2 downto 0);
RICH_CLK_OUT : out std_logic;
RICH_RESERVED_OUT : out std_logic;
- RICH_TIMING_OUT : out std_logic;
+ RICH_TIMING_OUT : out std_logic_vector(0 downto 0);
RICH_TRIGGER_OUT : out std_logic;
--Flash
SPI_CLK_OUT : out std_logic;
TRB3_LOS : out std_logic;
TRB3_MOD : inout std_logic_vector(2 downto 0);
TRB3_TX_DIS : out std_logic;
+ FAKE_SERDES_RXD_P_IN : in std_logic;
+ FAKE_SERDES_RXD_N_IN : in std_logic;
+ FAKE_SERDES_TXD_P_OUT : out std_logic;
+ FAKE_SERDES_TXD_N_OUT : out std_logic;
+ FAKE_SERDES_REFCLK_P_IN : in std_logic;
+ FAKE_SERDES_REFCLK_N_IN : in std_logic;
+
--Other
ONEWIRE_MONITOR_IN : in std_logic;
RS1 : out std_logic_vector(3 downto 0);
RS2 : out std_logic_vector(3 downto 0);
- DIS1 : out std_logic_vector(2 downto 0);
+ DIS1 : inout std_logic_vector(2 downto 0);
DIS2 : out std_logic_vector(2 downto 0);
--Debug
TEST_LINE : out std_logic_vector(31 downto 0)
);
+
attribute syn_useioff : boolean;
- attribute syn_useioff of FFC : signal is true;
attribute syn_useioff of SPI_CLK_OUT : signal is true;
attribute syn_useioff of SPI_CS_OUT : signal is true;
attribute syn_useioff of SPI_SO_IN : signal is true;
attribute syn_useioff of SPI_SI_OUT : signal is true;
attribute syn_useioff of ADO_TTL : signal is true;
- attribute syn_useioff of LVDS_IN : signal is true;
- attribute syn_useioff of LVDS_OUT : signal is true;
- attribute syn_useioff of PECL_OUT : signal is true;
+-- attribute syn_useioff of TRIG_IN : signal is true;
+-- attribute syn_useioff of LVDS_OUT : signal is true;
+-- attribute syn_useioff of PECL_OUT : signal is true;
attribute syn_useioff of RICH_CLK_OUT : signal is true;
attribute syn_useioff of RICH_RESERVED_OUT : signal is true;
- attribute syn_useioff of RICH_TIMING_OUT : signal is true;
+-- attribute syn_useioff of RICH_TIMING_OUT : signal is true;
attribute syn_useioff of RICH_TRIGGER_OUT : signal is true;
- attribute syn_useioff of SPI_CLK_OUT : signal is true;
- attribute syn_useioff of SPI_CS_OUT : signal is true;
- attribute syn_useioff of SPI_SI_OUT : signal is true;
- attribute syn_useioff of SPI_SO_IN : signal is true;
attribute syn_useioff of PROGRAMN_OUT : signal is false;
attribute syn_useioff of LED_GREEN : signal is false;
attribute syn_useioff of LED_ORANGE : signal is false;
attribute syn_useioff of TRB3_LOS : signal is false;
attribute syn_useioff of TRB3_MOD : signal is false;
attribute syn_useioff of TRB3_TX_DIS : signal is false;
+
+
end entity;
--Clock & Reset
signal clk_100 : std_logic;
--- signal clk_200 : std_logic;
+ signal clk_100_feed : std_logic;
+ signal rw_reset : std_logic;
+ signal clk_200 : std_logic;
+ signal clk_200_locked : std_logic;
signal clk_en : std_logic;
signal make_reset_via_network : std_logic;
signal pll_locked : std_logic;
signal reset_i_100 : std_logic;
+ signal reset_pulse : std_logic;
+ signal reset_gsr : std_logic;
+ signal reset_i_100_gsr : std_logic;
signal reset_async : std_logic;
signal delayed_restart_fpga : std_logic;
- signal restart_fpga_counter : unsigned(11 downto 0);
+ signal clk_400 : std_logic;
+ signal clk_400_tmp : std_logic;
+-- signal restart_fpga_counter : unsigned(11 downto 0);
+ signal global_reset_cnt : std_logic_vector(15 downto 0):=x"0000";
+ signal dll_100_lock : std_logic;
+ signal dll_200_lock : std_logic;
+
--media interface to endpoint
signal med_data_in : std_logic_vector (16-1 downto 0);
signal med_packet_num_in : std_logic_vector (3-1 downto 0);
signal fee_data_finished : std_logic;
signal fee_data_almost_full : std_logic;
- --endpoint RegIo registers
- signal regio_common_stat_reg : std_logic_vector (std_COMSTATREG*32-1 downto 0);
- signal regio_common_ctrl_reg : std_logic_vector (std_COMCTRLREG*32-1 downto 0);
- signal regio_stat_registers : std_logic_vector (32*2**(NUM_STAT_REGS)-1 downto 0);
- signal regio_ctrl_registers : std_logic_vector (32*2**(NUM_CTRL_REGS)-1 downto 0);
- signal regio_common_stat_strobe : std_logic_vector ((std_COMSTATREG)-1 downto 0);
- signal regio_common_ctrl_strobe : std_logic_vector ((std_COMCTRLREG)-1 downto 0);
- signal regio_stat_strobe : std_logic_vector (2**(NUM_STAT_REGS)-1 downto 0);
- signal regio_ctrl_strobe : std_logic_vector (2**(NUM_CTRL_REGS)-1 downto 0);
- signal my_address : std_logic_vector (15 downto 0);
+-- --endpoint RegIo registers
+-- signal regio_common_stat_reg : std_logic_vector (std_COMSTATREG*32-1 downto 0);
+-- signal regio_common_ctrl_reg : std_logic_vector (std_COMCTRLREG*32-1 downto 0);
+-- signal regio_stat_registers : std_logic_vector (32*2**(NUM_STAT_REGS)-1 downto 0);
+-- signal regio_ctrl_registers : std_logic_vector (32*2**(NUM_CTRL_REGS)-1 downto 0);
+-- signal regio_common_stat_strobe : std_logic_vector ((std_COMSTATREG)-1 downto 0);
+-- signal regio_common_ctrl_strobe : std_logic_vector ((std_COMCTRLREG)-1 downto 0);
+-- signal regio_stat_strobe : std_logic_vector (2**(NUM_STAT_REGS)-1 downto 0);
+-- signal regio_ctrl_strobe : std_logic_vector (2**(NUM_CTRL_REGS)-1 downto 0);
+-- signal my_address : std_logic_vector (15 downto 0);
--Timers
signal timing_trigger_feedback : std_logic;
signal local_time : std_logic_vector (7 downto 0);
signal time_since_last_trg : std_logic_vector (31 downto 0);
signal timer_ticks : std_logic_vector (1 downto 0);
+
+ --trigger logic
+ signal input_enable_in_i : std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ signal downscale_register_in_i : std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
+ signal delay_trigger_register_in_i : std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
+ signal delay_large_trigger_register_in_i : std_logic_vector((8*(12)-1) downto 0);
+ signal width_register_in_i : std_logic_vector((4*(TRIGGER_INPUTS_NUMBER+9)-1) downto 0);
+ signal width_register_large_in_i : std_logic_vector((4*(TRIGGER_INPUTS_NUMBER+9)-1) downto 0);
+ signal ts_gating_disable_in_i : std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ signal trigger_out_en_in_i : std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ signal multiplexer_out_i : std_logic_vector(1 downto 0);
+ signal trigger_logic_ctrl_in : std_logic_vector(31 downto 0);
+ signal scaler_out_i : std_logic_vector(SCALERS_NUMBER*32-1 downto 0);
+ signal beam_inhibit_in_i : std_logic;
+ signal no_timing_out_i : std_logic;
+ signal lvl1_triggbox_busy_in_i : std_logic;
+ signal lvl1_apv_trigger_out : std_logic;
+ signal lvl1_triggbox_code_out_i : std_logic_vector(3 downto 0);
+ signal lvl1_triggbox_trigger_i : std_logic;
+ signal lvl1_triggbox_busy_out_i : std_logic;
+ signal ipu_data_in_i : std_logic_vector(31 downto 0);
+ signal ipu_data_valid_in_i : std_logic;
+ signal token_in_i : std_logic;
+ signal data_out_i, data_i : std_logic_vector(31 downto 0);
+ signal data_valid_out_i, data_valid_i : std_logic;
+ signal token_out_i : std_logic;
+ signal save_scalers_out_i : std_logic;
+ signal saved_scalers_in_i : std_logic_vector(SCALERS_NUMBER*32 -1 downto 0);
+ signal trigger_in : std_logic_vector(TRIGGER_INPUTS_NUMBER*4-1 downto 0);
+ signal send_scalers_i : std_logic;
+
+ --trigger_buffer
+ signal lvl1_timing_trigger_out_i : std_logic;
+ signal lvl1_apv_trigger_out_i : std_logic;
+ signal lvl1_trbnet_busy_in_i : std_logic;
+ signal lvl1_trigger_out_i : std_logic;
+ signal lvl1_trigger_code_out_i : std_logic_vector(3 downto 0);
+ signal lvl1_trigger_tag_out_i : std_logic_vector(15 downto 0);
+ signal lvl1_rnd_number_out_i : std_logic_vector(7 downto 0);
+ signal lvl1_trigger_info_out_i : std_logic_vector(31 downto 0);
+ signal lvl2_trbnet_busy_in_i : std_logic;
+ signal lvl2_trigger_buffer_busy_out_i : std_logic;
+ signal lvl2_trigger_out_i : std_logic;
+ signal lvl2_trigger_code_out_i : std_logic_vector(3 downto 0);
+ signal lvl2_trigger_tag_out_i : std_logic_vector(15 downto 0);
+ signal lvl2_rnd_number_out_i : std_logic_vector(7 downto 0);
+ signal lvl2_trigger_info_out_i : std_logic_vector(31 downto 0);
+ --cts readout
+ signal lvl1_busy_out_i : std_logic;
+ signal lvl2_busy_out_i : std_logic;
+ signal lvl1_trbnet_trigger : std_logic;
+ signal lvl1_trbnet_trigger_tag_out_i : std_logic_vector(15 downto 0);
+ signal lvl1_trbnet_trigger_code_out_i : std_logic_vector(3 downto 0);
+ signal lvl1_finished : std_logic;
+ signal lvl2_finished : std_logic;
+ signal ipu_ready_in_i : std_logic;
+ signal ipu_dataready_out_i : std_logic;
+ signal ipu_data_out_i : std_logic_vector(31 downto 0);
+ signal data_version_readout : std_logic_vector(7 downto 0);
-begin
+
+ signal data_readout_cntr_int : integer range 0 to 255 :=0;
+ signal data_readout_cntr : std_logic_vector(7 downto 0);
+ signal data_readout_cntr_rst, data_readout_cntr_rst_fsm, data_readout_cntr_up, data_readout_cntr_up_fsm : std_logic;
+ signal data_readout, data_readout_fsm : std_logic_vector(31 downto 0);
+ signal data_valid, data_valid_fsm : std_logic;
+ signal scalers_finished, scalers_finished_fsm : std_logic;
+ type SCALERS_READOUT is (IDLE, SCALERS_READOUT_RW_A, SCALERS_READOUT_RW_B, SCALERS_READOUT_RESET_A, SCALERS_READOUT_RESET_B, SCALERS_READOUT_R_A, SCALERS_READOUT_R_B, SCALERS_READOUT_FINISHED);
+ signal SCALERS_READOUT_CURRENT, SCALERS_READOUT_NEXT : SCALERS_READOUT;
+
+ -- etrax_reg
+
+ type r_register_array is array(0 to R_REGISTERS_NUMBER) of std_logic_vector(31 downto 0);
+ signal r_register_i, r_register_buf_i : r_register_array;
+ type rw_register_array is array(0 to RW_REGISTERS_NUMBER) of std_logic_vector(31 downto 0);
+ signal rw_register_i : rw_register_array;
+ signal r_register_vector, r_register_out_buf : std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+ signal rw_register_vector : std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
+ signal internal_regio_addr_out_i : std_logic_vector(15 downto 0);
+ signal internal_regio_read_enable_out_i : std_logic;
+ signal internal_regio_write_enable_out_i : std_logic;
+ signal internal_regio_data_in_i : std_logic_vector(31 downto 0);
+ signal internal_regio_data_out_i : std_logic_vector(31 downto 0);
+ signal internal_regio_dataready_out_i : std_logic;
+ signal internal_regio_no_more_data_out_i : std_logic;
+ signal internal_regio_write_ack_out_i : std_logic;
+ signal internal_regio_unknown_addr_out_i : std_logic;
----------------------------------------------------------------------------
--- Fakes
----------------------------------------------------------------------------
-trg_release <= '0';
-trg_error_pattern <= (others => '0');
-fee_trg_release <= '0';
-fee_trg_statusbits <= (others => '0');
-fee_data <= (others => '0');
-fee_data_local <= (others => '0');
-fee_data_write <= '0';
-fee_data_finished <= '0';
-timing_trigger_feedback <= '0';
-med_stat_debug <= (others => '0');
-my_address <= (others => '0');
-regio_common_stat_reg <= (others => '0');
-regio_stat_registers <= (others => '0');
-
--- RICH trigger connection
-RICH_TRIGGER_OUT <= '0';
-RICH_TIMING_OUT <= '0';
-RICH_RESERVED_OUT <= '0';
-RICH_CLK_OUT <= '0';
-
--- LEDs
-LED_YELLOW <= '0';
-LED_RED <= '0';
-LED_ORANGE <= '0';
-LED_GREEN <= '0';
-
--- SFP status LEDs
-TRB3_TX_LED <= '0';
-TRB3_RX_LED <= '0';
-TRB3_OK_LED <= '0';
-TRB2_TX_LED <= '0';
-TRB2_RX_LED <= '0';
-TRB2_OK_LED <= '0';
+ -- fpga1 to fpga2
+ signal slow_clk_out_i : std_logic;
+ signal lvl1_trigger_out_test : std_logic;
+ signal r_register_vector_sync : std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+ signal rw_register_vector_sync : std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
+ --beam structure
+ signal beam_structure_out_buf : std_logic_vector(1 downto 0);
+ signal structure_data_out_buf : std_logic_vector(31 downto 0);
+ signal start_veto_beam_structure_buf : std_logic_vector(23 downto 0);
+ signal read_structure_in_buf, read_structure_finished_out_buf, read_structure_start_in_buf : std_logic_vector(0 downto 0);
+ signal beam_inhibit_buf : std_logic;
+ --polarity
+ signal trigger_polarity_buf : std_logic_vector(TRIGGER_INPUTS_NUMBER - 1 downto 0);
+ --rw register from fpga2
+ signal down_rw_register_out_buf : std_logic_vector(31 downto 0);
+ signal down_address_out_buf : std_logic_vector(31 downto 0);
+ signal down_data_valid_out_buf : std_logic;
+
+ --rich signals
+ signal clk_40 : std_logic;
+ signal pll40_locked : std_logic;
+ signal apv_pulse_sync_a, apv_pulse_sync_b, apv_pulse_sync_c : std_logic;
+ signal apv_double_pulse : std_logic;
+
+ --ddr out signals
+ signal timing_fast_lvds, timing_fast_pecl, timing_mdca, timing_mdcb : std_logic_vector(3 downto 0);
+ signal multiplexer_to_ddr : std_logic_vector(7 downto 0);
+begin
+
+-------------------------------------------------------------------------------
+-- Emergency stop is RS1
+-------------------------------------------------------------------------------
+-- DIS1(2) <= 'Z';
+
---------------------------------------------------------------------------
-- Clock & Reset state machine
---------------------------------------------------------------------------
clk_en <= '1';
make_reset_via_network <= MED_STAT_OP(0*16 + 13);
-
- THE_PLL : pll_in200_out100
+
+-- pll_in200_out200_1: pll_in200_out200
+-- port map (
+-- clk => CLK_200_IN,
+-- clkop => clk_200,
+-- clkos => open,
+-- lock => clk_200_locked);
+-- clk_200 <= CLK_200_IN;
+
+ THE_PLL : pll_in200_out400
port map(
CLK => CLK_200_IN,
- CLKOP => clk_100,
- CLKOS => open,
+ CLKOP => clk_400,
+ CLKOS => clk_100,
LOCK => pll_locked
);
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"0EEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => CLK_200_IN, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_locked, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => make_reset_via_network, -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => reset_async, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i_100, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
+-- DLL_IN400_OUT100_INST: dll_in400_out100
+-- port map (
+-- clk => clk_400_tmp,
+-- aluhold => '0',
+-- clkop => open,
+-- clkos => clk_100,
+-- lock => dll_100_lock);
----------------------------------------------------------------------------
--- Media Interface
----------------------------------------------------------------------------
- THE_MEDIA_INTERFACE_0: trb_net16_med_scm_sfp_gbe
- generic map(
- SERDES_NUM => 0,
- EXT_CLOCK => c_NO,
- USE_200_MHZ => c_YES
- )
- port map(
- CLK => CLK_200_IN, -- raw 200MHz clock
- SYSCLK => clk_100, -- 100MHz from PLL
- RESET => reset_i_100,
- CLEAR => reset_async,
- CLK_EN => clk_en,
- --Internal Connection
- MED_DATA_IN => med_data_out,
- MED_PACKET_NUM_IN => med_packet_num_out,
- MED_DATAREADY_IN => med_dataready_out,
- MED_READ_OUT => med_read_in,
- MED_DATA_OUT => med_data_in,
- MED_PACKET_NUM_OUT => med_packet_num_in,
- MED_DATAREADY_OUT => med_dataready_in,
- MED_READ_IN => med_read_out,
- REFCLK2CORE_OUT => open,
- --SFP Connection
- SD_RXD_P_IN => FAKE_SERDES_RXD_P_IN, -- ignore
- SD_RXD_N_IN => FAKE_SERDES_RXD_N_IN, -- ignore
- SD_TXD_P_OUT => FAKE_SERDES_TXD_P_OUT, -- ignore
- SD_TXD_N_OUT => FAKE_SERDES_TXD_N_OUT, -- ignore
- SD_REFCLK_P_IN => FAKE_SERDES_REFCLK_P_IN, -- ignore
- SD_REFCLK_N_IN => FAKE_SERDES_REFCLK_N_IN, -- ignore
- SD_PRSNT_N_IN => '0', -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN => '0', -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT => open, -- SFP disable
- -- Status and control port
- STAT_OP => med_stat_op,
- CTRL_OP => med_ctrl_op,
- STAT_DEBUG => open,
- CTRL_DEBUG => open
- );
+ DLL_IN400_OUT200_INST: dll_in400_out200
+ port map (
+ clk => clk_400,
+ aluhold => '0',
+ clkop => clk_400_tmp,
+ clkos => clk_200,
+ lock => dll_200_lock);
+
+
+
+
+-------------------------------------------------------------------------------
+ -- RICH
+-------------------------------------------------------------------------------
+
+ RICH_40MHz: pll_in200_out40
+ port map (
+ clk => CLK_200_IN,
+ clkop => clk_40,
+ clkos => open,
+ lock => pll40_locked);
+
+ RICH_CLK_OUT <= clk_40;
+
+ RICH_APV_FIRST_PULSE: edge_to_pulse
+ port map (
+ clock => clk_40,
+ en_clk => '1',
+ signal_in => rw_register_i(0)(30),
+ pulse => apv_pulse_sync_a);
+
+ MAKE_APV_DOUBLE_PULSE : process (clk_40, reset_i_100)
+ begin
+ if rising_edge(clk_40) then
+ if reset_i_100 = '1' then
+ apv_pulse_sync_b <= '0';
+ apv_pulse_sync_c <= '0';
+ apv_double_pulse <= '0';
+ else
+ apv_pulse_sync_b <= apv_pulse_sync_a;
+ apv_pulse_sync_c <= apv_pulse_sync_b;
+ apv_double_pulse <= apv_pulse_sync_a or apv_pulse_sync_c;
+ end if;
+ end if;
+ end process MAKE_APV_DOUBLE_PULSE;
+
+ RICH_TRIGGER_OUT <= apv_double_pulse;
+
+
+ GLOBAL_RESET: process(clk_100)
+ begin
+ if rising_edge(clk_100) then
+ if global_reset_cnt < x"100e" then
+ global_reset_cnt <= global_reset_cnt + 1;
+ reset_i_100 <= '1';
+ elsif global_reset_cnt = x"100e" then
+ reset_i_100 <= FFC(16); --0
+ global_reset_cnt <= x"100e";
+ else
+ reset_i_100 <= FFC(16);
+ global_reset_cnt <= global_reset_cnt;
+ end if;
+ end if;
+ end process GLOBAL_RESET;
---------------------------------------------------------------------------
--- TrbNet Endpoint
+-- Unused Ports
---------------------------------------------------------------------------
+-- FFC <= (others => 'Z');
+ DIS1 <= (others => 'Z');
+ DIS2 <= (others => 'Z');
+ RS1 <= (others => 'Z');
+ RS2 <= (others => 'Z');
- THE_ENDPOINT: trb_net16_endpoint_hades_full_handler
- generic map(
- REGIO_NUM_STAT_REGS => NUM_STAT_REGS,
- REGIO_NUM_CTRL_REGS => NUM_CTRL_REGS,
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- REGIO_INIT_ADDRESS => REGIO_INIT_ADDRESS,
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
- REGIO_INIT_ENDPOINT_ID => REGIO_ENDPOINT_ID,
- REGIO_COMPILE_VERSION => x"0000",
- REGIO_HARDWARE_VERSION => x"51000000",
- REGIO_USE_1WIRE_INTERFACE => c_MONITOR,
- CLOCK_FREQUENCY => 100,
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 11,
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 2**11-520,
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 2**9-10
- )
- port map(
- CLK => clk_100,
- RESET => reset_i_100,
- CLK_EN => clk_en,
-
- MED_DATAREADY_OUT => med_dataready_out,
- MED_DATA_OUT => med_data_out,
- MED_PACKET_NUM_OUT => med_packet_num_out,
- MED_READ_IN => med_read_in,
- MED_DATAREADY_IN => med_dataready_in,
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out,
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
-
- -- LVL1 trigger APL
- TRG_TIMING_TRG_RECEIVED_IN => timing_trigger_feedback,
- LVL1_TRG_DATA_VALID_OUT => trg_data_valid,
- LVL1_VALID_TIMING_TRG_OUT => trg_valid_timing,
- LVL1_VALID_NOTIMING_TRG_OUT=> trg_valid_notiming,
- LVL1_INVALID_TRG_OUT => trg_invalid,
- LVL1_TRG_TYPE_OUT => trg_type,
- LVL1_TRG_NUMBER_OUT => trg_number,
- LVL1_TRG_CODE_OUT => trg_code,
- LVL1_TRG_INFORMATION_OUT => trg_information,
- LVL1_INT_TRG_NUMBER_OUT => trg_int_trg_number,
-
- -- FEE Port
- FEE_TRG_RELEASE_IN(0) => fee_trg_release,
- FEE_TRG_STATUSBITS_IN => fee_trg_statusbits,
- FEE_DATA_IN => fee_data,
- FEE_DATA_WRITE_IN(0) => fee_data_write,
- FEE_DATA_FINISHED_IN(0) => fee_data_finished,
- FEE_DATA_ALMOST_FULL_OUT(0)=> fee_data_almost_full,
-
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => regio_common_stat_reg,
- REGIO_COMMON_CTRL_REG_OUT => regio_common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => regio_common_stat_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => regio_common_ctrl_strobe,
-
- REGIO_STAT_REG_IN => regio_stat_registers, --start 0x80
- REGIO_CTRL_REG_OUT => regio_ctrl_registers, --start 0xc0
- REGIO_STAT_STROBE_OUT => regio_stat_strobe,
- REGIO_CTRL_STROBE_OUT => regio_ctrl_strobe,
-
- --following ports only used when using internal data port
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => open,
- ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks
- );
+ TEST_LINE(31) <= clk_100;
+ TEST_LINE(30) <= lvl2_trbnet_busy_in_i;
+ TEST_LINE(29) <= lvl1_trbnet_busy_in_i;
+ TEST_LINE(28) <= ipu_data_out_i(31);
+ TEST_LINE(27) <= ipu_dataready_out_i;
+ TEST_LINE(26) <= lvl1_trigger_out_i;
+ TEST_LINE(25) <= lvl1_triggbox_busy_in_i;
+ TEST_LINE(24) <= lvl1_triggbox_busy_out_i;
+ TEST_LINE(23 downto 20) <= lvl1_triggbox_code_out_i;
+ TEST_LINE(19 downto 16) <= r_register_i(0)(23 downto 20);
+ TEST_LINE(15) <= reset_i_100;
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
--- D000 spi status register
--- D001 spi ctrl register
--- D100 - D13F spi memory
-
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 2,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", others => x"0000"),
- PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0)
+
+-------------------------------------------------------------------------------
+-- trigger logic
+-------------------------------------------------------------------------------
+
+ INPUT_ENABLE_A: if TRIGGER_INPUTS_NUMBER = 32 or TRIGGER_INPUTS_NUMBER < 32 generate
+ input_enable_in_i(TRIGGER_INPUTS_NUMBER-1 downto 0) <= rw_register_i(3)(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ end generate INPUT_ENABLE_A;
+
+ INPUT_ENABLE_B: if TRIGGER_INPUTS_NUMBER > 32 generate
+ input_enable_in_i(31 downto 0) <= rw_register_i(3);
+ ts_gating_disable_in_i(31 downto 0) <= rw_register_i(5);
+ trigger_out_en_in_i(31 downto 0) <= rw_register_i(7);
+ input_enable_in_i(TRIGGER_INPUTS_NUMBER-1 downto 32) <= rw_register_i(4)(TRIGGER_INPUTS_NUMBER-32-1 downto 0);
+ ts_gating_disable_in_i(TRIGGER_INPUTS_NUMBER-1 downto 32) <= rw_register_i(6)(TRIGGER_INPUTS_NUMBER-32-1 downto 0);
+ trigger_out_en_in_i(TRIGGER_INPUTS_NUMBER-1 downto 32) <= rw_register_i(8)(TRIGGER_INPUTS_NUMBER-32-1 downto 0);
+ end generate INPUT_ENABLE_B;
+
+ DOWNSCALE_DELAY_REGISTERS_INPUT_GENERATE: for i in 0 to TRIGGER_INPUTS_NUMBER -1 generate
+ downscale_register_in_i((i+1)*4-1 downto i*4) <= rw_register_i((i/8)+9)(((i mod 8)+1)*4-1 downto (i mod 8)*4);
+ delay_trigger_register_in_i((i+1)*4-1 downto i*4) <= rw_register_i((i/8)+17)(((i mod 8)+1)*4-1 downto (i mod 8)*4);
+ end generate DOWNSCALE_DELAY_REGISTERS_INPUT_GENERATE;
+
+ delay_large_trigger_register_in_i <= rw_register_i(29) & rw_register_i(28) & rw_register_i(27);
+
+ WIDTH_REGISTERS_INPUT_GENERATE: for i in 0 to TRIGGER_INPUTS_NUMBER -1 + 9 generate
+ --width_register_in_i((i+1)*4-1 downto i*4) <= rw_register_i((i/8)+25)(((i mod 8)+1)*4-1 downto (i mod 8)*4);
+ width_register_large_in_i((i+1)*4-1 downto i*4) <= rw_register_i((i/8)+30)(((i mod 8)+1)*4-1 downto (i mod 8)*4);
+ end generate WIDTH_REGISTERS_INPUT_GENERATE;
+
+ SCALERS_SLOW_CTS_MODE: if CTS_MODE = 0 generate
+ SCALERS_REGISTERS: for i in 0 to SCALERS_NUMBER-1 generate
+ r_register_i(i+8) <= scaler_out_i((i+1)*32-1 downto i*32);
+ end generate SCALERS_REGISTERS;
+ end generate SCALERS_SLOW_CTS_MODE;
+
+ SCALERS_FAST_CTS_MODE: if CTS_MODE = 1 generate
+ SCALERS_REGISTERS: for i in 0 to SCALERS_NUMBER-1 generate --+ 14 + 1 generate
+ r_register_i(i+8) <= scaler_out_i((i+1)*32-1 downto i*32);--saved_scalers_in_i((i+1)*32-1 downto i*32);
+ end generate SCALERS_REGISTERS;
+ end generate SCALERS_FAST_CTS_MODE;
+
+
+
+ THE_DDR2_BUSSES : ddr2_busses --to sample incoming data and select inputs
+ generic map (
+ TRIGGER_INPUTS_NUMBER => TRIGGER_INPUTS_NUMBER)
+ port map (
+ RESET => reset_i_100,
+ CLK => clk_200,
+ EDGE_CLK => clk_400,
+ TRIG_IN => TRIG_IN,
+ TRIG_OUT => trigger_in, --to cts trigger logic
+ FAST_LVDS_TIMING_IN => timing_fast_lvds,
+ FAST_PECL_TIMING_IN => timing_fast_pecl,
+ FAST_MDCA_TIMING_IN => timing_mdca,
+ FAST_MDCB_TIMING_IN => timing_mdcb,
+ MULTIPLEXER_IN => multiplexer_to_ddr,
+ LVDS_TIMING_OUT(9 downto 0) => LVDS_OUT(9 downto 0),
+ LVDS_TIMING_OUT(11 downto 10) => LVDS_OUT(14 downto 13),
+ PECL_TIMING_OUT => PECL_OUT,
+ START_VETO_STRUCTURE_OUT => start_veto_beam_structure_buf,
+ TRIG_CNTRL_IN => rw_register_i(27)(7 downto 0));
+
+ THE_CTS_TRIGGER_LOGIC: cts_trigger_logic
+ generic map (
+ TRIGGER_INPUTS_NUMBER => TRIGGER_INPUTS_NUMBER,
+ TRIGGER_OUTPUTS_NUMBER => TRIGGER_OUTPUTS_NUMBER,
+ CTS_NUMBER_IPU_DATA => CTS_NUMBER_IPU_DATA,
+ SCALERS_NUMBER => SCALERS_NUMBER,
+ VECTOR_WIDTH => VECTOR_WIDTH,
+ CTS_MODE => CTS_MODE,
+ RATE_MARKERS_NUMBER => RATE_MARKERS_NUMBER
)
- port map(
- CLK => clk_100,
- RESET => reset_i_100,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- --Bus Handler (SPI CTRL)
- BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
- BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
- BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
- BUS_ADDR_OUT(0*16) => spictrl_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
- BUS_DATAREADY_IN(0) => spictrl_ack,
- BUS_WRITE_ACK_IN(0) => spictrl_ack,
- BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
- BUS_UNKNOWN_ADDR_IN(0) => '0',
- --Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(1) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
- BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
- BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
- BUS_DATAREADY_IN(1) => spimem_ack,
- BUS_WRITE_ACK_IN(1) => spimem_ack,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- STAT_DEBUG => open
- );
+ port map (
+ CLK => clk_200,--CLK_200_IN,--clk_100,
+ HIGH_FREQ_CLK => clk_400,
+ CLK_100 => clk_100,
+ RESET => reset_i_100,
+ EMERGENCY_STOP => DIS1(2),
+ TRIGGER_IN => trigger_in,--TRIG_IN(TRIGGER_INPUTS_NUMBER-1 downto 0),
+ INPUT_ENABLE_IN => input_enable_in_i,
+ DOWNSCALE_REGISTER_IN => downscale_register_in_i,
+ DELAY_TRIGGER_REGISTER_IN => delay_trigger_register_in_i,
+ DELAY_LARGE_TRIGGER_REGISTER_IN => delay_large_trigger_register_in_i,
+ WIDTH_REGISTER_IN => width_register_in_i,
+ WIDTH_REGISTER_LARGE_IN => width_register_large_in_i,
+ TS_GATING_DISABLE_IN => ts_gating_disable_in_i,
+ TRIGGER_OUT_EN_IN => trigger_out_en_in_i,
+ MULTIPLEXER_SELECT_IN => rw_register_i(2)(27 downto 0),
+ MULTIPLEXER_OUT => multiplexer_to_ddr,
+-- MULTIPLEXER_OUT(3 downto 2) => LVDS_OUT(11 downto 10),
+ SCALER_OUT => scaler_out_i,
+ SCALERS_FINISHED_IN => scalers_finished,
+ SEND_SCALERS_OUT => send_scalers_i,
+ BEAM_INHIBIT_IN => beam_inhibit_buf,--LVDS_IN,--'0',
+ BEAM_START => LVDS_IN,
+ NO_TIMING_OUT => no_timing_out_i,
+ LVL1_LOCAL_BUSY_IN => lvl1_busy_out_i,
+ LVL1_TRBNET_BUSY_IN => lvl1_trbnet_busy_in_i,
+ LVL1_TRIGGER_ACCEPTED_IN => lvl1_trigger_out_i,
+ LVL1_TRIGGER_CODE_OUT => lvl1_trigger_code_out_i,
+ LVL1_TRIGGER_TAG_OUT => lvl1_trigger_tag_out_i,
+ LVL1_RND_NUMBER_OUT => lvl1_rnd_number_out_i,
+ LVL1_TRIGGER_OUT => lvl1_trigger_out_i,
+ LVL1_BUSY_OUT => open,
+ LVL2_TRBNET_BUSY_IN => lvl2_trbnet_busy_in_i,
+ LVL2_LOCAL_BUSY_IN => lvl2_busy_out_i,
+ LVL2_TRIGGER_OUT => lvl2_trigger_out_i,
+ LVL2_TRIGGER_CODE_OUT => lvl2_trigger_code_out_i,
+ LVL2_TRIGGER_TAG_OUT => lvl2_trigger_tag_out_i,
+ LVL2_RND_NUMBER_OUT => lvl2_rnd_number_out_i,
+
+ TRIGBOX_LVL1_TRIGGER_INFO_OUT => open,
+ TOKEN_IN => token_in_i,
+ DATA_OUT => data_out_i,
+ DATA_VALID_OUT => data_valid_out_i,
+ TOKEN_OUT => token_out_i,
+ SAVE_SCALERS_OUT => save_scalers_out_i,
+ SAVED_SCALERS_IN => saved_scalers_in_i,
+ FAST_TRIGGER_OUT_LVDS => timing_fast_lvds,
+ FAST_TRIGGER_OUT_PECL => timing_fast_pecl,
+ MDCA_TRIGGER_OUT => timing_mdca,
+ MDCB_TRIGGER_OUT => timing_mdcb,
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
- THE_SPI_MASTER: spi_master
- port map(
- CLK_IN => clk_100,
- RESET_IN => reset_i_100,
- -- Slave bus
- BUS_READ_IN => spictrl_read_en,
- BUS_WRITE_IN => spictrl_write_en,
- BUS_BUSY_OUT => spictrl_busy,
- BUS_ACK_OUT => spictrl_ack,
- BUS_ADDR_IN(0) => spictrl_addr,
- BUS_DATA_IN => spictrl_data_in,
- BUS_DATA_OUT => spictrl_data_out,
- -- SPI connections
- SPI_CS_OUT => SPI_CS_OUT,
- SPI_SDI_IN => SPI_SO_IN,
- SPI_SDO_OUT => SPI_SI_OUT,
- SPI_SCK_OUT => SPI_CLK_OUT,
- -- BRAM for read/write data
- BRAM_A_OUT => spi_bram_addr,
- BRAM_WR_D_IN => spi_bram_wr_d,
- BRAM_RD_D_OUT => spi_bram_rd_d,
- BRAM_WE_OUT => spi_bram_we,
- -- Status lines
- STAT => open
- );
+ HIGH_RATE_MARKERS_OUT => open,--r_register_i(71)(23 downto 16),
+ LOW_RATE_MARKERS_OUT => open,--r_register_i(71)(7 downto 0),
+ HIGH_RATE_THRESHOLD_IN => rw_register_i(33)(31 downto 24),
+ LOW_RATE_THRESHOLD_IN => rw_register_i(33)(23 downto 16),
+ BEAM_STRUCTURE_OUT => beam_structure_out_buf,
- -- data memory for SPI accesses
- THE_SPI_MEMORY: spi_databus_memory
- port map(
- CLK_IN => clk_100,
- RESET_IN => reset_i_100,
- -- Slave bus
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_ACK_OUT => spimem_ack,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
- -- state machine connections
- BRAM_ADDR_IN => spi_bram_addr,
- BRAM_WR_D_OUT => spi_bram_wr_d,
- BRAM_RD_D_IN => spi_bram_rd_d,
- BRAM_WE_IN => spi_bram_we,
- -- Status lines
- STAT => open
+ TRIGGER_POLARITY => trigger_polarity_buf,
+ TRIGGER_LOGIC_CTRL_IN_0 => rw_register_i(0),
+ TRIGGER_LOGIC_CTRL_IN_1 => rw_register_i(1),
+ TRIGGER_LOGIC_CTRL_IN_2 => rw_register_i(35),
+ TRIGGER_LOGIC_DEBUG_OUT_0 => r_register_i(0),
+ TRIGGER_LOGIC_DEBUG_OUT_1 => r_register_i(1),
+ TRIGGER_LOGIC_DEBUG_OUT_2 => r_register_i(2)(4 downto 0)
);
+
+ r_register_i(3) <= trigger_polarity_buf(31 downto 0);
+ r_register_i(2)((TRIGGER_INPUTS_NUMBER - 32 - 1 + 5) downto 5) <= trigger_polarity_buf(TRIGGER_INPUTS_NUMBER - 1 downto 32);
+
+
+ THE_CTS_FPGA1_TO_FPGA2: cts_fpga1_to_fpga2
+ generic map (
+ LVL1_SIZE_OF_DATA_BUS_OUT => LVL1_SIZE_OF_DATA_BUS_OUT,
+ LVL2_SIZE_OF_DATA_BUS_OUT => LVL2_SIZE_OF_DATA_BUS_OUT
+ )
+ port map (
+ RESET => reset_i_100,
+ CLK => clk_100,
+ SLOW_CLK_OUT => slow_clk_out_i,
+ DATA_IN => ipu_data_out_i,
+ LVL1_CTS_DATA_ACK_OUT => ipu_ready_in_i,
+ LVL1_DATA_VALID_IN => ipu_dataready_out_i,
+ LVL1_FINISHED_IN => lvl2_finished,
+ LVL1_TRIGGER_TAG_IN => lvl1_trigger_tag_out_i,
+ LVL1_RND_CODE_IN => lvl1_rnd_number_out_i,
+ LVL1_CODE_IN => lvl1_trigger_code_out_i,
+ LVL1_TRIGGER_IN => lvl1_trigger_out_i,
+ LVL1_TRIGGER_OUT => FFC(17),
+ LVL1_DATA_OUT => FFC(LVL1_SIZE_OF_DATA_BUS_OUT-1 downto 0),
+ LVL1_DATA_VALID_OUT => FFC(18),
+ LVL2_TRIGGER_TAG_IN => (others => '0'),--lvl2_trigger_tag_out_i,
+ LVL2_RND_CODE_IN => (others => '0'),--lvl2_rnd_number_out_i,
+ LVL2_CODE_IN => (others => '0'),--lvl2_trigger_code_out_i,
+ LVL2_TRIGGER_IN => '0',--lvl2_trigger_out_i,
+ LVL2_TRIGGER_OUT => open,
+ LVL2_DATA_OUT => open,--FFC(LVL1_SIZE_OF_DATA_BUS_OUT+LVL2_SIZE_OF_DATA_BUS_OUT-1 downto LVL1_SIZE_OF_DATA_BUS_OUT),
+ LVL2_DATA_VALID_OUT => open,--FFC(19),
+ IP_TABLE_IN => (others => '0'),--rw_register_i(33)(15 downto 0),
+ EVENTS_NUMBER_IN => (others => '0'),--rw_register_i(34)(23 downto 0),
+ LVL1_INFO_IN => rw_register_i(36)(15 downto 0),
+ CTS_FPGA1_TO_FPGA2_DEBUG_OUT => open);
+-- FFC(LVL1_SIZE_OF_DATA_BUS_OUT+LVL2_SIZE_OF_DATA_BUS_OUT-1 downto LVL1_SIZE_OF_DATA_BUS_OUT) <= (others => '0');
+
+-- FFC(19) <= '0';
+ FFC(20) <= slow_clk_out_i;
+-- FFC(20) <= clk_100;
+ FFC(21) <= 'Z'; --for lvl1 busy
+ FFC(22) <= 'Z'; --for lvl2 busy
+ FFC(16) <= 'Z';
+-- THE_TRIGGER_LOGIC : cts_trigger_logic
+-- generic map (
+-- TRIGGER_INPUTS_NUMBER => TRIGGER_INPUTS_NUMBER,
+-- CTS_NUMBER_IPU_DATA => CTS_NUMBER_IPU_DATA,
+-- SCALERS_NUMBER => SCALERS_NUMBER,
+-- CTS_MODE => CTS_MODE)
+-- port map (
+-- CLK => clk_100,
+-- HIGH_FREQ_CLK => CLK_200,
+-- RESET => reset_i_100,
+-- TRIGGER_IN => TRIG_IN(TRIGGER_INPUTS_NUMBER-1 downto 0),
+-- INPUT_ENABLE_IN => input_enable_in_i,
+-- DOWNSCALE_REGISTER_IN => downscale_register_in_i,
+-- DELAY_TRIGGER_REGISTER_IN => delay_trigger_register_in_i,
+-- WIDTH_REGISTER_IN => width_register_in_i,
+-- TS_GATING_DISABLE_IN => ts_gating_disable_in_i,
+-- TRIGGER_OUT_EN_IN => trigger_out_en_in_i,
+-- MULTIPLEXER_SELECT_IN => rw_register_i(7)(15 downto 0),
+-- MULTIPLEXER_OUT => multiplexer_out_i,
+-- TRIGGER_LOGIC_CTRL_IN => rw_register_i(0),
+-- SCALER_OUT => scaler_out_i,
+-- BEAM_INHIBIT_IN => '0',
+-- NO_TIMING_OUT => no_timing_out_i,
+-- LVL1_BUSY_IN => lvl1_triggbox_busy_in_i,
+-- LVL1_TRIGGER_ACCEPTED_IN => lvl1_trigger_out_i,
+-- LVL1_TRIGGER_CODE_OUT => lvl1_triggbox_code_out_i,
+-- LVL1_TRIGGER_OUT => lvl1_triggbox_trigger_i,
+-- LVL1_BUSY_OUT => lvl1_triggbox_busy_out_i,
+-- TRIGGER_LOGIC_DEBUG_OUT => r_register_i(0),
+-- IPU_DATA_IN => ipu_data_in_i,
+-- IPU_DATA_VALID_IN => ipu_data_valid_in_i,
+-- TOKEN_IN => token_in_i,
+-- DATA_OUT => data_out_i,
+-- DATA_VALID_OUT => data_valid_out_i,
+-- TOKEN_OUT => token_out_i,
+-- SAVE_SCALERS_OUT => save_scalers_out_i,
+-- SAVED_SCALERS_IN => saved_scalers_in_i
+-- );
+ ipu_data_valid_in_i <= '0';
----------------------------------------------------------------------------
--- Reboot FPGA
----------------------------------------------------------------------------
- PROC_REBOOT: process (clk_100, reset_i_100)
- begin
- if reset_i_100 = '1' then
- PROGRAMN_OUT <= '1';
- delayed_restart_fpga <= '0';
- restart_fpga_counter <= x"FFF";
- elsif rising_edge(clk_100) then
- PROGRAMN_OUT <= not delayed_restart_fpga;
- delayed_restart_fpga <= '0';
- if regio_common_ctrl_reg(15) = '1' then
- restart_fpga_counter <= x"000";
- elsif restart_fpga_counter /= x"FFF" then
- restart_fpga_counter <= restart_fpga_counter + 1;
- if restart_fpga_counter >= x"F00" then
- delayed_restart_fpga <= '1';
- end if;
- end if;
+ ADO_TTL(6) <= 'Z';
+ ADO_TTL(7) <= 'Z';
+
+-- ADO_TTL(9 downto 8) <= multiplexer_out_i;
+
+ ADO_TTL(13 downto 10) <= lvl1_trigger_code_out_i;
+
+ SEND_ASYNC_LVL1_TRIGGER : process (clk_100, reset_i_100)
+ begin
+ if rising_edge(clk_100) then
+ if reset_i_100 = '1' or lvl1_trbnet_busy_in_i = '1' then
+ ADO_TTL(16) <= '0';
+ elsif lvl1_trigger_out_i = '1' then
+ ADO_TTL(16) <= '1';
end if;
- end process;
+ end if;
+ end process SEND_ASYNC_LVL1_TRIGGER;
----------------------------------------------------------------------------
--- Unused Ports
----------------------------------------------------------------------------
- FFC <= (others => 'Z');
- DIS1 <= (others => 'Z');
- DIS2 <= (others => 'Z');
- RS1 <= (others => 'Z');
- RS2 <= (others => 'Z');
----------------------------------------------------------------------------
--- Debug
----------------------------------------------------------------------------
- proc_testline : process(clk_100)
- begin
- if rising_edge(clk_100) then
- TEST_LINE(30 downto 0) <= (others => '0');
+
+ OLD_CTS_REAL_CTS_SIMPLE_CONNECTION : process (clk_100, reset_i_100)
+ begin
+ if rising_edge(clk_100) then
+ if reset_i_100 = '1' then
+ lvl1_trbnet_busy_in_i <= '0';
+ lvl2_trbnet_busy_in_i <= '0';
+ else
+ lvl1_trbnet_busy_in_i <= FFC(21);
+ lvl2_trbnet_busy_in_i <= FFC(22);
end if;
- end process;
+ end if;
+ end process OLD_CTS_REAL_CTS_SIMPLE_CONNECTION;
- TEST_LINE(31) <= clk_100;
+ ------------------------------------------------------------------------------
+ -- trigg box readout
+ ------------------------------------------------------------------------------
+
+ data_version_readout <= x"0" & rw_register_i(2)(31 downto 28);
+ THE_CTS_READOUT : cts_readout
+ generic map (
+ CTS_TYPE => CTS_TYPE)
+ port map (
+ CLK => clk_100,
+ RESET => reset_i_100,
+ DATA_READY_IN => data_valid,
+ DATA_IN => data_readout,
+ SEND_DATA_TOKEN_OUT => token_in_i,
+ RECEIVED_DATA_TOKEN_IN => token_out_i,
+ LVL1_BUSY_OUT => lvl1_busy_out_i,
+ LVL1_TRBNET_TRIGGER_IN => lvl1_trigger_out_i,--lvl1_timing_trigger_out_i, --lvl1_trbnet_trigger, --without trbnet tmp
+-- !!!!!!!!!!!!!!!!!!
+ LVL1_TAG_IN => lvl1_trigger_tag_out_i,
+ LVL1_CODE_IN => lvl1_trigger_code_out_i,
+ LVL1_FINISHED_OUT => lvl1_finished,
+ LVL2_TRIGGER_IN => '0',
+ LVL2_FINISHED_OUT => lvl2_finished,
+ LVL2_BUSY_OUT => lvl2_busy_out_i,
+ IPU_READY_IN => ipu_ready_in_i,--without trbnet tmp
+---- !!!!!!
+ IPU_DATAREADY_OUT => ipu_dataready_out_i,
+ IPU_DATA_OUT => ipu_data_out_i,
+ DEBUG_REGISTER_00 => r_register_i(4),
+ DEBUG_REGISTER_01 => r_register_i(5),
+ DEBUG_REGISTER_02 => r_register_i(6),
+ DATA_VERSION => data_version_readout);
+-- fee_trg_release <= lvl1_finished;
+-- lvl2_finished
+
+ -------------------------------------------------------------------------
+ -- sendig all data registers when calib trigger
+ -------------------------------------------------------------------------
+
+ DATA_READOUT_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => clk_100,
+ RESET => data_readout_cntr_rst,
+ COUNT_OUT => data_readout_cntr,
+ UP_IN => data_readout_cntr_up,
+ DOWN_IN => '0');
+
+ SCALERS_READOUT_CLK : process (clk_100, reset_i_100)
+ begin
+ if rising_edge(clk_100) then
+ if reset_i_100 = '1' then
+ SCALERS_READOUT_CURRENT <= IDLE;
+ data_readout_cntr_up <= '0';
+ data_readout_cntr_rst <= '1';
+ data_readout <= (others => '0');
+ data_valid <= '0';
+ data_readout_cntr_int <= conv_integer(data_readout_cntr(7 downto 0));
+ scalers_finished <= '0';
+ else
+ SCALERS_READOUT_CURRENT <= SCALERS_READOUT_NEXT;
+ data_readout_cntr_up <= data_readout_cntr_up_fsm;
+ data_readout_cntr_rst <= data_readout_cntr_rst_fsm;
+ data_readout <= data_readout_fsm;
+ data_valid <= data_valid_fsm;
+ data_readout_cntr_int <= conv_integer(data_readout_cntr(7 downto 0));
+ scalers_finished <= scalers_finished_fsm;
+ end if;
+ end if;
+ end process SCALERS_READOUT_CLK;
+
+ SCALERS_READOUT_PROC : process (clk_100)
+ begin
+ data_readout_cntr_up_fsm <= '0';
+ data_readout_cntr_rst_fsm <= '1';
+ data_readout_fsm <= data_out_i;
+ data_valid_fsm <= data_valid_out_i;
+ scalers_finished_fsm <= '0';
+
+ case (SCALERS_READOUT_CURRENT) is
+
+ when IDLE =>
+ if send_scalers_i = '1' then
+ data_readout_cntr_up_fsm <= '1';
+ data_readout_cntr_rst_fsm <= '0';
+ SCALERS_READOUT_NEXT <= SCALERS_READOUT_RW_A;
+ else
+ SCALERS_READOUT_NEXT <= IDLE;
+ end if;
+
+ when SCALERS_READOUT_RW_A =>
+ data_readout_cntr_up_fsm <= '1';
+ data_readout_cntr_rst_fsm <= '0';
+ SCALERS_READOUT_NEXT <= SCALERS_READOUT_RW_B;
+
+ when SCALERS_READOUT_RW_B =>
+ data_valid_fsm <= '1';
+ data_readout_cntr_up_fsm <= '1';
+ data_readout_cntr_rst_fsm <= '0';
+ data_readout_fsm <= rw_register_i(data_readout_cntr_int);
+ if data_readout_cntr = RW_REGISTERS_NUMBER then
+ SCALERS_READOUT_NEXT <= SCALERS_READOUT_RESET_A;
+ else
+ SCALERS_READOUT_NEXT <= SCALERS_READOUT_RW_B;
+ end if;
+
+ when SCALERS_READOUT_RESET_A =>
+ data_valid_fsm <= '0';
+ SCALERS_READOUT_NEXT <= SCALERS_READOUT_RESET_B;
+
+ when SCALERS_READOUT_RESET_B =>
+ data_valid_fsm <= '0';
+ data_readout_cntr_up_fsm <= '1';
+ data_readout_cntr_rst_fsm <= '0';
+ SCALERS_READOUT_NEXT <= SCALERS_READOUT_R_A;
+ when SCALERS_READOUT_R_A =>
+ data_readout_cntr_up_fsm <= '1';
+ data_readout_cntr_rst_fsm <= '0';
+ SCALERS_READOUT_NEXT <= SCALERS_READOUT_R_B;
+
+ when SCALERS_READOUT_R_B =>
+ data_valid_fsm <= '1';
+-- data_readout_fsm <= r_register_i(data_readout_cntr_int);
+ data_readout_fsm <= r_register_buf_i(data_readout_cntr_int);
+ data_readout_cntr_up_fsm <= '1';
+ data_readout_cntr_rst_fsm <= '0';
+ if data_readout_cntr = R_REGISTERS_NUMBER then
+ SCALERS_READOUT_NEXT <= SCALERS_READOUT_FINISHED;
+ else
+ SCALERS_READOUT_NEXT <= SCALERS_READOUT_R_B;
+ end if;
+
+ when SCALERS_READOUT_FINISHED =>
+ scalers_finished_fsm <= '1';
+ SCALERS_READOUT_NEXT <= IDLE;
+
+ when others =>
+ SCALERS_READOUT_NEXT <= IDLE;
+
+ end case;
+ end process SCALERS_READOUT_PROC;
+
+
+-------------------------------------------------------------------------------
+-- registers
+-------------------------------------------------------------------------------
+
+ -- internal_regio_addr_out_i <= x"A0" & down_address_out_buf;
+
+ THE_TRBNET_ETRAX_REG_INTERFACE : etrax_reg_mem
+ generic map (
+ RW_REGISTERS_NUMBER => RW_REGISTERS_NUMBER,
+ R_REGISTERS_NUMBER => R_REGISTERS_NUMBER,
+ SCALERS_NUMBER => SCALERS_NUMBER,
+ ENABLE_ETRAX_RW_INTERFACE => ENABLE_ETRAX_RW_INTERFACE)
+ port map (
+ CLK => clk_100,
+ RESET => reset_i_100,
+ ETRAX_DATA_BUS_E => FS_PE(9 downto 8),
+ RW_REGISTER_OUT => rw_register_vector,
+ R_REGISTER_IN => r_register_vector,
+ R_REGISTER_OUT => r_register_out_buf,
+ R_REGISTER_IN_SAVE_1S_IN => save_scalers_out_i,
+ SAVED_SCALERS_OUT => saved_scalers_in_i,
+ REGIO_ADDR_IN => down_address_out_buf(15 downto 0), --internal_regio_addr_out_i,
+ REGIO_READ_ENABLE_IN => '0', --internal_regio_read_enable_out_i,
+ REGIO_WRITE_ENABLE_IN => down_data_valid_out_buf, --internal_regio_write_enable_out_i,
+ REGIO_DATA_IN => down_rw_register_out_buf,
+ REGIO_DATA_OUT => open,
+ REGIO_DATAREADY_OUT => open,
+ REGIO_NO_MORE_DATA_OUT => open,
+ REGIO_WRITE_ACK_OUT => open,
+ REGIO_UNKNOWN_ADDR_OUT => open,
+ DEBUG_REGISTER_OO => r_register_i(7));
+
+ REWRITE_R_REGISTER : for i in 1 to R_REGISTERS_NUMBER generate
+ r_register_vector(32*i-1 downto 32*(i-1)) <= r_register_i(i-1);
+ r_register_buf_i(i-1) <= r_register_out_buf(32*i-1 downto 32*(i-1));
+ -- buf -- for registers which are send in the data
+ end generate REWRITE_R_REGISTER;
+
+ REWRITE_RW_REGISTER : for i in 1 to RW_REGISTERS_NUMBER generate
+ rw_register_i(i-1) <= rw_register_vector(32*i-1 downto 32*(i-1));
+ end generate REWRITE_RW_REGISTER;
+
+ LED_GREEN <= '1';
+ LED_ORANGE <= '0';
+ LED_RED <= '1';
+ LED_YELLOW <= '0';
+ PROGRAMN_OUT <= '1';
+
+
+
+ -----------------------------------------------------------------------------
+ -- beam structure
+ -----------------------------------------------------------------------------
+
+
+ THE_CTS_BEAM_STRUCTURE: cts_beam_structure
+ generic map (
+ START_SAMPLE_NUMBER => 500,
+ HOW_MANY_HISTOGRAMS => 25)
+ port map (
+ RESET => reset_i_100,
+ TRIGGER_CLK => clk_200,--CLK_200_IN,
+ LOCAL_CLK => clk_100,
+ START_TIME_OFFSET_IN => rw_register_i(6),--(others => '0'),
+ START_TIME_SAMPLE_IN => rw_register_i(8),--x"0000000A",
+ START_BEAM_IN => LVDS_IN,
+ BEAM_INHIBIT_LENGTH_IN => rw_register_i(26),
+ BEAM_INHIBIT_OUT => beam_inhibit_buf,--open,
+ BEAM_STRUCTURE_SIGNAL_IN => beam_structure_out_buf,
+ BEAM_START_VETO_STRUCKTURE_IN(1 downto 0) => beam_structure_out_buf,
+ BEAM_START_VETO_STRUCKTURE_IN(25 downto 2) => start_veto_beam_structure_buf,
+ STRUCTURE_DATA_OUT => structure_data_out_buf,
+ READ_STRUCTURE_IN => read_structure_in_buf(0),
+ READ_STRUCTURE_FINISHED_OUT => read_structure_finished_out_buf(0),
+ READ_STRUCTURE_START_IN => read_structure_start_in_buf(0),
+ CTS_BEAM_STRUCTURE_DEBUG => open);
+
+ LVDS_OUT(12) <= beam_inhibit_buf;
+
+ -----------------------------------------------------------------------------
+ -- simple data transport
+ -----------------------------------------------------------------------------
+
+ MORE_FLIP_FLOPS_FREQ : process (clk_100)
+ begin
+ if rising_edge(clk_100) then
+ r_register_vector_sync <= r_register_out_buf;--r_register_vector;
+ rw_register_vector_sync <= rw_register_vector;
+ end if;
+ end process MORE_FLIP_FLOPS_FREQ;
+
+ THE_CTS_SIMPLE_DATA_TRANSPORT: cts_simple_data_transport
+ generic map (
+ UP_WIDTH => 4,
+ DOWN_WIDTH => 2,
+ UP_RW_REGISTERS_NUMBER => RW_REGISTERS_NUMBER,
+ UP_R_REGISTERS_NUMBER => R_REGISTERS_NUMBER,
+ UP_SPECIAL_REGISTERS_NUMBER => 1,
+ DOWN_RW_REGISTERS_NUMBER => 1,--RW_REGISTERS_NUMBER,
+ DOWN_R_REGISTERS_NUMBER => 1,
+ DOWN_SPECIAL_REGISTERS_NUMBER => 1,
+ UP_CLK_SELECT => 0,
+ FPGA_TYPE => 0)
+ port map (
+ RESET => reset_i_100,
+ CLK => clk_100,
+ DOWN_RW_REGISTER_OUT => open,--
+ DOWN_R_REGISTER_OUT => open,--DOWN_R_REGISTER_OUT,
+ DOWN_SPECIAL_REGISTER_OUT => open,--DOWN_SPECIAL_REGISTER_OUT,
+ DOWN_ADDRESS_OUT => open,--
+ DOWN_DATA_VALID_OUT => open,--
+ DOWN_DATA_OUT => open,--DOWN_DATA_OUT,
+
+ UP_RW_REGISTER_IN => rw_register_vector_sync,
+ UP_R_REGISTER_IN => r_register_vector_sync,
+ UP_SPECIAL_REGISTER_IN => structure_data_out_buf,
+ UP_SPECIAL_REGISTER_FINISHED_IN => read_structure_finished_out_buf,
+ UP_START_READ_STRUCTURE_OUT => read_structure_start_in_buf,
+ UP_RD_EN_STRUCTURE_OUT => read_structure_in_buf,
+ UP_CLK_OUT => open,
+ UP_CLK_IN => slow_clk_out_i,
+ UP_DATA_OUT => FFC(11 downto 8),
+ UP_DATA_VALID_OUT => FFC(19),
+
+ DOWN_CLK_IN => FFC(15),--DOWN_CLK_IN,
+ DOWN_DATA_IN => FFC(13 downto 12),--DOWN_DATA_IN,
+ DOWN_DATA_VALID_IN => FFC(14),--DOWN_DATA_VALID_IN,
+ RW_ADDRESS_OUT => down_address_out_buf,
+ RW_DATA_OUT => down_rw_register_out_buf,
+ RW_DATA_VALID_OUT => down_data_valid_out_buf
+ );
+
end architecture;
--- /dev/null
+#!/usr/bin/perl
+###########################################
+# Script file to run the flow
+#
+###########################################
+#
+# Command line for synplify_pro
+#
+
+
+use Data::Dumper;
+
+use warnings;
+use strict;
+
+#my $lattice_path = '/opt/lattice/ispLEVER8.0/isptools/';
+#my $lattice_path = '/opt/lattice/ispLEVER8.0/isptools/';
+my $lattice_path = '/opt/lattice/diamond/1.3/';
+#my $lattice_path = '/opt/lattice/diamond/1.3/';
+#my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/';
+#my $synplify_path = '/opt/synplicity/D-2009.12/bin/';
+#my $synplify_path = '/opt/synplicity/D-2010.03/bin/';
+#my $synplify_path = '/opt/synplicity/D-2010.03-SP1-1/bin/';
+#my $synplify_path = '/opt/synplicity/fpga_e201009sp2/bin/';
+my $synplify_path = '/opt/synplicity/fpga_e201103/bin/';
+#my $synplify_path = '/opt/synplicity/fpga_e201103/bin/';
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}="27000\@lxcad01.gsi.de";
+
+
+my $TOPNAME="cts_fpga1";
+
+my $FAMILYNAME="LatticeSCM";
+my $DEVICENAME="LFSCM3GA40EP1";
+my $PACKAGE="FFBGA1020";
+my $SPEEDGRADE="7";
+
+
+#create full lpf file
+#system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+#system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+#my $c=$synplify_path."synplify_pro_oem -batch $TOPNAME".".prj";
+#my $c="$synplify_path/bin/synplify_pro -Pro -prj $TOPNAME".".prj";
+my $c="$synplify_path/synplify_premier_dp -batch $TOPNAME".".prj";
+#my $c="$synplify_path/bin/synpwrap -Pro -prj $TOPNAME".".prj";
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+#if ($r) {
+#$c="cat $TOPNAME.srr";
+#system($c);
+#exit 129;
+#}
+
+foreach (@a)
+{
+ if(/\@E:/)
+ {
+ $c="cat $TOPNAME.srr";
+ system($c);
+ print "bdabdhsadbhjasdhasldhbas";
+ exit 129;
+ }
+}
+#if (0){
+
+$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de";
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+
+system("rm $TOPNAME.ncd");
+
+#$c=qq|$lattice_path/ispfpga/bin/lin/par -w -y -l 4 -i 15 "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |;
+#$c=qq|$lattice_path/ispfpga/bin/lin/par -f $TOPNAME.p2t "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |;
+$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -sp 7 "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# TWR Timing Report
+#$c=qq|$lattice_path/ispfpga/bin/lin/tg "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|;
+execute($c);
+
+#$c=q| perl -ne '$in=1 if(/Report Summary/); print if($in==1); $in=0 if(/All preferences were met./)' | . "$TOPNAME.twr.setup";
+#execute($c);
+
+
+chdir "..";
+
+exit;
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+ $op = "" if(!$op);
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+
+ return $r;
+
+}
--- /dev/null
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.all;
+use STD.TEXTIO.all;
+use IEEE.STD_LOGIC_TEXTIO.all;
+-- use work.support.all;
+--library UNISIM;
+--use UNISIM.VCOMPONENTS.all;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+use work.version.all;
+
+ENTITY cts_fpga1_tb IS
+END cts_fpga1_tb;
+--simulate at lest for 100 us
+ARCHITECTURE behavior OF cts_fpga1_tb IS
+
+ component cts_fpga1
+ port (
+ CLK_200_IN : in std_logic;
+ ADO_CLKOUT : out std_logic;
+ RESET_FPGA_1 : in std_logic;
+ ADDON_RESET : in std_logic;
+ ADO_TTL : inout std_logic_vector(46 downto 0);
+ FS_PE : inout std_logic_vector(9 downto 8);
+ FFC : inout std_logic_vector(22 downto 0);
+ TRIG_IN : in std_logic_vector(63 downto 0);
+ LVDS_OUT : out std_logic_vector(14 downto 0);
+ LVDS_IN : in std_logic;
+ PECL_OUT : out std_logic_vector(2 downto 0);
+ RICH_CLK_OUT : out std_logic;
+ RICH_RESERVED_OUT : out std_logic;
+ RICH_TIMING_OUT : out std_logic_vector(0 downto 0);
+ RICH_TRIGGER_OUT : out std_logic;
+ SPI_CLK_OUT : out std_logic;
+ SPI_CS_OUT : out std_logic;
+ SPI_SI_OUT : out std_logic;
+ SPI_SO_IN : in std_logic;
+ PROGRAMN_OUT : out std_logic;
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ TRB2_OK_LED : out std_logic;
+ TRB2_RX_LED : out std_logic;
+ TRB2_TX_LED : out std_logic;
+ TRB3_OK_LED : out std_logic;
+ TRB3_RX_LED : out std_logic;
+ TRB3_TX_LED : out std_logic;
+ TRB2_LOS : out std_logic;
+ TRB2_MOD : inout std_logic_vector(2 downto 0);
+ TRB2_TX_DIS : out std_logic;
+ TRB3_LOS : out std_logic;
+ TRB3_MOD : inout std_logic_vector(2 downto 0);
+ TRB3_TX_DIS : out std_logic;
+ FAKE_SERDES_RXD_P_IN : in std_logic;
+ FAKE_SERDES_RXD_N_IN : in std_logic;
+ FAKE_SERDES_TXD_P_OUT : out std_logic;
+ FAKE_SERDES_TXD_N_OUT : out std_logic;
+ FAKE_SERDES_REFCLK_P_IN : in std_logic;
+ FAKE_SERDES_REFCLK_N_IN : in std_logic;
+ ONEWIRE_MONITOR_IN : in std_logic;
+ RS1 : out std_logic_vector(3 downto 0);
+ RS2 : out std_logic_vector(3 downto 0);
+ DIS1 : inout std_logic_vector(2 downto 0);
+ DIS2 : out std_logic_vector(2 downto 0);
+ TEST_LINE : out std_logic_vector(31 downto 0));
+ end component;
+
+ component cts_fpga2
+ port (
+ CLK_100_IN : in std_logic;
+ CLK_125_IN : in std_logic;
+ RESET_FPGA_2 : in std_logic;
+ ADDON_RESET : in std_logic;
+ ADO_LV : inout std_logic_vector(61 downto 0);
+ FFC : inout std_logic_vector(22 downto 0);
+ LED_GBE_OK : out std_logic;
+ LED_GBE_RX : out std_logic;
+ LED_GBE_TX : out std_logic;
+ LED_TRB_OK : out std_logic;
+ LED_TRB_RX : out std_logic;
+ LED_TRB_TX : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ SFP_DATA_TX : out std_logic_vector(3 downto 0);
+ SFP_DATA_RX : in std_logic_vector(3 downto 0);
+ GBE_LOS : in std_logic;
+ GBE_MOD : inout std_logic_vector(2 downto 0);
+ GBE_TX_DIS : out std_logic;
+ TRB_LOS : in std_logic;
+ TRB_MOD : inout std_logic_vector(2 downto 0);
+ TRB_TX_DIS : out std_logic;
+ SPI_CLK_OUT : out std_logic;
+ SPI_CS_OUT : out std_logic;
+ SPI_SI_OUT : out std_logic;
+ SPI_SO_IN : in std_logic;
+ PROGRAMN_OUT : out std_logic;
+ RAM_ADSCB : out std_logic;
+ RAM_ADSPB : out std_logic;
+ RAM_ADVB : out std_logic;
+ RAM_CE_2 : out std_logic;
+ RAM_CEB : out std_logic;
+ RAM_CLK : out std_logic;
+ RAM_GWB : out std_logic;
+ RAM_OEB : out std_logic;
+ RAM_A : out std_logic_vector(19 downto 0);
+ RAM_DQ : inout std_logic_vector(18 downto 1);
+ ONEWIRE_MONITOR_OUT : out std_logic;
+ TEMPSENS : inout std_logic;
+-- TX_K_OUT : out std_logic_vector(3 downto 0);
+-- RX_K_IN : in std_logic_vector(3 downto 0);
+-- RX_DATA_IN : in std_logic_vector(31 downto 0);
+-- TX_DATA_OUT : out std_logic_vector(31 downto 0);
+-- SIM_MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
+-- SIM_MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
+-- SIM_MED_DATAREADY_IN : in std_logic;
+-- SIM_MED_READ_OUT : out std_logic;
+-- SIM_MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0);
+-- SIM_MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0);
+-- SIM_MED_DATAREADY_OUT : out std_logic;
+-- SIM_MED_READ_IN : in std_logic;
+ TEST_LINE : out std_logic_vector(15 downto 0));
+ end component;
+
+ component cts_fpga1_test
+ port (
+ CLK_200_IN : in std_logic;
+ ADO_CLKOUT : out std_logic;
+ RESET_FPGA_1 : in std_logic;
+ ADDON_RESET : in std_logic;
+ ADO_TTL : inout std_logic_vector(46 downto 0);
+ FS_PE : inout std_logic_vector(9 downto 8);
+-- FFC : inout std_logic_vector(22 downto 0);
+ TRIG_IN : out std_logic_vector(63 downto 0);
+ LVDS_OUT : out std_logic_vector(14 downto 0);
+ LVDS_IN : in std_logic;
+ PECL_OUT : out std_logic_vector(2 downto 0);
+ RICH_CLK_OUT : out std_logic;
+ RICH_RESERVED_OUT : out std_logic;
+ RICH_TIMING_OUT : out std_logic_vector(0 downto 0);
+ RICH_TRIGGER_OUT : out std_logic;
+ SPI_CLK_OUT : out std_logic;
+ SPI_CS_OUT : out std_logic;
+ SPI_SI_OUT : out std_logic;
+ SPI_SO_IN : in std_logic;
+ PROGRAMN_OUT : out std_logic;
+ LED_GREEN : out std_logic;
+ LED_ORANGE : out std_logic;
+ LED_RED : out std_logic;
+ LED_YELLOW : out std_logic;
+ TRB2_OK_LED : out std_logic;
+ TRB2_RX_LED : out std_logic;
+ TRB2_TX_LED : out std_logic;
+ TRB3_OK_LED : out std_logic;
+ TRB3_RX_LED : out std_logic;
+ TRB3_TX_LED : out std_logic;
+ TRB2_LOS : out std_logic;
+ TRB2_MOD : inout std_logic_vector(2 downto 0);
+ TRB2_TX_DIS : out std_logic;
+ TRB3_LOS : out std_logic;
+ TRB3_MOD : inout std_logic_vector(2 downto 0);
+ TRB3_TX_DIS : out std_logic;
+ FAKE_SERDES_RXD_P_IN : in std_logic;
+ FAKE_SERDES_RXD_N_IN : in std_logic;
+ FAKE_SERDES_TXD_P_OUT : out std_logic;
+ FAKE_SERDES_TXD_N_OUT : out std_logic;
+ FAKE_SERDES_REFCLK_P_IN : in std_logic;
+ FAKE_SERDES_REFCLK_N_IN : in std_logic;
+ ONEWIRE_MONITOR_IN : in std_logic;
+ RS1 : out std_logic_vector(3 downto 0);
+ RS2 : out std_logic_vector(3 downto 0);
+ DIS1 : out std_logic_vector(2 downto 0);
+ DIS2 : out std_logic_vector(2 downto 0);
+ TEST_LINE : out std_logic_vector(31 downto 0));
+ end component;
+
+
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+ constant ENABLE_DMA: integer := 2;
+
+ component etrax_write_read_tb
+ port (
+ CLK : in std_logic;
+ REG_ADDRESS_IN : in std_logic_vector(31 downto 0);
+ REG_DATA_IN : in std_logic_vector(31 downto 0);
+ REG_MODE_IN : in std_logic_vector(15 downto 0);
+ REG_START_IN : in std_logic;
+ REG_FINISHED_OUT : out std_logic;
+ CLOCK_PORT_OUT : out std_logic;
+ DATA_PORT_OUT : out std_logic);
+ end component;
+-------------------------------------------------------------------------------
+-- real cts fpga1
+-------------------------------------------------------------------------------
+ signal CLK_200_IN : std_logic;
+ signal CLK_100_IN : std_logic;
+ signal ADO_CLKOUT : std_logic;
+ signal RESET_FPGA_1 : std_logic;
+ signal ADDON_RESET : std_logic;
+ signal RCTS_ADO_TTL : std_logic_vector(46 downto 0);
+ signal FS_PE : std_logic_vector(9 downto 8);
+ signal FFC : std_logic_vector(22 downto 0);
+ signal TRIG_IN : std_logic_vector(63 downto 0);
+ signal LVDS_OUT : std_logic_vector(14 downto 0);
+ signal LVDS_IN : std_logic;
+ signal PECL_OUT : std_logic_vector(2 downto 0);
+ signal RICH_CLK_OUT : std_logic;
+ signal RICH_RESERVED_OUT : std_logic;
+ signal RICH_TIMING_OUT : std_logic_vector(0 downto 0);
+ signal RICH_TRIGGER_OUT : std_logic;
+ signal SPI_CLK_OUT : std_logic;
+ signal SPI_CS_OUT : std_logic;
+ signal SPI_SI_OUT : std_logic;
+ signal SPI_SO_IN : std_logic;
+ signal PROGRAMN_OUT : std_logic;
+ signal LED_GREEN : std_logic;
+ signal LED_ORANGE : std_logic;
+ signal LED_RED : std_logic;
+ signal LED_YELLOW : std_logic;
+ signal TRB2_OK_LED : std_logic;
+ signal TRB2_RX_LED : std_logic;
+ signal TRB2_TX_LED : std_logic;
+ signal TRB3_OK_LED : std_logic;
+ signal TRB3_RX_LED : std_logic;
+ signal TRB3_TX_LED : std_logic;
+ signal TRB2_LOS : std_logic;
+ signal TRB2_MOD : std_logic_vector(2 downto 0);
+ signal TRB2_TX_DIS : std_logic;
+ signal TRB3_LOS : std_logic;
+ signal TRB3_MOD : std_logic_vector(2 downto 0);
+ signal TRB3_TX_DIS : std_logic;
+ signal ONEWIRE_MONITOR_IN : std_logic;
+ signal RS1 : std_logic_vector(3 downto 0);
+ signal RS2 : std_logic_vector(3 downto 0);
+ signal DIS1 : std_logic_vector(2 downto 0);
+ signal DIS2 : std_logic_vector(2 downto 0);
+ signal TEST_LINE : std_logic_vector(31 downto 0);
+
+-----------------------------------------------------------------------------
+-- real cts fpga2
+-----------------------------------------------------------------------------
+
+ signal FPGA2_CLK_100_IN : std_logic;
+ signal FPGA2_CLK_125_IN : std_logic;
+ signal FPGA2_RESET_FPGA_2 : std_logic;
+ signal FPGA2_ADDON_RESET : std_logic;
+ signal FPGA2_ADO_LV : std_logic_vector(61 downto 0);
+ signal FPGA2_FFC : std_logic_vector(22 downto 0);
+ signal FPGA2_LED_GBE_OK : std_logic;
+ signal FPGA2_LED_GBE_RX : std_logic;
+ signal FPGA2_LED_GBE_TX : std_logic;
+ signal FPGA2_LED_TRB_OK : std_logic;
+ signal FPGA2_LED_TRB_RX : std_logic;
+ signal FPGA2_LED_TRB_TX : std_logic;
+ signal FPGA2_LED_RED : std_logic;
+ signal FPGA2_LED_YELLOW : std_logic;
+ signal FPGA2_LED_GREEN : std_logic;
+ signal FPGA2_LED_ORANGE : std_logic;
+ signal FPGA2_SFP_DATA_TX : std_logic_vector(3 downto 0);
+ signal FPGA2_SFP_DATA_RX : std_logic_vector(3 downto 0);
+ signal FPGA2_GBE_LOS : std_logic;
+ signal FPGA2_GBE_MOD : std_logic_vector(2 downto 0);
+ signal FPGA2_GBE_TX_DIS : std_logic;
+ signal FPGA2_TRB_LOS : std_logic;
+ signal FPGA2_TRB_MOD : std_logic_vector(2 downto 0);
+ signal FPGA2_TRB_TX_DIS : std_logic;
+ signal FPGA2_SPI_CLK_OUT : std_logic;
+ signal FPGA2_SPI_CS_OUT : std_logic;
+ signal FPGA2_SPI_SI_OUT : std_logic;
+ signal FPGA2_SPI_SO_IN : std_logic;
+ signal FPGA2_PROGRAMN_OUT : std_logic;
+ signal FPGA2_RAM_ADSCB : std_logic;
+ signal FPGA2_RAM_ADSPB : std_logic;
+ signal FPGA2_RAM_ADVB : std_logic;
+ signal FPGA2_RAM_CE_2 : std_logic;
+ signal FPGA2_RAM_CEB : std_logic;
+ signal FPGA2_RAM_CLK : std_logic;
+ signal FPGA2_RAM_GWB : std_logic;
+ signal FPGA2_RAM_OEB : std_logic;
+ signal FPGA2_RAM_A : std_logic_vector(19 downto 0);
+ signal FPGA2_RAM_DQ : std_logic_vector(18 downto 1);
+ signal FPGA2_ONEWIRE_MONITOR_OUT : std_logic;
+ signal FPGA2_TEMPSENS : std_logic;
+ signal FPGA2_TX_K_OUT : std_logic_vector(3 downto 0);
+ signal FPGA2_RX_K_IN : std_logic_vector(3 downto 0);
+ signal FPGA2_RX_DATA_IN : std_logic_vector(31 downto 0);
+ signal FPGA2_TX_DATA_OUT : std_logic_vector(31 downto 0);
+ signal TX_DATA_OUT : std_logic_vector(31 downto 0);
+ signal FPGA2_TEST_LINE : std_logic_vector(15 downto 0);
+ signal SIM_MED_DATA_IN_CTS : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal SIM_MED_PACKET_NUM_IN_CTS : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal SIM_MED_DATAREADY_IN_CTS : std_logic;
+ signal SIM_MED_READ_OUT_CTS : std_logic;
+ signal SIM_MED_DATA_OUT_CTS : std_logic_vector(c_DATA_WIDTH-1 downto 0);
+ signal SIM_MED_PACKET_NUM_OUT_CTS : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal SIM_MED_DATAREADY_OUT_CTS : std_logic;
+ signal SIM_MED_READ_IN_CTS : std_logic;
+
+-------------------------------------------------------------------------------
+-- cts test entity
+-------------------------------------------------------------------------------
+ signal TEST_CLK_200_IN : std_logic;
+ signal TEST_ADO_CLKOUT : std_logic;
+ signal TEST_RESET_FPGA_1 : std_logic;
+ signal TEST_ADDON_RESET : std_logic;
+ signal TEST_ADO_TTL : std_logic_vector(46 downto 0);
+ signal TEST_FS_PE : std_logic_vector(9 downto 8);
+-- signal TEST_FFC : std_logic_vector(22 downto 0);
+ signal TEST_TRIG_IN : std_logic_vector(63 downto 0);
+ signal TEST_LVDS_OUT : std_logic_vector(14 downto 0);
+ signal TEST_LVDS_IN : std_logic;
+ signal TEST_PECL_OUT : std_logic_vector(2 downto 0);
+ signal TEST_RICH_CLK_OUT : std_logic;
+ signal TEST_RICH_RESERVED_OUT : std_logic;
+ signal TEST_RICH_TIMING_OUT : std_logic_vector(0 downto 0);
+ signal TEST_RICH_TRIGGER_OUT : std_logic;
+ signal TEST_SPI_CLK_OUT : std_logic;
+ signal TEST_SPI_CS_OUT : std_logic;
+ signal TEST_SPI_SI_OUT : std_logic;
+ signal TEST_SPI_SO_IN : std_logic;
+ signal TEST_PROGRAMN_OUT : std_logic;
+ signal TEST_LED_GREEN : std_logic;
+ signal TEST_LED_ORANGE : std_logic;
+ signal TEST_LED_RED : std_logic;
+ signal TEST_LED_YELLOW : std_logic;
+ signal TEST_TRB2_OK_LED : std_logic;
+ signal TEST_TRB2_RX_LED : std_logic;
+ signal TEST_TRB2_TX_LED : std_logic;
+ signal TEST_TRB3_OK_LED : std_logic;
+ signal TEST_TRB3_RX_LED : std_logic;
+ signal TEST_TRB3_TX_LED : std_logic;
+ signal TEST_TRB2_LOS : std_logic;
+ signal TEST_TRB2_MOD : std_logic_vector(2 downto 0);
+ signal TEST_TRB2_TX_DIS : std_logic;
+ signal TEST_TRB3_LOS : std_logic;
+ signal TEST_TRB3_MOD : std_logic_vector(2 downto 0);
+ signal TEST_TRB3_TX_DIS : std_logic;
+ signal TEST_FAKE_SERDES_RXD_P_IN : std_logic;
+ signal TEST_FAKE_SERDES_RXD_N_IN : std_logic;
+ signal TEST_FAKE_SERDES_TXD_P_OUT : std_logic;
+ signal TEST_FAKE_SERDES_TXD_N_OUT : std_logic;
+ signal TEST_FAKE_SERDES_REFCLK_P_IN : std_logic;
+ signal TEST_FAKE_SERDES_REFCLK_N_IN : std_logic;
+ signal TEST_ONEWIRE_MONITOR_IN : std_logic;
+ signal TEST_RS1 : std_logic_vector(3 downto 0);
+ signal TEST_RS2 : std_logic_vector(3 downto 0);
+ signal TEST_DIS1 : std_logic_vector(2 downto 0);
+ signal TEST_DIS2 : std_logic_vector(2 downto 0);
+ signal TEST_TEST_LINE : std_logic_vector(31 downto 0);
+
+ -----------------------------------------------------------------------------
+ -- signals
+ -----------------------------------------------------------------------------
+
+ signal cts_rw_mode : std_logic_vector(15 downto 0);
+ signal cts_address : std_logic_vector(31 downto 0);
+ signal cts_data : std_logic_vector(31 downto 0);
+ signal cts_rw_cts_start : std_logic;
+ signal cts_rw_cts_end : std_logic;
+
+
+BEGIN
+
+
+ real_cts: cts_fpga1
+ port map (
+ CLK_200_IN => CLK_200_IN,
+ ADO_CLKOUT => ADO_CLKOUT,
+ RESET_FPGA_1 => RESET_FPGA_1,
+ ADDON_RESET => ADDON_RESET,
+ ADO_TTL => RCTS_ADO_TTL,
+ FS_PE => FS_PE,
+ FFC => FFC,
+ TRIG_IN => TRIG_IN,
+ LVDS_OUT => LVDS_OUT,
+ LVDS_IN => LVDS_IN,
+ PECL_OUT => PECL_OUT,
+ RICH_CLK_OUT => RICH_CLK_OUT,
+ RICH_RESERVED_OUT => RICH_RESERVED_OUT,
+ RICH_TIMING_OUT => RICH_TIMING_OUT,
+ RICH_TRIGGER_OUT => RICH_TRIGGER_OUT,
+ SPI_CLK_OUT => SPI_CLK_OUT,
+ SPI_CS_OUT => SPI_CS_OUT,
+ SPI_SI_OUT => SPI_SI_OUT,
+ SPI_SO_IN => SPI_SO_IN,
+ PROGRAMN_OUT => PROGRAMN_OUT,
+ LED_GREEN => LED_GREEN,
+ LED_ORANGE => LED_ORANGE,
+ LED_RED => LED_RED,
+ LED_YELLOW => LED_YELLOW,
+ TRB2_OK_LED => TRB2_OK_LED,
+ TRB2_RX_LED => TRB2_RX_LED,
+ TRB2_TX_LED => TRB2_TX_LED,
+ TRB3_OK_LED => TRB3_OK_LED,
+ TRB3_RX_LED => TRB3_RX_LED,
+ TRB3_TX_LED => TRB3_TX_LED,
+ TRB2_LOS => TRB2_LOS,
+ TRB2_MOD => TRB2_MOD,
+ TRB2_TX_DIS => TRB2_TX_DIS,
+ TRB3_LOS => TRB3_LOS,
+ TRB3_MOD => TRB3_MOD,
+ TRB3_TX_DIS => TRB3_TX_DIS,
+ FAKE_SERDES_RXD_P_IN => '0',
+ FAKE_SERDES_RXD_N_IN => '1',
+ FAKE_SERDES_TXD_P_OUT => open,
+ FAKE_SERDES_TXD_N_OUT => open,
+ FAKE_SERDES_REFCLK_P_IN => '0',
+ FAKE_SERDES_REFCLK_N_IN => '1',
+ ONEWIRE_MONITOR_IN => ONEWIRE_MONITOR_IN,
+ RS1 => RS1,
+ RS2 => RS2,
+ DIS1 => DIS1,
+ DIS2 => DIS2,
+ TEST_LINE => TEST_LINE);
+
+ cts_fpga2_1: cts_fpga2
+ port map (
+ CLK_100_IN => FPGA2_CLK_100_IN,
+ CLK_125_IN => FPGA2_CLK_125_IN,
+ RESET_FPGA_2 => FPGA2_RESET_FPGA_2,
+ ADDON_RESET => FPGA2_ADDON_RESET,
+ ADO_LV => FPGA2_ADO_LV,
+ FFC => FPGA2_FFC,
+ LED_GBE_OK => FPGA2_LED_GBE_OK,
+ LED_GBE_RX => FPGA2_LED_GBE_RX,
+ LED_GBE_TX => FPGA2_LED_GBE_TX,
+ LED_TRB_OK => FPGA2_LED_TRB_OK,
+ LED_TRB_RX => FPGA2_LED_TRB_RX,
+ LED_TRB_TX => FPGA2_LED_TRB_TX,
+ LED_RED => FPGA2_LED_RED,
+ LED_YELLOW => FPGA2_LED_YELLOW,
+ LED_GREEN => FPGA2_LED_GREEN,
+ LED_ORANGE => FPGA2_LED_ORANGE,
+ SFP_DATA_TX => FPGA2_SFP_DATA_TX,
+ SFP_DATA_RX => FPGA2_SFP_DATA_RX,
+ GBE_LOS => FPGA2_GBE_LOS,
+ GBE_MOD => FPGA2_GBE_MOD,
+ GBE_TX_DIS => FPGA2_GBE_TX_DIS,
+ TRB_LOS => FPGA2_TRB_LOS,
+ TRB_MOD => FPGA2_TRB_MOD,
+ TRB_TX_DIS => FPGA2_TRB_TX_DIS,
+ SPI_CLK_OUT => FPGA2_SPI_CLK_OUT,
+ SPI_CS_OUT => FPGA2_SPI_CS_OUT,
+ SPI_SI_OUT => FPGA2_SPI_SI_OUT,
+ SPI_SO_IN => FPGA2_SPI_SO_IN,
+ PROGRAMN_OUT => FPGA2_PROGRAMN_OUT,
+ RAM_ADSCB => FPGA2_RAM_ADSCB,
+ RAM_ADSPB => FPGA2_RAM_ADSPB,
+ RAM_ADVB => FPGA2_RAM_ADVB,
+ RAM_CE_2 => FPGA2_RAM_CE_2,
+ RAM_CEB => FPGA2_RAM_CEB,
+ RAM_CLK => FPGA2_RAM_CLK,
+ RAM_GWB => FPGA2_RAM_GWB,
+ RAM_OEB => FPGA2_RAM_OEB,
+ RAM_A => FPGA2_RAM_A,
+ RAM_DQ => FPGA2_RAM_DQ,
+ ONEWIRE_MONITOR_OUT => FPGA2_ONEWIRE_MONITOR_OUT,
+ TEMPSENS => FPGA2_TEMPSENS,
+-- TX_K_OUT => FPGA2_TX_K_OUT,
+-- RX_K_IN => FPGA2_RX_K_IN,
+-- RX_DATA_IN => FPGA2_RX_DATA_IN,
+-- TX_DATA_OUT => FPGA2_TX_DATA_OUT,
+-- SIM_MED_DATA_IN => SIM_MED_DATA_IN_CTS ,
+-- SIM_MED_PACKET_NUM_IN => SIM_MED_PACKET_NUM_IN_CTS ,
+-- SIM_MED_DATAREADY_IN => SIM_MED_DATAREADY_IN_CTS ,
+-- SIM_MED_READ_OUT => SIM_MED_READ_OUT_CTS ,
+-- SIM_MED_DATA_OUT => SIM_MED_DATA_OUT_CTS ,
+-- SIM_MED_PACKET_NUM_OUT => SIM_MED_PACKET_NUM_OUT_CTS ,
+-- SIM_MED_DATAREADY_OUT => SIM_MED_DATAREADY_OUT_CTS ,
+-- SIM_MED_READ_IN => SIM_MED_READ_IN_CTS ,
+ TEST_LINE => FPGA2_TEST_LINE);
+
+ THE_CTS_FPGA1_TEST: cts_fpga1_test
+ port map (
+ CLK_200_IN => TEST_CLK_200_IN,
+ ADO_CLKOUT => TEST_ADO_CLKOUT,
+ RESET_FPGA_1 => TEST_RESET_FPGA_1,
+ ADDON_RESET => TEST_ADDON_RESET,
+ ADO_TTL => TEST_ADO_TTL,
+ FS_PE => TEST_FS_PE,
+-- FFC => TEST_FFC,
+ TRIG_IN => TEST_TRIG_IN,
+ LVDS_OUT => TEST_LVDS_OUT,
+ LVDS_IN => TEST_LVDS_IN,
+ PECL_OUT => TEST_PECL_OUT,
+ RICH_CLK_OUT => TEST_RICH_CLK_OUT,
+ RICH_RESERVED_OUT => TEST_RICH_RESERVED_OUT,
+ RICH_TIMING_OUT => TEST_RICH_TIMING_OUT,
+ RICH_TRIGGER_OUT => TEST_RICH_TRIGGER_OUT,
+ SPI_CLK_OUT => TEST_SPI_CLK_OUT,
+ SPI_CS_OUT => TEST_SPI_CS_OUT,
+ SPI_SI_OUT => TEST_SPI_SI_OUT,
+ SPI_SO_IN => TEST_SPI_SO_IN,
+ PROGRAMN_OUT => TEST_PROGRAMN_OUT,
+ LED_GREEN => TEST_LED_GREEN,
+ LED_ORANGE => TEST_LED_ORANGE,
+ LED_RED => TEST_LED_RED,
+ LED_YELLOW => TEST_LED_YELLOW,
+ TRB2_OK_LED => TEST_TRB2_OK_LED,
+ TRB2_RX_LED => TEST_TRB2_RX_LED,
+ TRB2_TX_LED => TEST_TRB2_TX_LED,
+ TRB3_OK_LED => TEST_TRB3_OK_LED,
+ TRB3_RX_LED => TEST_TRB3_RX_LED,
+ TRB3_TX_LED => TEST_TRB3_TX_LED,
+ TRB2_LOS => TEST_TRB2_LOS,
+ TRB2_MOD => TEST_TRB2_MOD,
+ TRB2_TX_DIS => TEST_TRB2_TX_DIS,
+ TRB3_LOS => TEST_TRB3_LOS,
+ TRB3_MOD => TEST_TRB3_MOD,
+ TRB3_TX_DIS => TEST_TRB3_TX_DIS,
+ FAKE_SERDES_RXD_P_IN => TEST_FAKE_SERDES_RXD_P_IN,
+ FAKE_SERDES_RXD_N_IN => TEST_FAKE_SERDES_RXD_N_IN,
+ FAKE_SERDES_TXD_P_OUT => TEST_FAKE_SERDES_TXD_P_OUT,
+ FAKE_SERDES_TXD_N_OUT => TEST_FAKE_SERDES_TXD_N_OUT,
+ FAKE_SERDES_REFCLK_P_IN => TEST_FAKE_SERDES_REFCLK_P_IN,
+ FAKE_SERDES_REFCLK_N_IN => TEST_FAKE_SERDES_REFCLK_N_IN,
+ ONEWIRE_MONITOR_IN => TEST_ONEWIRE_MONITOR_IN,
+ RS1 => TEST_RS1,
+ RS2 => TEST_RS2,
+ DIS1 => TEST_DIS1,
+ DIS2 => TEST_DIS2,
+ TEST_LINE => TEST_TEST_LINE);
+
+-------------------------------------------------------------------------------
+-- beam inhibit in
+-------------------------------------------------------------------------------
+-- DIS1(2) <= '1';
+-- cts_beam_inhibit : process
+-- begin
+ LVDS_IN <= TEST_LVDS_OUT(0);
+ DIS1(2) <= '0';
+-- wait for 180 us;
+-- LVDS_IN <= '1';
+-- wait for 1 us;
+-- end process;
+
+-------------------------------------------------------------------------------
+-- CTS TO ENDPOINT
+-------------------------------------------------------------------------------
+
+-- SIM_MED_DATA_IN_ENDPOINT <= SIM_MED_DATA_OUT_CTS ;
+-- SIM_MED_PACKET_NUM_IN_ENDPOINT <= SIM_MED_PACKET_NUM_OUT_CTS ;
+-- SIM_MED_DATAREADY_IN_ENDPOINT <= SIM_MED_DATAREADY_OUT_CTS ;
+-- SIM_MED_READ_IN_CTS <= SIM_MED_READ_OUT_ENDPOINT ;
+-- SIM_MED_DATA_IN_CTS <= SIM_MED_DATA_OUT_ENDPOINT ;
+-- SIM_MED_PACKET_NUM_IN_CTS <= SIM_MED_PACKET_NUM_OUT_ENDPOINT ;
+-- SIM_MED_DATAREADY_IN_CTS <= SIM_MED_DATAREADY_OUT_ENDPOINT ;
+-- SIM_MED_READ_IN_ENDPOINT <= SIM_MED_READ_OUT_CTS ;
+
+-------------------------------------------------------------------------------
+-- real cts clock
+-------------------------------------------------------------------------------
+ test_cts_clock_gclk : process
+ begin
+ TEST_CLK_200_IN <= '0';
+ wait for 2.3 ns;
+ TEST_CLK_200_IN <= '1';
+ wait for 2.3 ns;
+ end process;
+
+
+ cts_clock_gclk : process
+ begin
+ CLK_200_IN <= '0';
+ wait for 2.5 ns;
+ CLK_200_IN <= '1';
+ wait for 2.5 ns;
+ end process;
+
+ cts_clock_100gclk : process
+ begin
+ CLK_100_IN <= '0';
+ wait for 2.5 ns;
+ CLK_100_IN <= '1';
+ wait for 2.5 ns;
+ end process;
+
+ cts2_clock_100gclk : process
+ begin
+ FPGA2_CLK_100_IN <= '0';
+ wait for 5 ns;
+ FPGA2_CLK_100_IN <= '1';
+ wait for 5 ns;
+ end process;
+
+
+ FPGA2_FFC(20 downto 17) <= FFC(20 downto 17);
+ FPGA2_FFC(11 downto 0) <= FFC(11 downto 0);
+
+ FFC(15 downto 12) <= FPGA2_FFC(15 downto 12);
+
+ FFC(16) <= FPGA2_FFC(16);
+ FFC(22 downto 21) <= FPGA2_FFC(22 downto 21);
+
+-------------------------------------------------------------------------------
+-- real cts <-> old trb cts
+-------------------------------------------------------------------------------
+-- RCTS_ADO_TTL(6) <= CTS_ADO_TTL(6);
+-- RCTS_ADO_TTL(7) <= CTS_ADO_TTL(7);
+-- CTS_ADO_TTL(16) <= RCTS_ADO_TTL(16);
+-- CTS_ADO_TTL(13 downto 10) <= RCTS_ADO_TTL(13 downto 10);
+
+-- SEND_DIFF_TRIGG_RCTS: for i in 0 to 63 generate
+-- TRIG_IN(i) <= triggers(i mod 4);
+-- end generate SEND_DIFF_TRIGG_RCTS;
+
+ TRIG_IN <= TEST_TRIG_IN;
+-- TRIG_IN(39 downto 32) <= TEST_TRIG_IN_B(55 downto 48);
+
+-- SEND_DIFF_TRIGG_RCTS: for i in 0 to 15 generate
+-- TRIG_IN(i) <= '0';
+-- end generate SEND_DIFF_TRIGG_RCTS;
+
+-- SEND_DIFF_TRIGG_RCTSA: for i in 17 to 30 generate
+-- TRIG_IN(i) <= '0';
+-- end generate SEND_DIFF_TRIGG_RCTSA;
+
+-- TRIG_IN(16) <= triggers(0);
+-- TRIG_IN(31) <= triggers(0);
+ -----------------------------------------------------------------------------
+ -- real cts registers
+ -----------------------------------------------------------------------------
+
+ RCTS_THE_ETRAX_WRITE_READ_TB: etrax_write_read_tb
+ port map (
+ CLK => CLK_100_IN,
+ REG_ADDRESS_IN => cts_address,
+ REG_DATA_IN => cts_data,
+ REG_MODE_IN => cts_rw_mode,
+ REG_START_IN => cts_rw_cts_start,
+ REG_FINISHED_OUT => cts_rw_cts_end,
+ CLOCK_PORT_OUT => FS_PE(9),
+ DATA_PORT_OUT => FS_PE(8));
+
+ rcts_etrax_int_test: process
+ begin
+ wait for 50000 ns;
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000c0";
+ cts_data <= x"00004220";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000c1";
+ cts_data <= x"000c4000";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"200000c2";
+ cts_data <= x"00001005";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ --inputs enable
+ cts_address <= x"000000c3";
+ cts_data <= x"ffffffff";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+ --inputs enable
+ cts_address <= x"000000c4";
+ cts_data <= x"ffffffff";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+ --ts gating disable
+ cts_address <= x"000000c5";
+ cts_data <= x"ffffffff";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+ --ts gating disable
+ cts_address <= x"000000c6";
+ cts_data <= x"0000000A";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 900 ns; --wait for trb cts
+ --trigger out en
+ cts_address <= x"000000c7";
+ cts_data <= x"ffffffff";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ --
+ cts_address <= x"000000c8";
+ cts_data <= x"00000002";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+ --downscale
+ cts_address <= x"000000c9";
+ cts_data <= x"24313210";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+ --downscale
+ cts_address <= x"000000d0";
+ cts_data <= x"01234567";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ --downscale last
+ cts_address <= x"000000d1";
+ cts_data <= x"102030ff";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+ --delay
+ cts_address <= x"000000d2";
+ cts_data <= x"22334455";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+-- --delay last
+-- cts_address <= x"000000d9";
+-- cts_data <= x"99aabbcf";
+-- cts_rw_cts_start <= '1';
+-- wait on CLK_100_IN until cts_rw_cts_end = '1';
+-- wait for 30 ns;
+-- --width
+-- cts_address <= x"000000da";
+-- cts_data <= x"33445566";
+-- cts_rw_cts_start <= '1';
+-- wait on CLK_100_IN until cts_rw_cts_end = '1';
+-- wait for 30 ns;
+-- --width
+-- cts_address <= x"000000db";
+-- cts_data <= x"110022ff";
+-- cts_rw_cts_start <= '1';
+-- wait on CLK_100_IN until cts_rw_cts_end = '1';
+-- wait for 30 ns;
+-- --width
+-- cts_address <= x"000000dc";
+-- cts_data <= x"55ddeeff";
+-- cts_rw_cts_start <= '1';
+-- wait on CLK_100_IN until cts_rw_cts_end = '1';
+-- wait for 30 ns;
+ --width
+ cts_address <= x"000000dd";
+ cts_data <= x"000007ee";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000e1";
+ cts_data <= x"0f0a8c7a";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000e2";
+ cts_data <= x"00000001";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000e3";
+ cts_data <= x"00000001";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000e4";
+ cts_data <= x"00000700";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000e5";
+ cts_data <= x"00000000";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000e6";
+ cts_data <= x"00000000";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000e7";
+ cts_data <= x"44444444";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+--set large width
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000e8";
+ cts_data <= x"122334af";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000e9";
+ cts_data <= x"120034af";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000ea";
+ cts_data <= x"120034af";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000eb";
+ cts_data <= x"120034af";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ cts_rw_mode <= x"0000";
+ cts_address <= x"000000ec";
+ cts_data <= x"120034af";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+
+-- cts_rw_mode <= x"0000";
+-- cts_address <= x"000000c0";
+-- cts_data <= x"00002000";
+-- cts_rw_cts_start <= '1';
+-- wait on CLK_100_IN until cts_rw_cts_end = '1';
+-- wait for 30 ns;
+
+
+
+
+ --width last
+ cts_address <= x"000000e1";
+ cts_data <= x"aa11bbff";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+ --test read
+ cts_rw_mode <= x"8000";
+ cts_address <= x"000000d8";
+ cts_data <= x"aa11bbff";
+ cts_rw_cts_start <= '1';
+ wait on CLK_100_IN until cts_rw_cts_end = '1';
+ wait for 30 ns;
+
+ wait;
+ end process rcts_etrax_int_test;
+
+
+
+-------------------------------------------------------------------------------
+-- write read from etrax
+-------------------------------------------------------------------------------
+-- THE_ETRAX_WRITE_READ_TB: etrax_write_read_tb
+-- port map (
+-- CLK => VIRT_CLK,
+-- REG_ADDRESS_IN => address,
+-- REG_DATA_IN => data,
+-- REG_MODE_IN => rw_mode,
+-- REG_START_IN => rw_cts_start,
+-- REG_FINISHED_OUT => rw_cts_end,
+-- CLOCK_PORT_OUT => CTS_FS_PC(17),
+-- DATA_PORT_OUT => CTS_FS_PC(16));
+
+-- etrax_int_test: process
+-- begin
+
+
+ --trigger out en
+-- wait for 47000 ns;
+-- rw_mode <= x"0000";
+-- address <= x"000000c5";
+-- data <= x"00000020";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+
+-- --downscale 7
+-- rw_mode <= x"0000";
+-- address <= x"000000cd";
+-- data <= x"01234560";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+-- --width 7-0
+-- rw_mode <= x"0000";
+-- address <= x"000000d5";
+-- data <= x"ffcc8855";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+-- --width 15-8
+-- rw_mode <= x"0000";
+-- address <= x"000000d6";
+-- data <= x"ffcc8855";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+-- --width 23-16
+-- rw_mode <= x"0000";
+-- address <= x"000000d7";
+-- data <= x"ffcc8855";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+-- --width 31-24
+-- rw_mode <= x"0000";
+-- address <= x"000000d8";
+-- data <= x"ffcc8855";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+
+-- --out en 7-0
+-- rw_mode <= x"0000";
+-- address <= x"000000da";
+-- data <= x"ffffffff";
+-- --data <= x"00000000";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+-- --TS gating disable en 7-0
+-- rw_mode <= x"0000";
+-- address <= x"000000d9";
+-- data <= x"aaaaaaaa";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+
+
+-- --trigg control in
+-- rw_mode <= x"0000";
+-- address <= x"000000dc";
+-- data <= x"00000000"; --enable cal and internal generator
+---- data <= x"00002020"; --enable cal and internal generator
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+
+-- --
+-- rw_mode <= x"0000";
+-- address <= x"000000cc";
+-- data <= x"ffffffff";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+-- --
+
+-- rw_mode <= x"0000";
+-- address <= x"000000c9";
+-- data <= x"00000002";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+
+-- --
+-- rw_mode <= x"0000";
+-- address <= x"000000ca";
+-- data <= x"76543210";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+
+-- --
+-- rw_mode <= x"0000";
+-- address <= x"000000cb";
+-- data <= x"76543210";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+-- --
+
+
+
+-- wait for 300 ns;
+-- --
+-- rw_mode <= x"0000";
+-- address <= x"000000db";
+-- data <= x"00000707";
+-- rw_cts_start <= '1';
+-- wait on VIRT_CLK until rw_cts_end = '1';
+-- wait for 30 ns;
+-- --
+
+---- rw_mode <= x"0005";
+---- address <= x"000000c1";
+---- data <= x"5555aaaa";
+---- rw_cts_start <= '1';
+---- wait on VIRT_CLK until rw_cts_end = '1';
+---- wait for 30 ns;
+---- --
+---- rw_mode <= x"8005";
+---- address <= x"000000c1";
+---- data <= x"f000f00f";
+---- rw_cts_start <= '1';
+---- wait on VIRT_CLK until rw_cts_end = '1';
+---- wait for 30 ns;
+-- wait;
+-- end process etrax_int_test;
+
+-- endpoint_etrax_int_test: process
+-- begin
+
+-- --enable RPC scalers data
+-- endpoint_rw_mode <= x"0000";
+-- endpoint_address <= x"000000c0";
+-- endpoint_data <= x"00000001";
+-- endpoint_rw_cts_start <= '1';
+-- wait on VIRT_CLK until endpoint_rw_cts_end = '1';
+-- wait for 30 ns;
+-- wait;
+-- end process endpoint_etrax_int_test;
+
+
+-- THE_ENDPOINT_ETRAX_WRITE_READ_TB: etrax_write_read_tb
+-- port map (
+-- CLK => VIRT_CLK,
+-- REG_ADDRESS_IN => endpoint_address,
+-- REG_DATA_IN => endpoint_data,
+-- REG_MODE_IN => endpoint_rw_mode,
+-- REG_START_IN => endpoint_rw_cts_start,
+-- REG_FINISHED_OUT => endpoint_rw_cts_end,
+-- CLOCK_PORT_OUT => FS_PC(17),
+-- DATA_PORT_OUT => FS_PC(16));
+
+-- CTS_SDA <= '0';
+
+
+
+-- GENERATE_DUMMY_TRIGGER_SIGNALS: for i in 0 to 31 generate
+-- phsyical_trigger : process
+-- variable wait_time : integer :=0;
+-- begin
+-- wait for 3.3 ns;
+-- triggers(i) <= '0';
+-- wait for ((wait_time mod 2)*45*4+2*25+i*wait_time)*ns;
+-- triggers(i) <= '1';
+-- wait for ((wait_time mod 4 )*5+2*25-i)*ns;
+-- triggers(i) <= '0';
+-- wait for ((wait_time mod 7 )*45+2*25+i)*ns;
+-- triggers(i) <= '1';
+-- wait_time := wait_time*3/2 +1;
+-- wait for ((wait_time mod 3 )*5+2*25+i*wait_time)*ns;
+-- if wait_time > 500000 then
+-- wait_time := 0;
+-- else
+-- wait_time := wait_time;
+-- end if;
+-- end process;
+-- end generate GENERATE_DUMMY_TRIGGER_SIGNALS;
+
+-- CTS_VIR_TRIG <= triggers(0);
+-- CTS_VIR_TRIGB <= not triggers(0);
+
+-- SEND_DIFF_TRIGG_A: for i in 0 to 15 generate
+-- CTS_ADO_LVDS_IN(i*2) <= triggers(i);
+-- CTS_ADO_LVDS_IN(i*2+1) <= not triggers(i);
+-- end generate SEND_DIFF_TRIGG_A;
+
+-- SEND_DIFF_TRIGG_B: for i in 0 to 3 generate
+-- CTS_ADO_LVDS_IN(32+i*2) <= triggers(i+28);
+-- CTS_ADO_LVDS_IN(32+i*2+1) <= not triggers(i+28);
+-- end generate SEND_DIFF_TRIGG_B;
+
+-- SEND_DIFF_TRIGG_C: for i in 0 to 15 generate
+-- ADO_LVDS_IN(i*2) <= triggers(i);
+-- ADO_LVDS_IN(i*2+1) <= not triggers(i);
+-- end generate SEND_DIFF_TRIGG_C;
+
+-- CTS_ADO_TTL(0) <= '0'; --beam inhibit
+----CTS_ADO_TTL(21 downto 16) <= triggers(21 downto 16);
+-- CTS_ADO_TTL(29 downto 24) <= triggers(27 downto 22);
+
+-- clock_gclk : process
+-- begin
+-- VIRT_CLK <= '0';
+-- VIRT_CLKB <= '1';
+-- wait for 5 ns;
+-- VIRT_CLKB <= '0';
+-- VIRT_CLK <= '1';
+-- wait for 5 ns;
+-- end process;
+
+
+
+-- dsp : process
+-- begin
+-- DSP_ACK <= '1';
+-- DSP_HBG <= '1';
+-- wait for 20 ns;
+-- DSPDAT <= (others => 'Z');
+-- wait on VIRT_CLK until DSP_HBR = '0';
+-- wait for 8 ns;
+-- DSP_HBG <= '0';
+-- DSPDAT <= x"babeface";
+-- wait for 10 ns;
+-- DSP_ACK <= '1';
+-- wait on VIRT_CLK until DSP_HBR = '1';
+-- DSP_ACK <= '0';
+-- DSP_HBG <= '1';
+-- DSPDAT <= (others => 'Z');
+-- wait on VIRT_CLK until test_synch_00 = '1';
+-- wait on VIRT_CLK until DSP_HBR = '0';
+-- wait for 8 ns;
+-- DSP_HBG <= '0';
+-- wait until DSP_HBR = '1';
+-- DSP_HBG <= '1';
+-- wait;
+-- end process;
+-- -----------------------------------------------------------------------
+-- -- TLK
+-- -----------------------------------------------------------------------
+-- clock_tlk_clk : process
+-- begin
+-- TLK_CLK <= '0';
+-- wait for 5 ns;
+-- TLK_CLK <= '1';
+-- wait for 5 ns;
+-- end process;
+-- clock_tlk_rx_clk : process
+-- begin
+-- TLK_RX_CLK <= '0';
+-- wait for 5 ns;
+-- TLK_RX_CLK <= '1';
+-- wait for 5 ns;
+-- end process;
+---- RX_ER: process
+---- begin
+---- TLK_RX_ER <= '0';
+---- wait for 2200 ns;
+---- TLK_RX_ER <= '1';
+---- wait for 120 ns;
+---- end process;
+---- TLK_RXD <= TLK_TXD;
+-- TLK_RX_ER <= '0';
+-- CTS_TLK_RX_ER <= '0';
+---- TLK_RX_DV <= CTS_TLK_TX_EN;
+
+-- TLK_RX_DV <= not ( FPGA2_TX_K_OUT(3) or FPGA2_TX_K_OUT(2) );
+-- TLK_RXD <= FPGA2_TX_DATA_OUT(31 downto 16);
+
+-- CTS_TLK_RX_DV <= TLK_TX_EN;
+-- CTS_TLK_RXD <= TLK_TXD;
+-- SFP_LOS <= '0';
+-- CTS_SFP_LOS <= '0';
+-- -----------------------------------------------------------------------
+-- -- process check headers - number of words in event
+-- -----------------------------------------------------------------------
+
+---- valid_pulse: edge_to_pulse
+---- port map (
+---- clock => VIRT_CLK,
+---- en_clk => '1',
+---- signal_in => CTS_FS_PB(16),
+---- pulse => valid_pulse_i);
+---- not_valid <= CTS_FS_PB(16);
+---- not_valid_pulse: edge_to_pulse
+---- port map (
+---- clock => VIRT_CLK,
+---- en_clk => '1',
+---- signal_in => not_valid,
+---- pulse => not_valid_pulse_i);
+---- etrax_pulse: edge_to_pulse
+---- port map (
+---- clock => VIRT_CLK,
+---- en_clk => '1',
+---- signal_in => etrax_ready,
+---- pulse => etrax_ready_pulse);
+
+---- ckeck_header: process(VIRT_CLK,valid_pulse_i,etrax_ready_pulse )
+---- begin
+---- if rising_edge(VIRT_CLK) then
+---- if valid_pulse_i = '1' then
+---- save_lenght <= CTS_FS_PB(15 downto 0);
+---- compare_counter <= (others => '0');
+---- elsif etrax_ready_pulse = '1' then
+---- save_lenght <= save_lenght;
+---- compare_counter <= compare_counter + 1;
+---- else
+---- save_lenght <= save_lenght;
+---- compare_counter <= compare_counter;
+---- end if;
+---- end if;
+---- end process ckeck_header;
+---- wrong_lenght_of_event <= '1' when ((save_lenght /= compare_counter) and CTS_FS_PB(16) = '0') else '0';
+-- -----------------------------------------------------------------------
+-- -- TDC and etrax readout
+-- -----------------------------------------------------------------------
+-- TDC_OUT <= tdc_data_i;
+-- VIR_TRIG <= PECL_OUT(0);--CTS_ADO_TTL(36);
+-- VIR_TRIGB <= not PECL_OUT(0);--not CTS_ADO_TTL(36);
+-- TDC_DATA_CHANGE: process(REF_TDC_CLK, RESET_VIRT)
+-- begin
+-- if rising_edge(REF_TDC_CLK) then
+-- if RESET_VIRT = '1' then
+-- tdc_data_i <= x"00000000";
+-- else
+-- tdc_data_i <= tdc_data_i + 1;
+-- end if;
+-- end if;
+-- end process TDC_DATA_CHANGE;
+
+-- clock_tdcclk : process
+-- begin
+-- wait for 12 ns;
+-- loop
+-- REF_TDC_CLK <= '0';
+-- REF_TDC_CLKB <= '1';
+-- wait for 12.5 ns;
+-- REF_TDC_CLK <= '1';
+-- REF_TDC_CLKB <= '0';
+-- wait for 12.5 ns;
+-- end loop;
+-- end process;
+
+-- trigger_lvl1 : process
+-- variable valid_time : integer :=0;
+-- begin
+-- A_DATA_READY <= '0';
+-- B_DATA_READY <= '0';
+-- C_DATA_READY <= '0';
+-- D_DATA_READY <= '0';
+-- TOKEN_IN <= '0';
+-- wait on REF_TDC_CLK until TOKEN_OUT = '1';
+-- wait on REF_TDC_CLK until TOKEN_OUT = '0';
+-- wait for 10 ns;
+-- A_DATA_READY <= '1';
+-- wait for ((valid_time mod 2)*50*4+2*25)*ns;
+-- A_DATA_READY <= '0';
+-- B_DATA_READY <= '1';
+-- wait for ((valid_time mod 3 )*50*2+2*25)*ns;
+-- B_DATA_READY <= '0';
+-- C_DATA_READY <= '1';
+-- wait for ((valid_time mod 4 )*50+2*25)*ns;
+-- C_DATA_READY <= '0';
+-- D_DATA_READY <= '1';
+-- wait for ((valid_time mod 7 )*50+2*25)*ns;
+-- D_DATA_READY <= '0';
+-- wait for 0 ns;
+-- TOKEN_IN <= '1';
+-- wait for 50 ns;
+-- TOKEN_IN <= '0';
+-- valid_time := valid_time*3/2 +1;
+-- end process;
+
+-- ETRAX_HAS_NO_DMA: if ENABLE_DMA = 2 generate
+-- ETRAX_BUSY_PROC: process
+-- variable etrax_busy_time : integer :=0;
+-- begin
+-- FS_PB_17 <= '0';
+-- wait on VIRT_CLK until FS_PB(16) ='1';
+-- wait for 320 ns;
+-- FS_PB_17 <= '1';
+-- wait for 380 ns;
+-- wait on VIRT_CLK until etrax_busy ='0';
+-- etrax_busy_time := etrax_busy_time*3/2 +1;
+-- end process ETRAX_BUSY_PROC;
+
+-- end generate ETRAX_HAS_NO_DMA;
+
+-- ETRAX_HAS_DMA: if ENABLE_DMA = 1 generate
+-- ETRAX_BUSY_PROC: process
+-- variable etrax_busy_time : integer :=0;
+-- begin
+-- FS_PB_17 <= '0';
+-- wait on VIRT_CLK until FS_PB(16) ='1';
+-- wait for 20 ns;
+-- FS_PB_17 <= '1';
+-- wait for 680 ns;
+-- etrax_busy_time := etrax_busy_time*3/2 +1;
+-- end process ETRAX_BUSY_PROC;
+
+-- end generate ETRAX_HAS_DMA;
+
+-- WAIT_FOR_TRANSFER_END: process
+-- variable wait_int : integer range 0 to 65535;
+-- begin
+-- etrax_busy <= '0';
+-- wait on VIRT_CLK until FS_PB(16) ='1';
+-- etrax_busy <= '1';
+-- wait for 37*10 ns;
+-- end process WAIT_FOR_TRANSFER_END;
+
+-- -----------------------------------------------------------------------
+-- -- TDC and etrax readout
+-- -----------------------------------------------------------------------
+-- CTS_TDC_OUT <= tdc_data_i;--x"00000000";--tdc_data_i;
+-- cts_clock_tdcclk : process
+-- begin
+-- wait for 12 ns;
+-- loop
+-- CTS_REF_TDC_CLK <= '0';
+-- CTS_REF_TDC_CLKB <= '1';
+-- wait for 12.5 ns;
+-- CTS_REF_TDC_CLK <= '1';
+-- CTS_REF_TDC_CLKB <= '0';
+-- wait for 12.5 ns;
+-- end loop;
+-- end process;
+
+-- cts_trigger_lvl1 : process
+-- variable valid_time : integer :=0;
+-- begin
+-- CTS_A_DATA_READY <= '0';
+-- CTS_B_DATA_READY <= '0';
+-- CTS_C_DATA_READY <= '0';
+-- CTS_D_DATA_READY <= '0';
+-- CTS_TOKEN_IN <= '0';
+-- wait on CTS_REF_TDC_CLK until CTS_TOKEN_OUT = '1';
+-- wait on CTS_REF_TDC_CLK until CTS_TOKEN_OUT = '0';
+-- wait for 10 ns;
+-- CTS_A_DATA_READY <= '1';
+-- wait for ((valid_time mod 2)*50*3+2*25)*ns;
+-- CTS_A_DATA_READY <= '0';
+-- CTS_B_DATA_READY <= '1';
+-- wait for ((valid_time mod 3 )*50*2+2*25)*ns;
+-- CTS_B_DATA_READY <= '0';
+-- CTS_C_DATA_READY <= '1';
+-- wait for ((valid_time mod 5 )*50+2*25)*ns;
+-- CTS_C_DATA_READY <= '0';
+-- CTS_D_DATA_READY <= '1';
+-- wait for ((valid_time mod 7 )*50+2*25)*ns;
+-- CTS_D_DATA_READY <= '0';
+-- wait for 0 ns;
+-- CTS_TOKEN_IN <= '1';
+-- wait for 50 ns;
+-- CTS_TOKEN_IN <= '0';
+-- valid_time := valid_time*3/2 +1;
+-- end process;
+
+-- CTS_ETRAX_HAS_NO_DMA_CTS: if ENABLE_DMA = 2 generate
+-- CTS_ETRAX_BUSY_PROC: process
+-- variable etrax_busy_time : integer :=0;
+-- begin
+-- CTS_FS_PB_17 <= '0';
+-- wait on VIRT_CLK until CTS_FS_PB(16) ='1';
+-- wait for 620 ns;
+-- CTS_FS_PB_17 <= '1';
+-- wait for 680 ns;
+-- wait on VIRT_CLK until etrax_busy ='0';
+-- etrax_busy_time := etrax_busy_time*32/2 +1;
+-- end process CTS_ETRAX_BUSY_PROC;
+
+-- end generate CTS_ETRAX_HAS_NO_DMA_CTS;
+
+-- CTS_ETRAX_HAS_DMA_CTS: if ENABLE_DMA = 1 generate
+-- CTS_ETRAX_BUSY_PROC: process
+-- variable etrax_busy_time : integer :=0;
+-- begin
+-- CTS_FS_PB_17 <= '0';
+-- wait on VIRT_CLK until CTS_FS_PB(16) ='1';
+-- wait for 20 ns;
+-- CTS_FS_PB_17 <= '1';
+-- wait for 680 ns;
+-- etrax_busy_time := etrax_busy_time*3/2 +1;
+-- end process CTS_ETRAX_BUSY_PROC;
+
+-- end generate CTS_ETRAX_HAS_DMA_CTS;
+
+
+
+
+
+-- CTS_WAIT_FOR_TRANSFER_END: process
+-- variable wait_int : integer range 0 to 65535;
+-- begin
+-- etrax_busy <= '0';
+-- wait on VIRT_CLK until CTS_FS_PB(16) ='1';
+-- etrax_busy <= '1';
+-- wait for 37*10 ns;
+-- end process CTS_WAIT_FOR_TRANSFER_END;
+
+-- -----------------------------------------------------------------------
+-- -- DTU
+-- -----------------------------------------------------------------------
+---- clock_dtu : process
+---- begin
+---- wait for 34 ns;
+
+---- loop
+---- dtu_clk <= '0';
+---- wait for 50 ns;
+---- dtu_clk <= '1';
+---- wait for 50 ns;
+---- end loop;
+---- end process;
+---- ADO_TTL(0) <= lvl1_trig;
+---- ADO_TTL(8) <= lvl2_trig;
+---- ADO_TTL(7) <= 'Z';
+---- ADO_TTL(15) <= 'Z';
+---- -- LVL1_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl1_trig)
+---- -- begin
+---- -- if rising_edge(dtu_clk) then
+---- -- if RESET_VIRT = '0' then
+---- -- dtu_lvl1_tag <= x"00";
+---- -- elsif ADO_TTL(17) = '1' then
+---- -- dtu_lvl1_tag <= dtu_lvl1_tag +1;
+---- -- end if;
+---- -- end if;
+---- -- end process LVL1_TAG_COUNTER;
+---- LVL1_COUNT:process
+---- begin
+---- wait for 100 ns;
+---- dtu_lvl1_tag <= x"00";
+---- wait on dtu_clk until ADO_TTL(0) = '0';
+---- wait on dtu_clk until lvl1_trig = '1';
+---- wait for 500 ns;
+---- dtu_lvl1_tag <= dtu_lvl1_tag +1;
+---- loop
+---- wait on dtu_clk until ADO_TTL(0) = '1';
+---- -- wait for 1000 ns;
+---- dtu_lvl1_tag <= dtu_lvl1_tag +1;
+---- wait on dtu_clk until ADO_TTL(0) = '0';
+---- end loop;
+---- end process LVL1_COUNT;
+---- LVL2_COUNT:process
+---- begin
+---- wait for 100 ns;
+---- dtu_lvl2_tag <= x"00";
+---- wait on dtu_clk until ADO_TTL(2) = '0';
+---- loop
+---- -- wait on dtu_clk until ADO_TTL(2) = '1';
+---- wait on dtu_clk until lvl2_trig = '1';
+---- -- wait for 1000 ns;
+---- wait for 500 ns;
+---- dtu_lvl2_tag <= dtu_lvl2_tag +1;
+---- wait on dtu_clk until ADO_TTL(2) = '0';
+---- end loop;
+---- end process LVL2_COUNT;
+
+
+---- -- LVL2_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl2_trig)
+---- -- begin
+---- -- if rising_edge(dtu_clk) then
+---- -- if RESET_VIRT = '0' then
+---- -- dtu_lvl2_tag <= x"00";
+---- -- elsif lvl2_trig = '1' then
+---- -- dtu_lvl2_tag <= dtu_lvl2_tag +1;
+---- -- end if;
+---- -- end if;
+---- -- end process LVL2_TAG_COUNTER;
+---- -- ADO_TTL(20 downto 17) <= (others => 'Z');
+
+
+---- ADO_TTL(4) <= lvl1_trig;
+---- DTU_EMULATION_LVL1: process
+---- variable lvl1_randomize : integer := 100;
+---- begin
+---- ADO_TTL(1) <= '0';
+---- lvl1_trig <= '0';
+---- VIR_TRIG <= '0';
+---- VIR_TRIGB <= '1';
+---- wait for 1000 ns;
+---- -- VIR_TRIG <= '1';
+---- -- VIR_TRIGB <= '0';
+---- -- wait for 100 ns;
+---- VIR_TRIG <= '0';
+---- VIR_TRIGB <= '1';
+---- wait on dtu_clk until ADO_TTL(7) = '0' and dtu_clk = '1'; --busylvl1
+---- lvl1_trig <= '1';
+---- ADO_TTL(5 downto 2) <= x"d";
+---- wait for 100 ns;
+---- lvl1_trig <= '0';
+---- wait for 100 ns;
+---- ADO_TTL(1) <= '1';
+---- ADO_TTL(5 downto 2) <= dtu_lvl1_tag(3 downto 0);
+---- wait for 100 ns;
+---- ADO_TTL(1) <= '0';
+---- wait for 100 ns;
+---- ADO_TTL(1) <= '1';
+---- ADO_TTL(5 downto 2) <= dtu_lvl1_tag(7 downto 4);
+---- loop
+---- wait for 100 ns;
+---- ADO_TTL(1) <= '0';
+---- wait for 100 ns;
+---- ADO_TTL(1) <= '1';
+---- wait for 100 ns;
+---- ADO_TTL(1) <= '0';
+---- wait on dtu_clk until ADO_TTL(7) = '0' and dtu_clk = '1'; --busylvl1
+---- lvl1_randomize := lvl1_randomize * 3/2 + 10;
+---- -- wait for (lvl1_randomize )*ns;
+---- VIR_TRIG <= '1';
+---- VIR_TRIGB <= '0';
+---- wait for 100 ns;
+---- VIR_TRIG <= '0';
+---- VIR_TRIGB <= '1';
+---- lvl1_trig <= '1';
+---- ADO_TTL(5 downto 2) <= x"1";
+---- wait for 100 ns;
+---- lvl1_trig <= '0';
+---- wait for 100 ns;
+---- ADO_TTL(1) <= '1';
+---- ADO_TTL(5 downto 2) <= dtu_lvl1_tag(3 downto 0);
+---- wait for 100 ns;
+---- ADO_TTL(1) <= '0';
+---- wait for 100 ns;
+---- ADO_TTL(1) <= '1';
+---- ADO_TTL(5 downto 2) <= dtu_lvl1_tag(7 downto 4);
+---- end loop;
+---- end process DTU_EMULATION_LVL1;
+
+---- -- ADO_TTL(10) <= lvl2_trig;
+---- DTU_EMULATION_LVL2:process
+---- begin
+---- -- ADO_TTL(15) <= '0';
+---- lvl2_trig <= '0';
+---- wait for 26000 ns;
+---- loop
+---- ADO_TTL(9) <= '0';
+---- wait on dtu_clk until ADO_TTL(15) = '0'and dtu_clk = '1'; --busylvl2
+---- -- wait on dtu_clk until dtu_lvl1_tag > dtu_lvl2_tag + 1;
+---- wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01";
+---- -- wait for 300 ns;
+---- lvl2_trig <= '1';
+---- ADO_TTL(13 downto 10) <= x"1";
+---- wait for 100 ns;
+---- lvl2_trig <= '0';
+---- wait for 100 ns;
+---- ADO_TTL(9) <= '1';
+---- ADO_TTL(13 downto 10) <= dtu_lvl2_tag(3 downto 0);
+---- wait for 100 ns;
+---- ADO_TTL(9) <= '0';
+---- wait for 100 ns;
+---- ADO_TTL(9) <= '1';
+---- ADO_TTL(13 downto 10) <= dtu_lvl2_tag(7 downto 4);
+---- wait for 100 ns;
+---- ADO_TTL(9) <= '0';
+---- wait for 100 ns;
+---- ADO_TTL(9) <= '1';
+---- wait for 100 ns;
+---- ADO_TTL(9) <= '0';
+
+---- wait on dtu_clk until ADO_TTL(15) = '0'and dtu_clk = '1';
+---- wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01";
+---- -- wait for 100 ns;
+---- lvl2_trig <= '1';
+---- ADO_TTL(13 downto 10) <= x"9";
+---- wait for 100 ns;
+---- lvl2_trig <= '0';
+---- wait for 100 ns;
+---- ADO_TTL(9) <= '1';
+---- ADO_TTL(13 downto 10) <= dtu_lvl2_tag(3 downto 0);
+---- wait for 100 ns;
+---- ADO_TTL(9) <= '0';
+---- wait for 100 ns;
+---- ADO_TTL(9) <= '1';
+---- ADO_TTL(13 downto 10) <= dtu_lvl2_tag(7 downto 4);
+---- wait for 100 ns;
+---- ADO_TTL(9) <= '0';
+---- wait for 100 ns;
+---- ADO_TTL(9) <= '1';
+---- wait for 100 ns;
+---- ADO_TTL(9) <= '0';
+---- end loop;
+---- end process DTU_EMULATION_LVL2;
+---------------------------------------------------------------------------------
+---- if external trigger
+---------------------------------------------------------------------------------
+---- send_external_trigger: process
+---- begin
+---- loop
+---- ADO_TTL(0) <= '0';
+---- wait for 10 ns;
+---- ADO_TTL(0) <= '1';
+---- wait for 10 ns;
+---- end loop;
+---- end process send_external_trigger;
+---- ETRAX_RESPONSE: process
+---- begin
+-- CTS_FS_PC(16) <= '0';
+-- CTS_FS_PC(17) <= '0';
+-- wait for 10 ns;
+-- RESET_VIRT <= '0';
+
+-- wait for 10 ns;
+-- CTS_FS_PC(16) <= '1';
+-- CTS_FS_PC(17) <= '1';
+-- RESET_VIRT <= '1';
+-- wait for 10 ns;
+
+-- wait for 30 ns;
+-- CTS_FS_PC(16) <= '0';
+-- CTS_FS_PC(17) <= '0';
+-- wait for 10 ns;
+-- loop
+-- CTS_FS_PC(17) <= '0';
+-- wait on TLK_CLK until CTS_FS_PB(16) ='1';
+-- wait for 20 ns;
+-- CTS_FS_PC(17) <= '1';
+-- wait for 2000 ns;
+-- end loop;
+-- end process ETRAX_RESPONSE;
+-- EXTERNAL_TRIGG: process
+-- begin
+-- wait for 15 ns;
+-- loop
+-- ADO_TTL(0) <= '1';
+-- ADO_TTL(1) <= '0';
+-- wait for 74 ns;
+-- ADO_TTL(0) <= '0';
+-- ADO_TTL(1) <= '1';
+-- wait for 82 ns;
+-- end loop;
+-- end process EXTERNAL_TRIGG;
+END;
--- /dev/null
+#-- Synplicity, Inc.
+#-- Version 9.0
+#-- Project file ../ctsaddon/cts_fpga1.prj
+
+add_file -vhdl -lib work "ram_register.vhd"
+add_file -vhdl -lib work "cts_fpga1_test.vhd"
+add_file -vhdl -lib work "etrax_reg_mem.vhd"
+add_file -vhdl -lib work "../trbv2/f_divider.vhd"
+add_file -vhdl -lib work "../trbv2/up_down_counter.vhd"
+add_file -vhdl -lib work "cts_delay_large.vhd"
+add_file -vhdl -lib work "delay_fifo.vhd"
+add_file -vhdl -lib work "cts_fpga1_test_set_width.vhd"
+
+#implementation: "workdir"
+impl -add workdir -type fpga
+
+#device options
+set_option -technology LATTICE-SCM
+set_option -part LFSCM3GA40EP1
+set_option -package FF1020C
+set_option -speed_grade -7
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+#set_option -resource_sharing 0
+set_option -top_module "cts_fpga1_test"
+
+#map options
+set_option -frequency 220
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 0
+set_option -force_gsr auto
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+
+
+
+#simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+#set result format/file last
+project -result_format "edif"
+project -result_file "workdir/cts_fpga1_test.edf"
+
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+-- use work.trb_net16_hub_func.all;
+use work.version.all;
+use work.cts_components.all;
+library SC;
+use SC.COMPONENTS.all;
+use ieee.std_logic_arith.all;
+
+entity cts_fpga1_test is
+ generic(
+ RW_REGISTERS_NUMBER : integer range 0 to 49 := 46;
+ R_REGISTERS_NUMBER : integer range 0 to 105 := 2;
+ ENABLE_ETRAX_RW_INTERFACE : integer range 0 to 1 :=1;
+ SCALERS_NUMBER : integer range 0 to 127 :=1;
+ TRIG_BUS_WIDTH : integer range 0 to 64:=32
+ );
+ port(
+ CLK_200_IN : in std_logic;
+ FS_PE : inout std_logic_vector(9 downto 8);
+ TRIG_IN : out std_logic_vector(TRIG_BUS_WIDTH-1 downto 0); --the direction
+ --doesn't
+ --corespond to
+ --the names !
+ --changed in
+ --signal names
+ LVDS_OUT : out std_logic_vector(14 downto 0);
+ LVDS_IN : in std_logic; --//--
+ PROGRAMN_OUT : out std_logic
+ --LED
+-- LED_GREEN : out std_logic;
+-- LED_ORANGE : out std_logic;
+-- LED_RED : out std_logic;
+-- LED_YELLOW : out std_logic;
+-- TRB2_OK_LED : out std_logic;
+-- TRB2_RX_LED : out std_logic;
+-- TRB2_TX_LED : out std_logic;
+-- TRB3_OK_LED : out std_logic;
+-- TRB3_RX_LED : out std_logic;
+-- TRB3_TX_LED : out std_logic;
+ --SFP
+ --Other
+-- TEST_LINE : out std_logic_vector(31 downto 0)
+ );
+
+ attribute syn_useioff : boolean;
+-- attribute syn_useioff of ADO_TTL : signal is true;
+ attribute syn_useioff of TRIG_IN : signal is true;
+ attribute syn_useioff of LVDS_OUT : signal is true;
+ attribute syn_useioff of PROGRAMN_OUT : signal is false;
+-- attribute syn_useioff of LED_GREEN : signal is false;
+-- attribute syn_useioff of LED_ORANGE : signal is false;
+-- attribute syn_useioff of LED_RED : signal is false;
+-- attribute syn_useioff of LED_YELLOW : signal is false;
+-- attribute syn_useioff of TRB2_OK_LED : signal is false;
+-- attribute syn_useioff of TRB2_RX_LED : signal is false;
+-- attribute syn_useioff of TRB2_TX_LED : signal is false;
+-- attribute syn_useioff of TRB3_OK_LED : signal is false;
+-- attribute syn_useioff of TRB3_RX_LED : signal is false;
+-- attribute syn_useioff of TRB3_TX_LED : signal is false;
+
+
+end entity;
+
+architecture cts_fpga1_test of cts_fpga1_test is
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+ component cts_delay_large --20ns -> 15ns
+ generic (
+ VECTOR_WIDTH : integer range 1 to 32);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ DELAY_IN : in std_logic_vector(7 downto 0);
+ DELAY_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ DELAY_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0));
+ end component;
+
+ component cts_fpga1_test_set_width
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ SIGNAL_WIDTH : in std_logic_vector(7 downto 0);
+ SIGNAL_IN : in std_logic;
+ SIGNAL_OUT : out std_logic);
+ end component;
+
+ component etrax_reg_mem
+ generic (
+ RW_REGISTERS_NUMBER : natural;
+ R_REGISTERS_NUMBER : natural;
+ SCALERS_NUMBER : natural;
+ ENABLE_ETRAX_RW_INTERFACE : natural);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ ETRAX_DATA_BUS_E : inout std_logic_vector(9 downto 8);
+ RW_REGISTER_OUT : out std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
+ R_REGISTER_IN : in std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+ R_REGISTER_OUT : out std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+ R_REGISTER_IN_SAVE_1S_IN : in std_logic;
+ SAVED_SCALERS_OUT : out std_logic_vector(SCALERS_NUMBER*32 -1 downto 0);
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
+ REGIO_READ_ENABLE_IN : in std_logic;
+ REGIO_WRITE_ENABLE_IN : in std_logic;
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0);
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
+ REGIO_DATAREADY_OUT : out std_logic;
+ REGIO_NO_MORE_DATA_OUT : out std_logic;
+ REGIO_WRITE_ACK_OUT : out std_logic;
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_REGISTER_OO : out std_logic_vector(31 downto 0));
+ end component;
+
+ constant sim_or_real : integer := 0;
+
+ signal global_reset_cnt : std_logic_vector(15 downto 0):=x"0000";
+ signal reset_i_100 : std_logic;
+
+ signal trig_out_buf : std_logic_vector(63 downto 0);
+ signal hit_cntr : std_logic_vector(31 downto 0);
+
+ --start
+ signal start_pulses, start_out_buf : std_logic_vector(63 downto 0);
+ type start_pulses_type is array (0 to 63) of std_logic_vector(0 downto 0);
+ signal start_pulses_in_array, start_pulses_out_array : start_pulses_type;
+
+ --beam inhbit
+ signal beam_inhibit_out, beam_inhibit_pulse : std_logic;
+
+ -- etrax_reg
+ type r_register_array is array(0 to R_REGISTERS_NUMBER) of std_logic_vector(31 downto 0);
+ signal r_register_i, r_register_buf_i : r_register_array;
+ type rw_register_array is array(0 to RW_REGISTERS_NUMBER) of std_logic_vector(31 downto 0);
+ signal rw_register_i : rw_register_array;
+ signal r_register_vector, r_register_out_buf : std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+ signal rw_register_vector : std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
+
+ --old connections
+ signal save_scalers_out_i : std_logic;
+ signal saved_scalers_in_i : std_logic_vector(SCALERS_NUMBER*32 -1 downto 0);
+ signal down_rw_register_out_buf : std_logic_vector(31 downto 0);
+ signal down_address_out_buf : std_logic_vector(31 downto 0);
+ signal down_data_valid_out_buf : std_logic;
+
+begin
+
+---------------------------------------------------------------------------
+-- Clock & Reset state machine
+---------------------------------------------------------------------------
+
+
+ GLOBAL_RESET: process(CLK_200_IN)
+ begin
+ if rising_edge(CLK_200_IN) then
+ if global_reset_cnt < x"100e" then
+ global_reset_cnt <= global_reset_cnt + 1;
+ reset_i_100 <= '1';
+ elsif global_reset_cnt = x"100e" then
+ reset_i_100 <= '0';
+ global_reset_cnt <= x"100e";
+ else
+ reset_i_100 <= '0';
+ global_reset_cnt <= global_reset_cnt;
+ end if;
+ end if;
+ end process GLOBAL_RESET;
+
+
+-------------------------------------------------------------------------------
+-- registers
+-------------------------------------------------------------------------------
+
+ THE_TRBNET_ETRAX_REG_INTERFACE : etrax_reg_mem
+ generic map (
+ RW_REGISTERS_NUMBER => RW_REGISTERS_NUMBER,
+ R_REGISTERS_NUMBER => R_REGISTERS_NUMBER,
+ SCALERS_NUMBER => SCALERS_NUMBER,
+ ENABLE_ETRAX_RW_INTERFACE => ENABLE_ETRAX_RW_INTERFACE)
+ port map (
+ CLK => CLK_200_IN,
+ RESET => reset_i_100,
+ ETRAX_DATA_BUS_E => FS_PE(9 downto 8),
+ RW_REGISTER_OUT => rw_register_vector,
+ R_REGISTER_IN => r_register_vector,
+ R_REGISTER_OUT => r_register_out_buf,
+ R_REGISTER_IN_SAVE_1S_IN => save_scalers_out_i,
+ SAVED_SCALERS_OUT => saved_scalers_in_i,
+ REGIO_ADDR_IN => down_address_out_buf(15 downto 0), --internal_regio_addr_out_i,
+ REGIO_READ_ENABLE_IN => '0', --internal_regio_read_enable_out_i,
+ REGIO_WRITE_ENABLE_IN => down_data_valid_out_buf, --internal_regio_write_enable_out_i,
+ REGIO_DATA_IN => down_rw_register_out_buf,
+ REGIO_DATA_OUT => open,
+ REGIO_DATAREADY_OUT => open,
+ REGIO_NO_MORE_DATA_OUT => open,
+ REGIO_WRITE_ACK_OUT => open,
+ REGIO_UNKNOWN_ADDR_OUT => open,
+ DEBUG_REGISTER_OO => open);
+
+ REWRITE_R_REGISTER : for i in 1 to R_REGISTERS_NUMBER generate
+ r_register_vector(32*i-1 downto 32*(i-1)) <= r_register_i(i-1);
+ r_register_buf_i(i-1) <= r_register_out_buf(32*i-1 downto 32*(i-1));
+ -- buf -- for registers which are send in the data
+ end generate REWRITE_R_REGISTER;
+
+ REWRITE_RW_REGISTER : for i in 1 to RW_REGISTERS_NUMBER generate
+ rw_register_i(i-1) <= rw_register_vector(32*i-1 downto 32*(i-1));
+ end generate REWRITE_RW_REGISTER;
+
+
+-------------------------------------------------------------------------------
+-- SIGNALS
+-------------------------------------------------------------------------------
+
+-- TEST_LINE(31) <= CLK_200_IN;
+-- TEST_LINE(15) <= reset_i_100;
+
+-- LED_GREEN <= '1';
+-- LED_ORANGE <= '0';
+-- LED_RED <= '1';
+-- LED_YELLOW <= '0';
+ PROGRAMN_OUT <= '1';
+
+ HIT_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 32)
+ port map (
+ CLK => CLK_200_IN,
+ RESET => reset_i_100,
+ COUNT_OUT => hit_cntr,
+ UP_IN => '1',
+ DOWN_IN => '0');
+
+ --selection of the frequency
+
+ GENERATE_SIGNALS: for i in 0 to 32 generate
+
+ MAKE_START_PUSLES: edge_to_pulse
+ port map (
+ clock => CLK_200_IN,
+ en_clk => '1',
+ signal_in => hit_cntr(conv_integer(rw_register_i(i/6)(((i mod 6)+1)*5-1 downto (i mod 6)*5))),
+ pulse => start_pulses(i));
+
+ start_pulses_in_array(i)(0) <= start_pulses(i);
+ DELAY_START_PULSES: cts_delay_large
+ generic map (
+ VECTOR_WIDTH => 1)
+ port map (
+ RESET => reset_i_100,
+ CLK => CLK_200_IN,
+ DELAY_IN => rw_register_i(i/4+11)(((i mod 4)+1)*8-1 downto (i mod 4)*8),
+ DELAY_VECTOR_IN => start_pulses_in_array(i),
+ DELAY_VECTOR_OUT => start_pulses_out_array(i));
+
+ START_SET_WIDTH: cts_fpga1_test_set_width
+ port map (
+ RESET => reset_i_100,
+ CLK => CLK_200_IN,
+ SIGNAL_WIDTH => rw_register_i(i/4+27)(((i mod 4)+1)*8-1 downto (i mod 4)*8),
+ SIGNAL_IN => start_pulses_out_array(i/4)(0),
+ SIGNAL_OUT => start_out_buf(i));
+
+
+ end generate GENERATE_SIGNALS ;
+
+ trig_out_buf <= not start_out_buf;
+ TRIG_IN <= trig_out_buf(TRIG_BUS_WIDTH-1 downto 0);
+-------------------------------------------------------------------------------
+-- beam start signal
+-------------------------------------------------------------------------------
+
+ MAKE_BEAM_INHIBIT_PUSLE: edge_to_pulse
+ port map (
+ clock => CLK_200_IN,
+ en_clk => '1',
+ signal_in => hit_cntr(conv_integer(rw_register_i(44)(5 downto 0))),
+ pulse => beam_inhibit_pulse);
+
+ BEAM_INHIBIT_SET_WIDTH: cts_fpga1_test_set_width
+ port map (
+ RESET => reset_i_100,
+ CLK => CLK_200_IN,
+ SIGNAL_WIDTH => x"64",
+ SIGNAL_IN => beam_inhibit_pulse,
+ SIGNAL_OUT => beam_inhibit_out);
+
+ LVDS_OUT(0) <= beam_inhibit_out;
+ LVDS_OUT(1) <= beam_inhibit_out;
+ LVDS_OUT(2) <= CLK_200_IN;
+ LVDS_OUT(3) <= beam_inhibit_pulse;
+ LVDS_OUT(4) <= beam_inhibit_out;
+ LVDS_OUT(5) <= beam_inhibit_out;
+ LVDS_OUT(6) <= beam_inhibit_out;
+ LVDS_OUT(7) <= beam_inhibit_out;
+ LVDS_OUT(8) <= beam_inhibit_out;
+ LVDS_OUT(9) <= beam_inhibit_out;
+ LVDS_OUT(10) <= beam_inhibit_out;
+ LVDS_OUT(11) <= beam_inhibit_out;
+ LVDS_OUT(12) <= beam_inhibit_out;
+ LVDS_OUT(13) <= beam_inhibit_out;
+ LVDS_OUT(14) <= beam_inhibit_out;
+
+end architecture;
--- /dev/null
+#!/usr/bin/perl
+###########################################
+# Script file to run the flow
+#
+###########################################
+#
+# Command line for synplify_pro
+#
+
+
+use Data::Dumper;
+
+use warnings;
+use strict;
+my $lattice_path = '/opt/lattice/diamond/1.3/';
+#my $lattice_path = '/opt/lattice/ispLEVER8.0/isptools/';
+#my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/';
+#my $synplify_path = '/opt/synplicity/D-2009.12/bin/';
+#my $synplify_path = '/opt/synplicity/D-2010.03/bin/';
+#my $synplify_path = '/opt/synplicity/D-2010.03-SP1-1/bin/';
+my $synplify_path = '/opt/synplicity/fpga_e201103/bin/';
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}="27000\@lxcad01.gsi.de";
+
+
+my $TOPNAME="cts_fpga1_test";
+
+my $FAMILYNAME="LatticeSCM";
+my $DEVICENAME="LFSCM3GA40EP1";
+my $PACKAGE="FFBGA1020";
+my $SPEEDGRADE="7";
+
+
+#create full lpf file
+#system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+#system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+#my $c=$synplify_path."synplify_pro_oem -batch $TOPNAME".".prj";
+#my $c="$synplify_path/bin/synplify_pro -Pro -prj $TOPNAME".".prj";
+my $c="$synplify_path/synplify_premier_dp -batch $TOPNAME".".prj";
+#my $c="$synplify_path/bin/synpwrap -Pro -prj $TOPNAME".".prj";
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+#if ($r) {
+#$c="cat $TOPNAME.srr";
+#system($c);
+#exit 129;
+#}
+
+foreach (@a)
+{
+ if(/\@E:/)
+ {
+ $c="cat $TOPNAME.srr";
+ system($c);
+ print "bdabdhsadbhjasdhasldhbas";
+ exit 129;
+ }
+}
+#if (0){
+
+$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de";
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+
+system("rm $TOPNAME.ncd");
+
+#$c=qq|$lattice_path/ispfpga/bin/lin/par -w -y -l 4 -i 15 "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |;
+#$c=qq|$lattice_path/ispfpga/bin/lin/par -f $TOPNAME.p2t "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |;
+$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# TWR Timing Report
+#$c=qq|$lattice_path/ispfpga/bin/lin/tg "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|;
+execute($c);
+
+#$c=q| perl -ne '$in=1 if(/Report Summary/); print if($in==1); $in=0 if(/All preferences were met./)' | . "$TOPNAME.twr.setup";
+#execute($c);
+
+
+chdir "..";
+
+exit;
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+ $op = "" if(!$op);
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+
+ return $r;
+
+}
--- /dev/null
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
+<ispXCF version="17.0 Linux Beta">
+ <Comment></Comment>
+ <Chain>
+ <Comm>JTAG</Comm>
+ <Device>
+ <Pos>1</Pos>
+ <Vendor>NA</Vendor>
+ <Family>Generic JTAG Device</Family>
+ <Name>JTAG-NOP</Name>
+ <Package>All</Package>
+ <PON>JTAG-NOP</PON>
+ <Bypass>
+ <InstrLen>10</InstrLen>
+ <InstrVal>1111111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>2</Pos>
+ <Ref>cts_fpga1</Ref>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeSCM</Family>
+ <Name>LFSCM3GA40E</Name>
+ <IDCode>0x0a81a157</IDCode>
+ <Package>All</Package>
+ <PON>LFSCM3GA40EP1</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/home/marek/ctsaddon/workdir/cts_fpga1_test.bit</File>
+ <FileTime>11/3/2010 14:36:35</FileTime>
+ <Operation>Fast Program</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1447</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>3</Pos>
+ <Ref>cts_fpga2</Ref>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP2M</Family>
+ <Name>LFE2M100E</Name>
+ <IDCode>0x0127d043</IDCode>
+ <Package>900-ball fpBGA</Package>
+ <PON>LFE2M100E-XXF900</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <MaskFile>/home/marek/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk</MaskFile>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1311</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>4</Pos>
+ <Ref>power</Ref>
+ <Vendor>NA</Vendor>
+ <Family>Generic JTAG Device</Family>
+ <Name>JTAG-NOP</Name>
+ <Package>All</Package>
+ <PON>JTAG-NOP</PON>
+ <Bypass>
+ <InstrLen>4</InstrLen>
+ <InstrVal>1111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ </Option>
+ </Device>
+ </Chain>
+ <ProjectOptions>
+ <Program>SEQUENTIAL</Program>
+ <Process>ENTIRED CHAIN</Process>
+ <OperationOverride>No Override</OperationOverride>
+ <StartTAP>TLR</StartTAP>
+ <EndTAP>TLR</EndTAP>
+ <DeGlitch value="TRUE"/>
+ <VerifyUsercode value="TRUE"/>
+ <PinSetting>
+ TMS LOW;
+ TCK LOW;
+ TDI LOW;
+ TDO LOW;
+ CableEN HIGH;
+ </PinSetting>
+ </ProjectOptions>
+</ispXCF>
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+
+entity cts_fpga1_to_fpga2 is
+
+ generic (
+ LVL1_SIZE_OF_DATA_BUS_OUT : natural;
+ LVL2_SIZE_OF_DATA_BUS_OUT : natural
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ SLOW_CLK_OUT : out std_logic;
+ DATA_IN : in std_logic_vector(31 downto 0);
+ LVL1_CTS_DATA_ACK_OUT : out std_logic;
+ LVL1_DATA_VALID_IN : in std_logic;
+ LVL1_FINISHED_IN : in std_logic;
+ LVL1_TRIGGER_TAG_IN : in std_logic_vector(15 downto 0);
+ LVL1_RND_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_CODE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRIGGER_IN : in std_logic;
+ LVL1_TRIGGER_OUT : out std_logic;
+ LVL1_DATA_OUT : out std_logic_vector(LVL1_SIZE_OF_DATA_BUS_OUT - 1 downto 0);
+ LVL1_DATA_VALID_OUT : out std_logic;
+ LVL2_TRIGGER_TAG_IN : in std_logic_vector(15 downto 0);
+ LVL2_RND_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL2_CODE_IN : in std_logic_vector(3 downto 0);
+ LVL2_TRIGGER_IN : in std_logic;
+ LVL2_TRIGGER_OUT : out std_logic;
+ LVL2_DATA_OUT : out std_logic_vector(LVL2_SIZE_OF_DATA_BUS_OUT - 1 downto 0);
+ LVL2_DATA_VALID_OUT : out std_logic;
+ IP_TABLE_IN : in std_logic_vector(15 downto 0);
+ EVENTS_NUMBER_IN : in std_logic_vector(23 downto 0);
+ LVL1_INFO_IN : in std_logic_vector(15 downto 0);
+ CTS_FPGA1_TO_FPGA2_DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
+end cts_fpga1_to_fpga2;
+
+architecture cts_fpga1_to_fpga2 of cts_fpga1_to_fpga2 is
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ component cts_eb_ip_switch
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ LVL2_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL2_TRIGGER_IN : in std_logic;
+ IP_TABLE_IN : in std_logic_vector(15 downto 0);
+ NUMBER_OF_EVENTS_IN : in std_logic_vector(23 downto 0);
+ EB_IP_SWITCH_OUT : out std_logic_vector(3 downto 0);
+ EB_IP_SWITCH_STATUS_OUT : out std_logic_vector(3 downto 0));
+ end component;
+
+ --lvl1
+ type LVL1_DATA_SEND_FSM is (IDLE, LVL1_INFO_PREPARE_A, LVL1_INFO_PREPARE_B, LVL1_INFO_SEND, LVL1_DATA_SEND_WAIT_FOR_BEGINNING,LVL1_DATA_PREPARE_A, LVL1_DATA_PREPARE_B, LVL1_DATA_PREPARE_C, LVL1_DATA_PREPARE_D, LVL1_DATA_PREPARE_E, LVL1_DATA_SEND, LVL1_DATA_SEND_CHECK, LVL1_TRIGGER_SEND_A, LVL1_TRIGGER_SEND_B);
+ signal LVL1_DATA_SEND_CURRENT, LVL1_DATA_SEND_NEXT : LVL1_DATA_SEND_FSM;
+ signal lvl1_info_data : std_logic_vector(95 downto 0);
+ signal lvl1_data_send_debug,lvl1_data_send_debug_fsm : std_logic_vector(3 downto 0);
+ signal lvl1_info_cntr : std_logic_vector(7 downto 0);
+ signal lvl1_info_cntr_up, lvl1_info_cntr_up_fsm,lvl1_info_cntr_rst,lvl1_info_cntr_rst_fsm : std_logic;
+ signal lvl1_info_integer_cntr, lvl1_data_integer_cntr : integer range 0 to 33 :=0;
+
+ signal lvl1_data_out_i, lvl1_data_out_fsm : std_logic_vector(LVL1_SIZE_OF_DATA_BUS_OUT - 1 downto 0);
+ signal lvl1_cts_data_ack_out_i, lvl1_cts_data_ack_out_fsm ,lvl1_trigger_out_i, lvl1_trigger_out_fsm, lvl1_data_valid_out_i, lvl1_data_valid_out_fsm,lvl1_data_valid_out_sync,lvl1_data_valid_out_tmp : std_logic;
+
+ signal lvl1_data_cntr_rst, lvl1_data_cntr_rst_fsm, lvl1_data_cntr_up, lvl1_data_cntr_up_fsm : std_logic;
+ signal lvl1_data_cntr : std_logic_vector(3 downto 0);
+ signal lvl1_data_valid_in_i : std_logic;
+ signal lvl1_finished_marker : std_logic;
+
+ --lvl2
+ type LVL2_DATA_SEND_FSM is (IDLE, LVL2_INFO_PREPARE_A, LVL2_INFO_PREPARE_B, LVL2_INFO_SEND, LVL2_TRIGGER_SEND_A, LVL2_TRIGGER_SEND_B);
+ signal LVL2_DATA_SEND_CURRENT, LVL2_DATA_SEND_NEXT : LVL2_DATA_SEND_FSM;
+ signal lvl2_info_data : std_logic_vector(95 downto 0);
+ signal lvl2_data_send_debug,lvl2_data_send_debug_fsm : std_logic_vector(3 downto 0);
+ signal lvl2_info_cntr : std_logic_vector(7 downto 0);
+ signal lvl2_info_cntr_up, lvl2_info_cntr_up_fsm,lvl2_info_cntr_rst,lvl2_info_cntr_rst_fsm : std_logic;
+ signal lvl2_info_integer_cntr, lvl2_data_integer_cntr : integer range 0 to 33 :=0;
+
+ signal lvl2_data_out_i, lvl2_data_out_fsm : std_logic_vector(LVL2_SIZE_OF_DATA_BUS_OUT - 1 downto 0);
+ signal lvl2_trigger_out_i, lvl2_trigger_out_fsm, lvl2_data_valid_out_i, lvl2_data_valid_out_fsm,lvl2_data_valid_out_sync,lvl2_data_valid_out_tmp : std_logic;
+ signal eb_ip_switch_out_i : std_logic_vector(3 downto 0);
+ signal eb_ip_update, eb_ip_update_fsm : std_logic;
+
+ --global
+ signal slow_data_cntr,slow_data_cntr_sync : std_logic_vector(0 downto 0);
+
+
+begin
+
+-------------------------------------------------------------------------------
+-- lvl1
+-------------------------------------------------------------------------------
+
+ LVL1_SLOW_DATA_SEND_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 1)
+ port map (
+ CLK => CLK,
+ RESET => RESET,--lvl1_slow_data_rst,
+ COUNT_OUT => slow_data_cntr,
+ UP_IN => '1',
+ DOWN_IN => '0');
+
+ SLOW_CLK_OUT <= slow_data_cntr(0);
+
+ LVL1_FINISHED_PROC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or LVL1_DATA_SEND_CURRENT = LVL1_TRIGGER_SEND_A then
+ lvl1_finished_marker <= '0';
+ elsif LVL1_FINISHED_IN = '1' then
+ lvl1_finished_marker <= '1';
+ end if;
+ end if;
+ end process LVL1_FINISHED_PROC;
+
+ THE_LVL1_INFO_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => lvl1_info_cntr_rst,
+ COUNT_OUT => lvl1_info_cntr,
+ UP_IN => lvl1_info_cntr_up,
+ DOWN_IN => '0');
+
+ THE_LVL1_DATA_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 4)
+ port map (
+ CLK => CLK,
+ RESET => lvl1_data_cntr_rst,
+ COUNT_OUT => lvl1_data_cntr,
+ UP_IN => lvl1_data_cntr_up,
+ DOWN_IN => '0');
+
+
+ SAVE_LVL1_INFO : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_info_data <= (others => '0');
+ elsif LVL1_TRIGGER_IN = '1' then
+ lvl1_info_data <= x"00" & LVL1_INFO_IN & LVL1_RND_CODE_IN &
+ x"0000000" & LVL1_CODE_IN &
+ x"0000" & LVL1_TRIGGER_TAG_IN;
+ end if;
+ end if;
+ end process SAVE_LVL1_INFO;
+
+ LVL1_DATA_SEND_CLK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL1_DATA_SEND_CURRENT <= IDLE;
+ lvl1_cts_data_ack_out_i <= '0';
+ lvl1_data_send_debug <= x"0";
+ lvl1_info_integer_cntr <= 0;
+ lvl1_data_integer_cntr <= 0;
+ lvl1_info_cntr_rst <= '1';
+ lvl1_info_cntr_up <= '0';
+ lvl1_data_out_i <= (others => '0');
+ lvl1_data_valid_out_i <= '0';
+ lvl1_data_cntr_rst <= '1';
+ lvl1_data_cntr_up <= '0';
+ lvl1_cts_data_ack_out_i <= '0';
+ slow_data_cntr_sync(0) <= '0';
+ else
+ LVL1_DATA_SEND_CURRENT <= LVL1_DATA_SEND_NEXT;
+ lvl1_cts_data_ack_out_i <= lvl1_cts_data_ack_out_fsm;
+ lvl1_data_send_debug <= lvl1_data_send_debug_fsm;
+ lvl1_info_integer_cntr <= conv_integer(lvl1_info_cntr(3 downto 0));
+ lvl1_data_integer_cntr <= conv_integer(lvl1_data_cntr(3 downto 0));
+ lvl1_info_cntr_rst <= lvl1_info_cntr_rst_fsm;
+ lvl1_info_cntr_up <= lvl1_info_cntr_up_fsm;
+ lvl1_data_out_i <= lvl1_data_out_fsm;
+ lvl1_trigger_out_i <= lvl1_trigger_out_fsm;
+ lvl1_data_valid_out_i <= lvl1_data_valid_out_fsm;
+ lvl1_data_cntr_rst <= lvl1_data_cntr_rst_fsm;
+ lvl1_data_cntr_up <= lvl1_data_cntr_up_fsm;
+ lvl1_cts_data_ack_out_i <= lvl1_cts_data_ack_out_fsm;
+ slow_data_cntr_sync <= slow_data_cntr;
+ end if;
+ end if;
+ end process LVL1_DATA_SEND_CLK;
+
+ LVL1_DATA_OUT <= lvl1_data_out_i;
+ LVL1_TRIGGER_OUT <= lvl1_trigger_out_i;
+
+ LVL1_VALID_OUT_SYNC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_data_valid_out_sync <= '0';
+ lvl1_data_valid_out_tmp <= '0';
+ else
+ lvl1_data_valid_out_sync <= lvl1_data_valid_out_i;
+ lvl1_data_valid_out_tmp <= lvl1_data_valid_out_i and lvl1_data_valid_out_sync;
+ end if;
+ end if;
+ end process LVL1_VALID_OUT_SYNC;
+
+ LVL1_DATA_VALID_OUT <= lvl1_data_valid_out_tmp;
+ LVL1_CTS_DATA_ACK_OUT <= lvl1_cts_data_ack_out_i;
+ lvl1_data_valid_in_i <= LVL1_DATA_VALID_IN;
+
+ LVL1_DATA_SEND_PROC : process (CLK)
+ begin
+ lvl1_cts_data_ack_out_fsm <= '0';
+ lvl1_data_send_debug_fsm <= x"0";
+ lvl1_info_cntr_rst_fsm <= '1';
+ lvl1_info_cntr_up_fsm <= '0';
+ lvl1_data_out_fsm <= (others => '0');
+ lvl1_data_valid_out_fsm <= '0';
+ lvl1_trigger_out_fsm <= '0';
+ lvl1_data_cntr_rst_fsm <= '1';
+ lvl1_data_cntr_up_fsm <= '0';
+ lvl1_cts_data_ack_out_fsm <= '0';
+
+ case (LVL1_DATA_SEND_CURRENT) is
+ when IDLE =>
+ lvl1_data_send_debug_fsm <= x"1";
+ if LVL1_TRIGGER_IN = '1' then
+ LVL1_DATA_SEND_NEXT <= LVL1_INFO_PREPARE_A;
+ else
+ LVL1_DATA_SEND_NEXT <= IDLE;
+ end if;
+
+ when LVL1_INFO_PREPARE_A =>
+ lvl1_data_send_debug_fsm <= x"3";
+ if slow_data_cntr(0) = '0' then
+ LVL1_DATA_SEND_NEXT <= LVL1_INFO_SEND;
+ else
+ LVL1_DATA_SEND_NEXT <= LVL1_INFO_PREPARE_A;
+ end if;
+
+ when LVL1_INFO_SEND =>
+ lvl1_data_send_debug_fsm <= x"4";
+ lvl1_info_cntr_up_fsm <= slow_data_cntr_sync(0);
+ lvl1_info_cntr_rst_fsm <= '0';
+ lvl1_data_out_fsm <= lvl1_info_data((LVL1_SIZE_OF_DATA_BUS_OUT*(lvl1_info_integer_cntr+1))-1 downto LVL1_SIZE_OF_DATA_BUS_OUT*(lvl1_info_integer_cntr));
+
+ if lvl1_info_cntr = (3*(32/LVL1_SIZE_OF_DATA_BUS_OUT)) then
+ lvl1_data_valid_out_fsm <= '0';
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_SEND_WAIT_FOR_BEGINNING;
+ else
+ lvl1_data_valid_out_fsm <= '1';
+ LVL1_DATA_SEND_NEXT <= LVL1_INFO_SEND;
+ end if;
+
+-- lvl1 data transport
+
+ when LVL1_DATA_SEND_WAIT_FOR_BEGINNING =>
+ if lvl1_data_valid_in_i = '1' then
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_PREPARE_A;
+ elsif lvl1_finished_marker = '1' then
+ LVL1_DATA_SEND_NEXT <= LVL1_TRIGGER_SEND_A;
+ else
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_SEND_WAIT_FOR_BEGINNING;
+ end if;
+
+ when LVL1_DATA_PREPARE_A =>
+ lvl1_data_send_debug_fsm <= x"2";
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_PREPARE_B;
+
+ when LVL1_DATA_PREPARE_B =>
+ lvl1_data_send_debug_fsm <= x"2";
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_PREPARE_C;
+
+ when LVL1_DATA_PREPARE_C =>
+ lvl1_data_send_debug_fsm <= x"2";
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_PREPARE_D;
+
+ when LVL1_DATA_PREPARE_D =>
+ lvl1_data_send_debug_fsm <= x"2";
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_PREPARE_E;
+
+ when LVL1_DATA_PREPARE_E =>
+ lvl1_data_send_debug_fsm <= x"3";
+ if lvl1_data_valid_in_i = '1' and slow_data_cntr(0) = '0' then
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_SEND;
+ elsif lvl1_data_valid_in_i = '1' and slow_data_cntr(0) = '1' then
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_PREPARE_E;
+ else
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_SEND_CHECK;
+ end if;
+
+ when LVL1_DATA_SEND =>
+ lvl1_data_send_debug_fsm <= x"4";
+ lvl1_data_cntr_up_fsm <= slow_data_cntr_sync(0);--'1';
+ lvl1_data_cntr_rst_fsm <= '0';
+ lvl1_data_out_fsm <= DATA_IN((LVL1_SIZE_OF_DATA_BUS_OUT*(lvl1_data_integer_cntr+1))-1 downto LVL1_SIZE_OF_DATA_BUS_OUT*(lvl1_data_integer_cntr));
+ if lvl1_data_cntr = ((32/LVL1_SIZE_OF_DATA_BUS_OUT)) then
+-- LVL1_DATA_SEND_NEXT <= LVL1_DATA_SEND_WAIT_FOR_BEGINNING;
+ lvl1_data_valid_out_fsm <= '0';
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_SEND_CHECK;
+ else
+ lvl1_data_valid_out_fsm <= '1';
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_SEND;
+ end if;
+
+ when LVL1_DATA_SEND_CHECK =>
+ if lvl1_finished_marker = '0' and lvl1_data_valid_in_i = '1' then
+ lvl1_cts_data_ack_out_fsm <= '1';
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_PREPARE_A;
+ elsif lvl1_finished_marker = '1' then
+ LVL1_DATA_SEND_NEXT <= LVL1_TRIGGER_SEND_A;
+ elsif lvl1_finished_marker = '0' and lvl1_data_valid_in_i = '0' then
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_SEND_WAIT_FOR_BEGINNING;
+ else
+ LVL1_DATA_SEND_NEXT <= LVL1_DATA_SEND_CHECK;
+ end if;
+
+ when LVL1_TRIGGER_SEND_A =>
+ lvl1_trigger_out_fsm <= '1';
+ LVL1_DATA_SEND_NEXT <= LVL1_TRIGGER_SEND_B;
+
+ when LVL1_TRIGGER_SEND_B =>
+ lvl1_trigger_out_fsm <= '1';
+ LVL1_DATA_SEND_NEXT <= IDLE;
+
+ when others =>
+ LVL1_DATA_SEND_NEXT <= IDLE;
+ end case;
+ end process LVL1_DATA_SEND_PROC;
+
+ -----------------------------------------------------------------------------
+ -- lvl2
+ -----------------------------------------------------------------------------
+
+
+
+ cts_eb_ip_switch_1: cts_eb_ip_switch
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ LVL2_TRIGGER_TYPE_IN => LVL2_CODE_IN,
+ LVL2_TRIGGER_IN => eb_ip_update,
+ IP_TABLE_IN => IP_TABLE_IN,
+ NUMBER_OF_EVENTS_IN => EVENTS_NUMBER_IN,
+ EB_IP_SWITCH_OUT => eb_ip_switch_out_i,
+ EB_IP_SWITCH_STATUS_OUT => CTS_FPGA1_TO_FPGA2_DEBUG_OUT(3 downto 0));
+
+
+
+ THE_LVL2_INFO_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => lvl2_info_cntr_rst,
+ COUNT_OUT => lvl2_info_cntr,
+ UP_IN => lvl2_info_cntr_up,
+ DOWN_IN => '0');
+
+ SAVE_LVL2_INFO : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_info_data <= (others => '0');
+ elsif LVL2_TRIGGER_IN = '1' then
+ lvl2_info_data <= x"000000" & LVL2_RND_CODE_IN &
+ x"0000000" & LVL2_CODE_IN &
+ x"000" & eb_ip_switch_out_i & LVL2_TRIGGER_TAG_IN;
+ end if;
+ end if;
+ end process SAVE_LVL2_INFO;
+
+ LVL2_DATA_SEND_CLK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL2_DATA_SEND_CURRENT <= IDLE;
+ lvl2_data_send_debug <= x"0";
+ lvl2_info_integer_cntr <= 0;
+ lvl2_info_cntr_rst <= '1';
+ lvl2_info_cntr_up <= '0';
+ lvl2_data_out_i <= (others => '0');
+ lvl2_trigger_out_i <= '0';
+ lvl2_data_valid_out_i <= '0';
+ eb_ip_update <= '0';
+ else
+ LVL2_DATA_SEND_CURRENT <= LVL2_DATA_SEND_NEXT;
+ lvl2_data_send_debug <= lvl2_data_send_debug_fsm;
+ lvl2_info_integer_cntr <= conv_integer(lvl2_info_cntr(3 downto 0));
+ lvl2_info_cntr_rst <= lvl2_info_cntr_rst_fsm;
+ lvl2_info_cntr_up <= lvl2_info_cntr_up_fsm;
+ lvl2_data_out_i <= lvl2_data_out_fsm;
+ lvl2_trigger_out_i <= lvl2_trigger_out_fsm;
+ lvl2_data_valid_out_i <= lvl2_data_valid_out_fsm;
+ eb_ip_update <= eb_ip_update_fsm;
+ end if;
+ end if;
+ end process LVL2_DATA_SEND_CLK;
+
+ LVL2_DATA_OUT <= lvl2_data_out_i;
+ LVL2_TRIGGER_OUT <= lvl2_trigger_out_i;
+
+ LVL2_DATA_SEND_PROC : process (CLK)
+ begin
+ lvl2_data_send_debug_fsm <= x"0";
+ lvl2_info_cntr_rst_fsm <= '1';
+ lvl2_info_cntr_up_fsm <= '0';
+ lvl2_data_out_fsm <= (others => '0');
+ lvl2_data_valid_out_fsm <= '0';
+ lvl2_trigger_out_fsm <= '0';
+ eb_ip_update_fsm <= '0';
+
+ case (LVL2_DATA_SEND_CURRENT) is
+ when IDLE =>
+ lvl2_data_send_debug_fsm <= x"1";
+ if LVL2_TRIGGER_IN = '1' then
+ LVL2_DATA_SEND_NEXT <= LVL2_INFO_PREPARE_A;
+ else
+ LVL2_DATA_SEND_NEXT <= IDLE;
+ end if;
+
+ when LVL2_INFO_PREPARE_A =>
+ lvl2_data_send_debug_fsm <= x"3";
+ if slow_data_cntr(0) = '0' then
+ LVL2_DATA_SEND_NEXT <= LVL2_INFO_SEND;
+ else
+ LVL2_DATA_SEND_NEXT <= LVL2_INFO_PREPARE_A;
+ end if;
+
+ when LVL2_INFO_SEND =>
+ lvl2_data_send_debug_fsm <= x"4";
+ lvl2_info_cntr_up_fsm <= slow_data_cntr_sync(0);
+ lvl2_info_cntr_rst_fsm <= '0';
+ lvl2_data_out_fsm <= lvl2_info_data((LVL2_SIZE_OF_DATA_BUS_OUT*(lvl2_info_integer_cntr+1))-1 downto LVL2_SIZE_OF_DATA_BUS_OUT*(lvl2_info_integer_cntr));
+ if lvl2_info_cntr = (3*(32/LVL2_SIZE_OF_DATA_BUS_OUT)) then
+ lvl2_data_valid_out_fsm <= '0';
+ LVL2_DATA_SEND_NEXT <= LVL2_TRIGGER_SEND_A;
+ else
+ lvl2_data_valid_out_fsm <= '1';
+ LVL2_DATA_SEND_NEXT <= LVL2_INFO_SEND;
+ end if;
+
+ when LVL2_TRIGGER_SEND_A =>
+ lvl2_trigger_out_fsm <= '1';
+ eb_ip_update_fsm <= '1';
+ LVL2_DATA_SEND_NEXT <= LVL2_TRIGGER_SEND_B;
+
+ when LVL2_TRIGGER_SEND_B =>
+ lvl2_trigger_out_fsm <= '1';
+ LVL2_DATA_SEND_NEXT <= IDLE;
+
+ when others =>
+ LVL2_DATA_SEND_NEXT <= IDLE;
+ end case;
+ end process LVL2_DATA_SEND_PROC;
+
+ LVL2_VALID_OUT_SYNC : process (CLK, RESET,lvl2_data_valid_out_i,lvl2_data_valid_out_sync)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_data_valid_out_sync <= '0';
+ lvl2_data_valid_out_tmp <= '0';
+ else
+ lvl2_data_valid_out_sync <= lvl2_data_valid_out_i;
+ lvl2_data_valid_out_tmp <= lvl2_data_valid_out_i and lvl2_data_valid_out_sync;
+ end if;
+ end if;
+ end process LVL2_VALID_OUT_SYNC;
+
+ LVL2_DATA_VALID_OUT <= lvl2_data_valid_out_tmp;
+
+end cts_fpga1_to_fpga2;
--- /dev/null
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
+<ispXCF version="17.0 Linux Beta">
+ <Comment></Comment>
+ <Chain>
+ <Comm>JTAG</Comm>
+ <Device>
+ <Pos>1</Pos>
+ <Vendor>NA</Vendor>
+ <Family>Generic JTAG Device</Family>
+ <Name>JTAG-NOP</Name>
+ <Package>All</Package>
+ <PON>JTAG-NOP</PON>
+ <Bypass>
+ <InstrLen>10</InstrLen>
+ <InstrVal>1111111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>2</Pos>
+ <Ref>cts_fpga1</Ref>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeSCM</Family>
+ <Name>LFSCM3GA40E</Name>
+ <IDCode>0x0a81a157</IDCode>
+ <Package>All</Package>
+ <PON>LFSCM3GA40EP1</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/home/marek/ctsaddon/workdir/cts_fpga1.bit</File>
+ <FileTime>10/5/2010 11:15:23</FileTime>
+ <Operation>Fast Program</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1447</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>3</Pos>
+ <Ref>cts_fpga2</Ref>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP2M</Family>
+ <Name>LFE2M100E</Name>
+ <IDCode>0x0127d043</IDCode>
+ <Package>900-ball fpBGA</Package>
+ <PON>LFE2M100E-XXF900</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <MaskFile>/home/marek/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk</MaskFile>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1311</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>4</Pos>
+ <Ref>power</Ref>
+ <Vendor>NA</Vendor>
+ <Family>Generic JTAG Device</Family>
+ <Name>JTAG-NOP</Name>
+ <Package>All</Package>
+ <PON>JTAG-NOP</PON>
+ <Bypass>
+ <InstrLen>4</InstrLen>
+ <InstrVal>1111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ </Option>
+ </Device>
+ </Chain>
+ <ProjectOptions>
+ <Program>SEQUENTIAL</Program>
+ <Process>ENTIRED CHAIN</Process>
+ <OperationOverride>No Override</OperationOverride>
+ <StartTAP>TLR</StartTAP>
+ <EndTAP>TLR</EndTAP>
+ <DeGlitch value="TRUE"/>
+ <VerifyUsercode value="TRUE"/>
+ <PinSetting>
+ TMS LOW;
+ TCK LOW;
+ TDI LOW;
+ TDO LOW;
+ CableEN HIGH;
+ </PinSetting>
+ </ProjectOptions>
+</ispXCF>
--- /dev/null
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
+<ispXCF version="17.0 Linux Beta">
+ <Comment></Comment>
+ <Chain>
+ <Comm>JTAG</Comm>
+ <Device>
+ <Pos>1</Pos>
+ <Ref>cts_fpga1</Ref>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeSCM</Family>
+ <Name>LFSCM3GA40E</Name>
+ <IDCode>0x0a81a157</IDCode>
+ <Package>All</Package>
+ <PON>LFSCM3GA40EP1</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/home/marek/ctsaddon/workdir/cts_fpga1.bit</File>
+ <FileTime>10/5/2010 11:15:23</FileTime>
+ <Operation>Fast Program</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1447</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>2</Pos>
+ <Ref>cts_fpga2</Ref>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP2M</Family>
+ <Name>LFE2M100E</Name>
+ <IDCode>0x0127d043</IDCode>
+ <Package>900-ball fpBGA</Package>
+ <PON>LFE2M100E-XXF900</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <MaskFile>/home/marek/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk</MaskFile>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1311</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>3</Pos>
+ <Ref>power</Ref>
+ <Vendor>NA</Vendor>
+ <Family>Generic JTAG Device</Family>
+ <Name>JTAG-NOP</Name>
+ <Package>All</Package>
+ <PON>JTAG-NOP</PON>
+ <Bypass>
+ <InstrLen>4</InstrLen>
+ <InstrVal>1111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ </Option>
+ </Device>
+ </Chain>
+ <ProjectOptions>
+ <Program>SEQUENTIAL</Program>
+ <Process>ENTIRED CHAIN</Process>
+ <OperationOverride>No Override</OperationOverride>
+ <StartTAP>TLR</StartTAP>
+ <EndTAP>TLR</EndTAP>
+ <DeGlitch value="TRUE"/>
+ <VerifyUsercode value="TRUE"/>
+ <PinSetting>
+ TMS LOW;
+ TCK LOW;
+ TDI LOW;
+ TDO LOW;
+ CableEN HIGH;
+ </PinSetting>
+ </ProjectOptions>
+</ispXCF>
--- /dev/null
+#################################################################
+# Basic Constraints
+#################################################################
+COMMERCIAL ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ;
+
+
+#################################################################
+# Clock
+#################################################################
+LOCATE COMP "CLK_100_IN" SITE "T5";
+LOCATE COMP "CLK_125_IN" SITE "N1";
+
+IOBUF PORT "CLK_100_IN" IO_TYPE=LVDS25 ;
+IOBUF PORT "CLK_125_IN" IO_TYPE=LVDS25 ;
+
+#################################################################
+# Reset
+#################################################################
+LOCATE COMP "ADDON_RESET" SITE "AC16";
+LOCATE COMP "RESET_FPGA_2" SITE "AG11";
+
+IOBUF PORT "ADDON_RESET" IO_TYPE=LVTTL33 PULLMODE=UP ;
+IOBUF PORT "RESET_FPGA_2" IO_TYPE=LVTTL33 PULLMODE=UP ;
+
+#################################################################
+# To TRB
+#################################################################
+LOCATE COMP "ADO_LV_0" SITE "F25";
+LOCATE COMP "ADO_LV_1" SITE "F24";
+LOCATE COMP "ADO_LV_2" SITE "G25";
+LOCATE COMP "ADO_LV_3" SITE "F26";
+LOCATE COMP "ADO_LV_4" SITE "E27";
+LOCATE COMP "ADO_LV_5" SITE "D27";
+LOCATE COMP "ADO_LV_6" SITE "H25";
+LOCATE COMP "ADO_LV_7" SITE "G24";
+LOCATE COMP "ADO_LV_8" SITE "E28";
+LOCATE COMP "ADO_LV_9" SITE "D28";
+LOCATE COMP "ADO_LV_10" SITE "H24";
+LOCATE COMP "ADO_LV_11" SITE "H23";
+LOCATE COMP "ADO_LV_12" SITE "G26";
+LOCATE COMP "ADO_LV_13" SITE "H27";
+LOCATE COMP "ADO_LV_14" SITE "H26";
+LOCATE COMP "ADO_LV_15" SITE "J26";
+LOCATE COMP "ADO_LV_16" SITE "J23";
+LOCATE COMP "ADO_LV_17" SITE "J22";
+LOCATE COMP "ADO_LV_18" SITE "K22";
+LOCATE COMP "ADO_LV_19" SITE "K23";
+LOCATE COMP "ADO_LV_20" SITE "K26";
+LOCATE COMP "ADO_LV_21" SITE "J27";
+LOCATE COMP "ADO_LV_22" SITE "K25";
+LOCATE COMP "ADO_LV_23" SITE "K24";
+LOCATE COMP "ADO_LV_24" SITE "D29";
+LOCATE COMP "ADO_LV_25" SITE "D30";
+LOCATE COMP "ADO_LV_26" SITE "L23";
+LOCATE COMP "ADO_LV_27" SITE "L24";
+LOCATE COMP "ADO_LV_28" SITE "G27";
+LOCATE COMP "ADO_LV_29" SITE "G28";
+LOCATE COMP "ADO_LV_30" SITE "J28";
+LOCATE COMP "ADO_LV_31" SITE "H28";
+LOCATE COMP "ADO_LV_32" SITE "L26";
+LOCATE COMP "ADO_LV_33" SITE "L25";
+LOCATE COMP "ADO_LV_34" SITE "E29";
+LOCATE COMP "ADO_LV_35" SITE "E30";
+LOCATE COMP "ADO_LV_36" SITE "F29";
+LOCATE COMP "ADO_LV_37" SITE "F30";
+LOCATE COMP "ADO_LV_38" SITE "M22";
+LOCATE COMP "ADO_LV_39" SITE "L22";
+LOCATE COMP "ADO_LV_40" SITE "G29";
+LOCATE COMP "ADO_LV_41" SITE "H29";
+LOCATE COMP "ADO_LV_42" SITE "L27";
+LOCATE COMP "ADO_LV_43" SITE "L28";
+LOCATE COMP "ADO_LV_44" SITE "L29";
+LOCATE COMP "ADO_LV_45" SITE "L30";
+LOCATE COMP "ADO_LV_46" SITE "M26";
+LOCATE COMP "ADO_LV_47" SITE "M25";
+LOCATE COMP "ADO_LV_48" SITE "G30";
+LOCATE COMP "ADO_LV_49" SITE "H30";
+LOCATE COMP "ADO_LV_50" SITE "M28";
+LOCATE COMP "ADO_LV_51" SITE "M27";
+LOCATE COMP "ADO_LV_52" SITE "N26";
+LOCATE COMP "ADO_LV_53" SITE "N25";
+LOCATE COMP "ADO_LV_54" SITE "N23";
+LOCATE COMP "ADO_LV_55" SITE "N24";
+LOCATE COMP "ADO_LV_56" SITE "J29";
+LOCATE COMP "ADO_LV_57" SITE "J30";
+LOCATE COMP "ADO_LV_58" SITE "P22";
+LOCATE COMP "ADO_LV_59" SITE "N22";
+LOCATE COMP "ADO_LV_60" SITE "K29";
+LOCATE COMP "ADO_LV_61" SITE "K30";
+
+DEFINE PORT GROUP "ADOLV_group" "ADO_LV*" ;
+IOBUF GROUP "ADOLV_group" IO_TYPE=LVCMOS25 PULLMODE=NONE DRIVE=12;
+
+
+#################################################################
+# To 1st FPGA
+#################################################################
+LOCATE COMP "FFC_0" SITE "R1";
+LOCATE COMP "FFC_1" SITE "T1";
+LOCATE COMP "FFC_2" SITE "T3";
+LOCATE COMP "FFC_3" SITE "T2";
+LOCATE COMP "FFC_4" SITE "U9";
+LOCATE COMP "FFC_5" SITE "U8";
+LOCATE COMP "FFC_6" SITE "U5";
+LOCATE COMP "FFC_7" SITE "U4";
+LOCATE COMP "FFC_8" SITE "V9";
+LOCATE COMP "FFC_9" SITE "V7";
+LOCATE COMP "FFC_10" SITE "U3";
+LOCATE COMP "FFC_11" SITE "U2";
+LOCATE COMP "FFC_12" SITE "V8";
+LOCATE COMP "FFC_13" SITE "U6";
+LOCATE COMP "FFC_14" SITE "U1";
+LOCATE COMP "FFC_15" SITE "V2";
+LOCATE COMP "FFC_16" SITE "V5";
+LOCATE COMP "FFC_17" SITE "V6";
+LOCATE COMP "FFC_18" SITE "V1";
+LOCATE COMP "FFC_19" SITE "W1";
+LOCATE COMP "FFC_20" SITE "W5";
+LOCATE COMP "FFC_21" SITE "W6";
+LOCATE COMP "FFC_22" SITE "W3";
+# LOCATE COMP "FFC_23" SITE "W4";
+LOCATE COMP "ONEWIRE_MONITOR_OUT" SITE "W4";
+
+DEFINE PORT GROUP "FFC_group" "FFC*" ;
+IOBUF GROUP "FFC_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
+IOBUF PORT "ONEWIRE_MONITOR_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4 ;
+
+#################################################################
+# LED
+#################################################################
+LOCATE COMP "LED_GBE_OK" SITE "AC30";
+LOCATE COMP "LED_GBE_RX" SITE "AB30";
+LOCATE COMP "LED_GBE_TX" SITE "AA30";
+LOCATE COMP "LED_TRB_OK" SITE "AC27";
+LOCATE COMP "LED_TRB_RX" SITE "AC28";
+LOCATE COMP "LED_TRB_TX" SITE "AC29";
+
+LOCATE COMP "LED_RED" SITE "R29";
+LOCATE COMP "LED_YELLOW" SITE "T27";
+LOCATE COMP "LED_GREEN" SITE "T26";
+LOCATE COMP "LED_ORANGE" SITE "N30";
+
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=8;
+
+#################################################################
+# SFP
+#################################################################
+LOCATE COMP "GBE_LOS" SITE "AG8";
+LOCATE COMP "GBE_MOD_0" SITE "AF8";
+LOCATE COMP "GBE_MOD_1" SITE "AE15";
+LOCATE COMP "GBE_MOD_2" SITE "AC15";
+LOCATE COMP "GBE_TX_DIS" SITE "AD14";
+
+LOCATE COMP "TRB_LOS" SITE "AG9";
+LOCATE COMP "TRB_MOD_0" SITE "AH14";
+LOCATE COMP "TRB_MOD_1" SITE "AG12";
+LOCATE COMP "TRB_MOD_2" SITE "AG15";
+LOCATE COMP "TRB_TX_DIS" SITE "AG10";
+
+DEFINE PORT GROUP "GBE_group" "GBE*" ;
+IOBUF GROUP "GBE_group" IO_TYPE=LVTTL33 PULLMODE=UP;
+
+DEFINE PORT GROUP "TRB_group" "TRB*" ;
+IOBUF GROUP "TRB_group" IO_TYPE=LVTTL33 PULLMODE=UP;
+
+#################################################################
+# Flash
+#################################################################
+LOCATE COMP "SPI_CLK_OUT" SITE "AE21";
+LOCATE COMP "SPI_CS_OUT" SITE "AE20";
+LOCATE COMP "SPI_SI_OUT" SITE "AC23";
+LOCATE COMP "SPI_SO_IN" SITE "AD23";
+LOCATE COMP "PROGRAMN_OUT" SITE "AJ14";
+
+DEFINE PORT GROUP "SPI_group" "SPI*" ;
+IOBUF GROUP "SPI_group" IO_TYPE=LVTTL33 PULLMODE=UP;
+IOBUF PORT "PROGRAMN_OUT" IO_TYPE=LVTTL33 PULLMODE=UP;
+
+#################################################################
+# RAM
+#################################################################
+LOCATE COMP "RAM_ADSCB" SITE "F14";
+LOCATE COMP "RAM_ADSPB" SITE "H14";
+LOCATE COMP "RAM_ADVB" SITE "J14";
+LOCATE COMP "RAM_CE_2" SITE "E15";
+LOCATE COMP "RAM_CEB" SITE "C14";
+LOCATE COMP "RAM_CLK" SITE "E16";
+LOCATE COMP "RAM_GWB" SITE "F15";
+LOCATE COMP "RAM_OEB" SITE "G14";
+
+LOCATE COMP "RAM_A_0" SITE "J18";
+LOCATE COMP "RAM_A_1" SITE "J19";
+LOCATE COMP "RAM_A_2" SITE "H17";
+LOCATE COMP "RAM_A_3" SITE "J17";
+LOCATE COMP "RAM_A_4" SITE "F18";
+LOCATE COMP "RAM_A_5" SITE "F17";
+LOCATE COMP "RAM_A_6" SITE "A16";
+LOCATE COMP "RAM_A_7" SITE "B16";
+LOCATE COMP "RAM_A_8" SITE "G17";
+LOCATE COMP "RAM_A_9" SITE "G16";
+LOCATE COMP "RAM_A_10" SITE "H16";
+LOCATE COMP "RAM_A_11" SITE "F16";
+LOCATE COMP "RAM_A_12" SITE "J16";
+LOCATE COMP "RAM_A_13" SITE "G15";
+LOCATE COMP "RAM_A_14" SITE "C16";
+LOCATE COMP "RAM_A_15" SITE "D16";
+LOCATE COMP "RAM_A_16" SITE "J15";
+LOCATE COMP "RAM_A_17" SITE "H15";
+LOCATE COMP "RAM_A_18" SITE "A15";
+LOCATE COMP "RAM_A_19" SITE "B15";
+
+LOCATE COMP "RAM_DQ_1" SITE "E23";
+LOCATE COMP "RAM_DQ_2" SITE "G22";
+LOCATE COMP "RAM_DQ_3" SITE "D22";
+LOCATE COMP "RAM_DQ_4" SITE "F21";
+LOCATE COMP "RAM_DQ_5" SITE "G18";
+LOCATE COMP "RAM_DQ_6" SITE "H18";
+LOCATE COMP "RAM_DQ_7" SITE "D20";
+LOCATE COMP "RAM_DQ_8" SITE "D21";
+LOCATE COMP "RAM_DQ_9" SITE "E20";
+LOCATE COMP "RAM_DQ_10" SITE "E19";
+LOCATE COMP "RAM_DQ_11" SITE "D19";
+LOCATE COMP "RAM_DQ_12" SITE "E18";
+LOCATE COMP "RAM_DQ_13" SITE "D18";
+LOCATE COMP "RAM_DQ_14" SITE "C17";
+LOCATE COMP "RAM_DQ_15" SITE "A17";
+LOCATE COMP "RAM_DQ_16" SITE "B17";
+LOCATE COMP "RAM_DQ_17" SITE "C15";
+LOCATE COMP "RAM_DQ_18" SITE "D15";
+
+LOCATE COMP "RAM_TCK" SITE "D26";
+LOCATE COMP "RAM_TDI" SITE "D23";
+LOCATE COMP "RAM_TDO" SITE "E26";
+LOCATE COMP "RAM_TMS" SITE "E21";
+
+DEFINE PORT GROUP "RAM_group" "RAM*" ;
+IOBUF GROUP "RAM_group" IO_TYPE=LVCMOS25 PULLMODE=UP;
+
+
+#################################################################
+# Debug
+#################################################################
+LOCATE COMP "TEST_LINE_0" SITE "J3";
+LOCATE COMP "TEST_LINE_1" SITE "J2";
+LOCATE COMP "TEST_LINE_2" SITE "H1";
+LOCATE COMP "TEST_LINE_3" SITE "J1";
+LOCATE COMP "TEST_LINE_4" SITE "L5";
+LOCATE COMP "TEST_LINE_5" SITE "L4";
+LOCATE COMP "TEST_LINE_6" SITE "N9";
+LOCATE COMP "TEST_LINE_7" SITE "N7";
+LOCATE COMP "TEST_LINE_8" SITE "K2";
+LOCATE COMP "TEST_LINE_9" SITE "K1";
+LOCATE COMP "TEST_LINE_10" SITE "P9";
+LOCATE COMP "TEST_LINE_11" SITE "P7";
+LOCATE COMP "TEST_LINE_12" SITE "M6";
+LOCATE COMP "TEST_LINE_13" SITE "M5";
+LOCATE COMP "TEST_LINE_14" SITE "N5";
+LOCATE COMP "TEST_LINE_15" SITE "N6";
+DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ;
+IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12;
+
+#################################################################
+# Other
+#################################################################
+LOCATE COMP "TEMPSENS" SITE "AF10";
+IOBUF PORT "TEMPSENS" IO_TYPE=LVTTL33 PULLMODE=UP;
+
+
+#################################################################
+# Signals not needed in lpf
+#################################################################
+# LOCATE COMP "DONE_F_2" SITE "AF27";
+# LOCATE COMP "F2_TO_F1_BN" SITE "AJ6";
+# LOCATE COMP "F2_TO_F1_AP" SITE "AK5";
+# LOCATE COMP "F2_TO_F1_AN" SITE "AJ5";
+# LOCATE COMP "F2_TO_F1_BP" SITE "AK6";
+# LOCATE COMP "F2_CFG_0" SITE "AG28";
+# LOCATE COMP "F1_TO_F2_BN" SITE "AJ3";
+# LOCATE COMP "F1_TO_F2_AP" SITE "AK2";
+# LOCATE COMP "F1_TO_F2_AN" SITE "AJ2";
+# LOCATE COMP "F1_TO_F2_BP" SITE "AK3";
+# LOCATE COMP "F2_CFG_1" SITE "AD25";
+# LOCATE COMP "F2_CFG_2" SITE "AG27";
+# LOCATE COMP "FS_PE_1" SITE "AF2";
+# LOCATE COMP "FS_PE_2" SITE "AE2";
+# LOCATE COMP "GBE_RXN" SITE "B29";
+# LOCATE COMP "GBE_RXP" SITE "A29";
+# LOCATE COMP "GBE_TXN" SITE "B26";
+# LOCATE COMP "GBE_TXP" SITE "A26";
+# LOCATE COMP "GBE_RATE_SEL" SITE "AD15";
+# LOCATE COMP "GBE_TX_FAULT" SITE "AF12";
+# LOCATE COMP "GND" SITE "Y17";
+# LOCATE COMP "INITN_F_2" SITE "AC24";
+# LOCATE COMP "TRB_RXN" SITE "AJ29";
+# LOCATE COMP "TRB_RXP" SITE "AK29";
+# LOCATE COMP "TRB_TXN" SITE "AJ26";
+# LOCATE COMP "TRB_TXP" SITE "AK26";
+# LOCATE COMP "TDO_F_1" SITE "AE1";
+# LOCATE COMP "TDO_F_2" SITE "AF1";
+# LOCATE COMP "SPI_CLK_F_2" SITE "AG29";
+# LOCATE COMP "SPI_CS_F_2" SITE "AA22";
+# LOCATE COMP "SPI_FAST" SITE "AF29";
+# LOCATE COMP "SPI_IN_F_2" SITE "AA23";
+# LOCATE COMP "SPI_OUT_F_2" SITE "AD30";
+# LOCATE COMP "N_18431150" SITE "T5";
+# LOCATE COMP "N_18431154" SITE "T4";
+# LOCATE COMP "N_18431301" SITE "R29";
+# LOCATE COMP "N_18431304" SITE "T27";
+# LOCATE COMP "N_18431307" SITE "T26";
+# LOCATE COMP "N_18431310" SITE "N30";
+# LOCATE COMP "N_18569491" SITE "AD26";
+# LOCATE COMP "N_18569495" SITE "AE30";
+# LOCATE COMP "N_18569497" SITE "AE29";
+# LOCATE COMP "N_18569499" SITE "AE26";
+# LOCATE COMP "N_18569501" SITE "AF28";
+# LOCATE COMP "N_18569511" SITE "AB23";
+# LOCATE COMP "N_18569543" SITE "AC25";
+# LOCATE COMP "N_18569545" SITE "AD29";
+# LOCATE COMP "N_18569559" SITE "G23";
+# LOCATE COMP "N_18569579" SITE "AC26";
+# LOCATE COMP "N_18569592" SITE "AB8";
+# LOCATE COMP "N_18569596" SITE "AB22";
+# LOCATE COMP "N_18569744" SITE "AF30";
+# LOCATE COMP "N_18645722" SITE "P1";
+# LOCATE COMP "N_18645740" SITE "N1";
+# LOCATE COMP "N_19273974" SITE "K2";
+# LOCATE COMP "N_19273977" SITE "K1";
+# LOCATE COMP "N_19273980" SITE "P9";
+# LOCATE COMP "N_19273983" SITE "P7";
+# LOCATE COMP "N_19273986" SITE "M6";
+# LOCATE COMP "N_19273989" SITE "M5";
+# LOCATE COMP "N_19273992" SITE "N5";
+# LOCATE COMP "N_19273995" SITE "N6";
+# LOCATE COMP "N_19273998" SITE "J3";
+# LOCATE COMP "N_19274001" SITE "J2";
+# LOCATE COMP "N_19274004" SITE "H1";
+# LOCATE COMP "N_19274007" SITE "J1";
+# LOCATE COMP "N_19274010" SITE "L5";
+# LOCATE COMP "N_19274013" SITE "L4";
+# LOCATE COMP "N_19274016" SITE "N9";
+# LOCATE COMP "N_19274019" SITE "N7";
+# LOCATE COMP "N_19511852" SITE "AF10";
+# LOCATE COMP "N_20664224" SITE "AJ14";
+# LOCATE COMP "TRB_RATE_SEL" SITE "AG13";
+# LOCATE COMP "TRB_TX_FAULT" SITE "AF15";
+COMMERCIAL ;
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+BLOCK RD_DURING_WR_PATHS ;
+
+#########################################
+# Clock Constraints
+#########################################
+ FREQUENCY PORT CLK_100_IN 100.000000 MHz HOLD_MARGIN 0.100000 nS ;
+ FREQUENCY PORT CLK_125_IN 125.000000 MHz HOLD_MARGIN 0.100000 nS ;
+
+
+
+#########################################
+# Serdes Placement
+#########################################
+REGION "MED0" "R9C100" 18 26 ;
+REGION "MED1" "R80C100" 25 26 ;
+
+LOCATE COMP "THE_MEDIA_INTERFACE_0/gen_serdes_0_THE_SERDES/PCSC_INST" SITE "URPCS" ;
+LOCATE UGROUP "THE_MEDIA_INTERFACE_0/media_interface_group" REGION "MED0" ;
+
+LOCATE COMP "THE_MEDIA_INTERFACE_1/gen_serdes_0_THE_SERDES/PCSC_INST" SITE "LRPCS" ;
+LOCATE UGROUP "THE_MEDIA_INTERFACE_1/media_interface_group" REGION "MED1" ;
+
+
+#########################################
+# Endpoint Placement
+#########################################
+REGION "ENDP_CTS_REGION" "R59C80" 52 48;
+REGION "ENDP_RDO_REGION" "R2C80" 56 48;
+
+#Readout endpoint
+
+LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_regio_regIO/RegIO_group" REGION "ENDP_RDO_REGION";
+
+LOCATE UGROUP "THE_RDO_BUS_HANDLER/Bus_handler_group" REGION "ENDP_RDO_REGION";
+
+
+LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "ENDP_RDO_REGION";
+LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_gen_api_DAT_PASSIVE_API/API_group" REGION "ENDP_RDO_REGION";
+
+LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "ENDP_RDO_REGION";
+LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "ENDP_RDO_REGION";
+LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "ENDP_RDO_REGION";
+
+# LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "ENDP_RDO_REGION";
+# LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "ENDP_RDO_REGION";
+# LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3/OBUF_group" REGION "ENDP_RDO_REGION";
+
+LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "ENDP_RDO_REGION";
+LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "ENDP_RDO_REGION";
+LOCATE UGROUP "THE_DATA_ENDPOINT/THE_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "ENDP_RDO_REGION";
+
+#CTS endpoint
+LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "ENDP_CTS_REGION";
+LOCATE UGROUP "THE_CTS_ENDPOINT/regIO/RegIO_group" REGION "ENDP_CTS_REGION";
+
+LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_0_geniobuf_gen_api_act_DAT_ACTIVE_API/API_group" REGION "ENDP_CTS_REGION";
+LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_1_geniobuf_gen_api_act_DAT_ACTIVE_API/API_group" REGION "ENDP_CTS_REGION";
+LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_3_geniobuf_gen_api_pas_DAT_PASSIVE_API/API_group" REGION "ENDP_CTS_REGION";
+
+LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_0_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "ENDP_CTS_REGION";
+LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_1_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "ENDP_CTS_REGION";
+LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_3_geniobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "ENDP_CTS_REGION";
+
+LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "ENDP_CTS_REGION";
+LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "ENDP_CTS_REGION";
+# LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genINITOBUF2_gen_INITOBUF3/OBUF_group" REGION "ENDP_CTS_REGION";
+
+# LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_0_geniobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3/OBUF_group" REGION "ENDP_CTS_REGION";
+# LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_1_geniobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3/OBUF_group" REGION "ENDP_CTS_REGION";
+LOCATE UGROUP "THE_CTS_ENDPOINT/genbuffers_3_geniobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "ENDP_CTS_REGION";
+
+
+
+
+
--- /dev/null
+#!/usr/bin/perl
+###########################################
+# Script file to run the flow
+#
+###########################################
+#
+# Command line for synplify_pro
+#
+
+
+use Data::Dumper;
+
+use warnings;
+use strict;
+my $lattice_path = '/opt/lattice/diamond/1.3/';
+#my $lattice_path = '/opt/lattice/ispLEVER8.0/isptools/';
+#my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/';
+#my $synplify_path = '/opt/synplicity/D-2009.12/bin/';
+#my $synplify_path = '/opt/synplicity/D-2010.03-SP1-1/bin/';
+#my $synplify_path = '/opt/synplicity/fpga_e201009sp2/bin/';
+my $synplify_path = '/opt/synplicity/fpga_e201103/bin/';
+use FileHandle;
+
+$ENV{'SYNPLIFY'}=$synplify_path;
+$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1;
+$ENV{'LM_LICENSE_FILE'}="27000\@lxcad01.gsi.de";
+
+
+my $TOPNAME="cts_fpga2";
+
+my $FAMILYNAME="LATTICEECP2M";
+my $DEVICENAME="LFE2M100E";
+my $PACKAGE="FPBGA900";
+my $SPEEDGRADE="5";
+
+
+#create full lpf file
+system("cp ../trbnet/pinout/$TOPNAME.lpf workdir/$TOPNAME.lpf");
+system("cat constraints_$TOPNAME.lpf >> workdir/$TOPNAME.lpf");
+
+#set -e
+#set -o errexit
+
+#generate timestamp
+my $t=time;
+my $fh = new FileHandle(">version.vhd");
+die "could not open file" if (! defined $fh);
+print $fh <<EOF;
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := $t;
+
+end package version;
+EOF
+$fh->close;
+
+system("env| grep LM_");
+my $r = "";
+#my $c=$synplify_path."synplify_pro_oem -batch $TOPNAME".".prj";
+#my $c="$synplify_path/bin/synplify_pro -Pro -prj $TOPNAME".".prj";
+my $c="$synplify_path/synplify_premier_dp -batch $TOPNAME".".prj";
+#my $c="$synplify_path/bin/synpwrap -Pro -prj $TOPNAME".".prj";
+$r=execute($c, "do_not_exit" );
+
+
+chdir "workdir";
+$fh = new FileHandle("<$TOPNAME".".srr");
+my @a = <$fh>;
+$fh -> close;
+
+#if ($r) {
+#$c="cat $TOPNAME.srr";
+#system($c);
+#exit 129;
+#}
+
+foreach (@a)
+{
+ if(/\@E:/)
+ {
+ $c="cat $TOPNAME.srr";
+ system($c);
+ print "bdabdhsadbhjasdhasldhbas";
+ exit 129;
+ }
+}
+#if (0){
+
+$ENV{'LM_LICENSE_FILE'}="1710\@cronos.e12.physik.tu-muenchen.de";
+
+$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/or5s00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|;
+execute($c);
+
+my $tpmap = $TOPNAME . "_map" ;
+
+$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|;
+execute($c);
+
+
+system("rm $TOPNAME.ncd");
+
+#$c=qq|$lattice_path/ispfpga/bin/lin/par -w -y -l 4 -i 15 "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |;
+#$c=qq|$lattice_path/ispfpga/bin/lin/par -f $TOPNAME.p2t "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf" |;
+$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|;
+execute($c);
+
+# IOR IO Timing Report
+$c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+# TWR Timing Report
+#$c=qq|$lattice_path/ispfpga/bin/lin/tg "$TOPNAME.ncd" "$TOPNAME.prf"|;
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+$c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|;
+execute($c);
+
+
+$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" -f "$TOPNAME.t2b" "$TOPNAME.prf"|;
+execute($c);
+
+chdir "..";
+
+exit;
+
+sub execute {
+ my ($c, $op) = @_;
+ #print "option: $op \n";
+ $op = "" if(!$op);
+ print "\n\ncommand to execute: $c \n";
+ $r=system($c);
+ if($r) {
+ print "$!";
+ if($op ne "do_not_exit") {
+ exit;
+ }
+ }
+
+ return $r;
+
+}
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+
+entity cts_fpga2_lvl1_data_downscale is
+
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ LVL1_TRIGGER_IN : in std_logic;
+ LVL1_DOWNSCALE_IN : in std_logic_vector(15 downto 0);
+ LVL1_INFO_OUT : out std_logic
+ );
+end cts_fpga2_lvl1_data_downscale;
+
+architecture cts_fpga2_lvl1_data_downscale of cts_fpga2_lvl1_data_downscale is
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ signal downscale_cntr_rst, downscale_info, downscale_info_sync : std_logic;
+ signal downscale_cntr : std_logic_vector(15 downto 0);
+
+begin
+
+ LVL1_TRIGGCNTR_FOR_DWNSCL: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 16)
+ port map (
+ CLK => CLK,
+ RESET => downscale_cntr_rst,
+ COUNT_OUT => downscale_cntr,
+ UP_IN => LVL1_TRIGGER_IN,
+ DOWN_IN => '0');
+
+ RESET_DOWNSCALE_CNTR : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ downscale_cntr_rst <= '1';
+ elsif downscale_cntr = LVL1_DOWNSCALE_IN then
+ downscale_cntr_rst <= '1';
+ else
+ downscale_cntr_rst <= '0';
+ end if;
+ end if;
+ end process RESET_DOWNSCALE_CNTR;
+
+ SET_INFO_OUT : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or downscale_cntr = 1 then
+ downscale_info <= '1';
+ elsif downscale_cntr = LVL1_DOWNSCALE_IN then
+ downscale_info <= '0';
+ end if;
+ end if;
+ end process SET_INFO_OUT;
+
+ LVL1_INFO_OUT <= downscale_info;
+
+end cts_fpga2_lvl1_data_downscale;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+--use work.cts_components.all;
+
+entity cts_fpga2_lvl1_lvl2_fifo is
+
+ generic (
+ SIZE_OF_DATA_BUS_IN : natural;
+ FPGA_TYPE : natural
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ FPGA1_CLK_IN : in std_logic;
+ DATA_IN : in std_logic_vector(SIZE_OF_DATA_BUS_IN-1 downto 0);
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ WR_EN_IN : in std_logic;
+ RD_EN_IN : in std_logic;
+ RCNT_OUT : out std_logic_vector(9 downto 0);
+ EMPTY_OUT : out std_logic;
+ FULL_OUT : out std_logic
+ );
+end cts_fpga2_lvl1_lvl2_fifo;
+
+architecture cts_fpga2_lvl1_lvl2_fifo of cts_fpga2_lvl1_lvl2_fifo is
+
+ component fifo_1bit_to_32bit
+ port (
+ Data : in std_logic_vector(0 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ RCNT : out std_logic_vector(9 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+end component;
+
+component fifo_2bit_to_32bit
+ port (
+ Data : in std_logic_vector(1 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ RCNT : out std_logic_vector(9 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+end component;
+
+component fifo_4bit_to_32bit
+ port (
+ Data : in std_logic_vector(3 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ RCNT : out std_logic_vector(9 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+end component;
+
+
+component fifo_8bit_to_32bit
+ port (
+ Data : in std_logic_vector(7 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ RCNT : out std_logic_vector(9 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+end component;
+
+component fifo_16bit_to_32bit
+ port (
+ Data : in std_logic_vector(15 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ RCNT : out std_logic_vector(9 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+end component;
+
+
+--scm
+
+ component scm_fifo_1bit_to_32bit
+ port (
+ Data : in std_logic_vector(0 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+ component scm_fifo_2bit_to_32bit
+ port (
+ Data : in std_logic_vector(1 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+ component scm_fifo_4bit_to_32bit
+ port (
+ Data : in std_logic_vector(3 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+ component scm_fifo_8bit_to_32bit
+ port (
+ Data : in std_logic_vector(7 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+ component scm_fifo_16bit_to_32bit
+ port (
+ Data : in std_logic_vector(15 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+ component scm_fifo_32bit_to_32bit
+ port (
+ Data : in std_logic_vector(31 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+
+ signal data_in_i : std_logic_vector(SIZE_OF_DATA_BUS_IN-1 downto 0);
+ signal fpga1_clk_in_i, clk_i, wr_en_in_i, rd_en_in_i,reset_i,empty_out_i,full_out_i : std_logic;
+ signal data_out_i : std_logic_vector(31 downto 0);
+ signal rcnt_out_i : std_logic_vector(9 downto 0);
+
+begin
+
+
+
+ data_in_i <= DATA_IN;
+ fpga1_clk_in_i <= FPGA1_CLK_IN;
+ clk_i <= CLK;
+ wr_en_in_i <= WR_EN_IN;
+ rd_en_in_i <= RD_EN_IN;
+ reset_i <= RESET;
+ reset_i <= RESET;
+ DATA_OUT <= data_out_i;
+ RCNT_OUT <= rcnt_out_i;
+ EMPTY_OUT <= empty_out_i;
+ FULL_OUT <= full_out_i;
+
+ FIFO_1BIT: if SIZE_OF_DATA_BUS_IN = 1 and FPGA_TYPE = 1 generate
+ THE_FIFO_1BIT_TO_32BIT: fifo_1bit_to_32bit
+ port map (
+ Data => data_in_i,
+ WrClock => fpga1_clk_in_i,
+ RdClock => clk_i,
+ WrEn => wr_en_in_i,
+ RdEn => rd_en_in_i,
+ Reset => reset_i,
+ RPReset => reset_i,
+ Q => data_out_i,
+ RCNT => rcnt_out_i,
+ Empty => empty_out_i,
+ Full => full_out_i);
+ end generate FIFO_1BIT;
+
+ FIFO_2BIT: if SIZE_OF_DATA_BUS_IN = 2 and FPGA_TYPE = 1 generate
+ THE_FIFO_2BIT_TO_32BIT: fifo_2bit_to_32bit
+ port map (
+ Data => data_in_i,
+ WrClock => fpga1_clk_in_i,
+ RdClock => clk_i,
+ WrEn => wr_en_in_i,
+ RdEn => rd_en_in_i,
+ Reset => reset_i,
+ RPReset => reset_i,
+ Q => data_out_i,
+ RCNT => rcnt_out_i,
+ Empty => empty_out_i,
+ Full => full_out_i);
+ end generate FIFO_2BIT;
+
+ FIFO_4BIT: if SIZE_OF_DATA_BUS_IN = 4 and FPGA_TYPE = 1 generate
+ THE_FIFO_4BIT_TO_32BIT: fifo_4bit_to_32bit
+ port map (
+ Data => data_in_i,
+ WrClock => fpga1_clk_in_i,
+ RdClock => clk_i,
+ WrEn => wr_en_in_i,
+ RdEn => rd_en_in_i,
+ Reset => reset_i,
+ RPReset => reset_i,
+ Q => data_out_i,
+ RCNT => rcnt_out_i,
+ Empty => empty_out_i,
+ Full => full_out_i);
+ end generate FIFO_4BIT;
+
+ FIFO_8BIT: if SIZE_OF_DATA_BUS_IN = 8 and FPGA_TYPE = 1 generate
+ THE_FIFO_8BIT_TO_32BIT: fifo_8bit_to_32bit
+ port map (
+ Data => data_in_i,
+ WrClock => fpga1_clk_in_i,
+ RdClock => clk_i,
+ WrEn => wr_en_in_i,
+ RdEn => rd_en_in_i,
+ Reset => reset_i,
+ RPReset => reset_i,
+ Q => data_out_i,
+ RCNT => rcnt_out_i,
+ Empty => empty_out_i,
+ Full => full_out_i);
+ end generate FIFO_8BIT;
+
+ FIFO_16BIT: if SIZE_OF_DATA_BUS_IN = 16 and FPGA_TYPE = 1 generate
+ THE_FIFO_16BIT_TO_32BIT: fifo_16bit_to_32bit
+ port map (
+ Data => data_in_i,
+ WrClock => fpga1_clk_in_i,
+ RdClock => clk_i,
+ WrEn => wr_en_in_i,
+ RdEn => rd_en_in_i,
+ Reset => reset_i,
+ RPReset => reset_i,
+ Q => data_out_i,
+ RCNT => rcnt_out_i,
+ Empty => empty_out_i,
+ Full => full_out_i);
+ end generate FIFO_16BIT;
+
+ -----------------------------------------------------------------------------
+ -- scm
+ -----------------------------------------------------------------------------
+
+
+ SCM_FIFO_1BIT: if SIZE_OF_DATA_BUS_IN = 1 and FPGA_TYPE = 0 generate
+ SCM_THE_FIFO_1BIT_TO_32BIT: scm_fifo_1bit_to_32bit
+ port map (
+ Data => data_in_i,
+ WrClock => fpga1_clk_in_i,
+ RdClock => clk_i,
+ WrEn => wr_en_in_i,
+ RdEn => rd_en_in_i,
+ Reset => reset_i,
+ RPReset => reset_i,
+ Q => data_out_i,
+ Empty => empty_out_i,
+ Full => full_out_i,
+ AlmostEmpty => open,
+ AlmostFull => open);
+ end generate SCM_FIFO_1BIT;
+
+ SCM_FIFO_2BIT: if SIZE_OF_DATA_BUS_IN = 2 and FPGA_TYPE = 0 generate
+ SCM_THE_FIFO_2BIT_TO_32BIT: scm_fifo_2bit_to_32bit
+ port map (
+ Data => data_in_i,
+ WrClock => fpga1_clk_in_i,
+ RdClock => clk_i,
+ WrEn => wr_en_in_i,
+ RdEn => rd_en_in_i,
+ Reset => reset_i,
+ RPReset => reset_i,
+ Q => data_out_i,
+ Empty => empty_out_i,
+ Full => full_out_i,
+ AlmostEmpty => open,
+ AlmostFull => open);
+ end generate SCM_FIFO_2BIT;
+
+ SCM_FIFO_4BIT: if SIZE_OF_DATA_BUS_IN = 4 and FPGA_TYPE = 0 generate
+ SCM_THE_FIFO_4BIT_TO_32BIT: scm_fifo_4bit_to_32bit
+ port map (
+ Data => data_in_i,
+ WrClock => fpga1_clk_in_i,
+ RdClock => clk_i,
+ WrEn => wr_en_in_i,
+ RdEn => rd_en_in_i,
+ Reset => reset_i,
+ RPReset => reset_i,
+ Q => data_out_i,
+ Empty => empty_out_i,
+ Full => full_out_i,
+ AlmostEmpty => open,
+ AlmostFull => open);
+ end generate SCM_FIFO_4BIT;
+
+ SCM_FIFO_8BIT: if SIZE_OF_DATA_BUS_IN = 8 and FPGA_TYPE = 0 generate
+ SCM_THE_FIFO_8BIT_TO_32BIT: scm_fifo_8bit_to_32bit
+ port map (
+ Data => data_in_i,
+ WrClock => fpga1_clk_in_i,
+ RdClock => clk_i,
+ WrEn => wr_en_in_i,
+ RdEn => rd_en_in_i,
+ Reset => reset_i,
+ RPReset => reset_i,
+ Q => data_out_i,
+ Empty => empty_out_i,
+ Full => full_out_i,
+ AlmostEmpty => open,
+ AlmostFull => open);
+ end generate SCM_FIFO_8BIT;
+
+ SCM_FIFO_16BIT: if SIZE_OF_DATA_BUS_IN = 16 and FPGA_TYPE = 0 generate
+ SCM_THE_FIFO_16BIT_TO_32BIT: scm_fifo_16bit_to_32bit
+ port map (
+ Data => data_in_i,
+ WrClock => fpga1_clk_in_i,
+ RdClock => clk_i,
+ WrEn => wr_en_in_i,
+ RdEn => rd_en_in_i,
+ Reset => reset_i,
+ RPReset => reset_i,
+ Q => data_out_i,
+ Empty => empty_out_i,
+ Full => full_out_i,
+ AlmostEmpty => open,
+ AlmostFull => open);
+ end generate SCM_FIFO_16BIT;
+
+end cts_fpga2_lvl1_lvl2_fifo;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use work.version.all;
+use ieee.std_logic_arith.all;
+
+entity cts_fpga2_lvl2 is
+ generic (
+ MAX_NUMBER_OF_BUFFERED_LVL2_EVENTS : natural
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ SELECT_LVL2_SOURCE_IN : in std_logic;
+ LVL1_TRIGGER_IN : in std_logic;
+ LVL1_TRIGGER_RND_CODE_IN : in std_logic_vector(7 downto 0);
+ LVL1_TRIGGER_TYPE_IN : in std_logic_vector(3 downto 0);
+ LVL1_TRIGGER_TAG_IN : in std_logic_vector(15 downto 0);
+ LVL1_BUSY_IN : in std_logic;
+ LVL1_BACK_PRESURE_BUSY_OUT : out std_logic;
+ LVL2_TRBNET_BUSY_IN : in std_logic;
+ LVL2_TRIGGER_OUT : out std_logic;
+ LVL2_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL2_TRIGGER_CODE_OUT : out std_logic_vector(3 downto 0);
+ LVL2_RND_NUMBER_OUT : out std_logic_vector(7 downto 0);
+ LV2_LVL1_TYPE_FOR_CAL_OUT : out std_logic_vector(3 downto 0);
+ LVL2_STATUS_0UT_0 : out std_logic_vector(31 downto 0);
+ LVL2_STATUS_0UT_1 : out std_logic_vector(31 downto 0);
+
+ LVL2_CNTRL_IN : in std_logic_vector(31 downto 0)
+ );
+end cts_fpga2_lvl2;
+
+architecture cts_fpga2_lvl2 of cts_fpga2_lvl2 is
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ component ecp2m_lvl2_trigger_buffer_fifo_1kW
+ port (
+ Data : in std_logic_vector(33 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(33 downto 0);
+ WCNT : out std_logic_vector(9 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+ end component;
+
+ signal not_lvl2_busy, not_lvl1_busy, lvl1_busy_finished_pulse, lvl2_busy_finished_pulse, lvl2_trigger_buffer_busy : std_logic;
+ signal trigger_buffer_fifo_data_cntr : std_logic_vector(9 downto 0);
+ signal lvl2_trigger_code : std_logic_vector(3 downto 0);
+ signal lvl2_trigger_code_and_tag : std_logic_vector(33 downto 0);
+ signal lvl2_trigger_code_and_tag_out : std_logic_vector(33 downto 0);
+ signal trigger_buffer_fifo_empty, trigger_buffer_fifo_full : std_logic;
+ signal lvl1_lvl2_diff_cntr : std_logic_vector(9 downto 0);
+ signal lvl2_trigger_out_i, lvl2_trigger_out_pulse, lvl2_trigger_out_pulse_sync_a, lvl2_trigger_out_pulse_sync_b, lvl2_trigger_out_pulse_sync_c, lvl2_trigger_out_pulse_sync_d : std_logic;
+ signal lvl1_back_presure_busy_out_i : std_logic;
+begin
+
+ NOT_BUSY : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ not_lvl2_busy <= '0';
+ not_lvl1_busy <= '0';
+ else
+ not_lvl2_busy <= not LVL2_TRBNET_BUSY_IN;
+ not_lvl1_busy <= not LVL1_BUSY_IN;
+ end if;
+ end if;
+ end process NOT_BUSY;
+
+ THE_LVL2_BUSY_END_PULSER: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_lvl2_busy,
+ pulse => lvl2_busy_finished_pulse
+ );
+
+ SET_LVL2_BUSY : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or lvl2_busy_finished_pulse = '1' then
+ lvl2_trigger_buffer_busy <= '0';
+ elsif lvl2_trigger_out_pulse = '1' then
+ lvl2_trigger_buffer_busy <= '1';
+ else
+ lvl2_trigger_buffer_busy <= lvl2_trigger_buffer_busy;
+ end if;
+ end if;
+ end process SET_LVL2_BUSY;
+
+ LVL2_STATUS_0UT_0 <= lvl2_trigger_buffer_busy & lvl1_back_presure_busy_out_i & lvl1_lvl2_diff_cntr & trigger_buffer_fifo_data_cntr(3 downto 0) & lvl2_trigger_code_and_tag_out(15 downto 0);
+
+ lvl2_trigger_code <= x"1";
+ --lvl2_trigger_code_and_tag <= "00" & x"0" & LVL1_TRIGGER_RND_CODE_IN & lvl2_trigger_code & LVL1_TRIGGER_TAG_IN;
+ lvl2_trigger_code_and_tag <= "00" & LVL1_TRIGGER_TYPE_IN & LVL1_TRIGGER_RND_CODE_IN & lvl2_trigger_code & LVL1_TRIGGER_TAG_IN;
+
+
+ ecp2m_lvl2_trigger_buffer_fifo_1kW_1: ecp2m_lvl2_trigger_buffer_fifo_1kW
+ port map (
+ Data => lvl2_trigger_code_and_tag,
+ Clock => CLK,
+ WrEn => LVL1_TRIGGER_IN,
+ RdEn => lvl2_trigger_out_pulse,
+ Reset => RESET,
+ Q => lvl2_trigger_code_and_tag_out,
+ WCNT => trigger_buffer_fifo_data_cntr,
+ Empty => trigger_buffer_fifo_empty,
+ Full => trigger_buffer_fifo_full);
+
+ THE_LVL1_BUSY_END_PULSER: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_lvl1_busy,
+ pulse => lvl1_busy_finished_pulse
+ );
+
+ THE_LVL1_LVL2_DIFF_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 10)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ COUNT_OUT => lvl1_lvl2_diff_cntr,
+ UP_IN => lvl1_busy_finished_pulse,
+ DOWN_IN => lvl2_trigger_out_pulse);
+ LVL2_STATUS_0UT_1(9 downto 0) <= lvl1_lvl2_diff_cntr;
+
+ STOP_LVL1_LVL2_IS_FULL : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_back_presure_busy_out_i <= '0';
+ elsif lvl1_lvl2_diff_cntr > MAX_NUMBER_OF_BUFFERED_LVL2_EVENTS then
+ lvl1_back_presure_busy_out_i <= '1';
+ else
+ lvl1_back_presure_busy_out_i <= '0';
+ end if;
+ end if;
+ end process STOP_LVL1_LVL2_IS_FULL;
+ LVL1_BACK_PRESURE_BUSY_OUT <= lvl1_back_presure_busy_out_i;
+
+ SEND_LVL2_TRIGGER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_trigger_out_i <= '0';
+ elsif (lvl1_lvl2_diff_cntr > LVL2_CNTRL_IN(7 downto 0)) and trigger_buffer_fifo_empty = '0' and lvl2_trigger_buffer_busy = '0' then
+ lvl2_trigger_out_i <= '1';
+ else
+ lvl2_trigger_out_i <= '0';
+ end if;
+ end if;
+ end process SEND_LVL2_TRIGGER;
+
+ THE_LVL2_TRIGGER_OUT_EDGE_TO_PULSE: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl2_trigger_out_i,
+ pulse => lvl2_trigger_out_pulse
+ );
+
+ DELAY_LVL2_TRIGGER_TO_PREPARE_DATA : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_trigger_out_pulse_sync_a <= '0';
+ lvl2_trigger_out_pulse_sync_b <= '0';
+ lvl2_trigger_out_pulse_sync_c <= '0';
+ lvl2_trigger_out_pulse_sync_d <= '0';
+ else
+ lvl2_trigger_out_pulse_sync_a <= lvl2_trigger_out_pulse;
+ lvl2_trigger_out_pulse_sync_b <= lvl2_trigger_out_pulse_sync_a;
+ lvl2_trigger_out_pulse_sync_c <= lvl2_trigger_out_pulse_sync_b;
+ lvl2_trigger_out_pulse_sync_d <= lvl2_trigger_out_pulse_sync_c;
+ end if;
+ end if;
+ end process DELAY_LVL2_TRIGGER_TO_PREPARE_DATA;
+
+ LVL2_TRIGGER_OUT <= lvl2_trigger_out_pulse_sync_d;
+ LVL2_TRIGGER_TAG_OUT <= lvl2_trigger_code_and_tag_out(15 downto 0);
+ LVL2_TRIGGER_CODE_OUT <= lvl2_trigger_code_and_tag_out(19 downto 16);
+ LVL2_RND_NUMBER_OUT <= lvl2_trigger_code_and_tag_out(27 downto 20);
+ LV2_LVL1_TYPE_FOR_CAL_OUT <= lvl2_trigger_code_and_tag_out(31 downto 28);
+
+end cts_fpga2_lvl2;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+
+entity cts_fpga2_reg_interface is
+
+ generic (
+ RW_REGISTERS_NUMBER : natural;
+ R_REGISTERS_NUMBER : natural;
+ DOWN_WIDTH : natural;
+ UP_WIDTH : natural
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ --regio
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
+ REGIO_READ_ENABLE_IN : in std_logic;
+ REGIO_WRITE_ENABLE_IN : in std_logic;
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0);
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
+ REGIO_DATAREADY_OUT : out std_logic;
+ REGIO_NO_MORE_DATA_OUT : out std_logic;
+ REGIO_WRITE_ACK_OUT : out std_logic;
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic;
+ -- local registers
+ RW_REGISTER_OUT : out std_logic_vector(RW_REGISTERS_NUMBER*32 -1 downto 0);
+ R_REGISTER_IN : in std_logic_vector(R_REGISTERS_NUMBER*32 -1 downto 0);
+ -- from fpga 2
+ DOWN_DATA_IN : in std_logic_vector(DOWN_WIDTH - 1 downto 0);
+ DOWN_CLK_IN : in std_logic;
+ DOWN_DATA_VALID_IN : in std_logic;
+ --to fpga 1
+ RW_DATA_OUT : out std_logic_vector(UP_WIDTH - 1 downto 0);
+ RW_DATA_VALID_OUT : out std_logic;
+ RW_CLK_OUT : out std_logic
+ );
+end cts_fpga2_reg_interface;
+
+architecture cts_fpga2_reg_interface of cts_fpga2_reg_interface is
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+ component cts_fpga2_lvl1_lvl2_fifo
+ generic (
+ SIZE_OF_DATA_BUS_IN : natural;
+ FPGA_TYPE : natural);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ FPGA1_CLK_IN : in std_logic;
+ DATA_IN : in std_logic_vector(SIZE_OF_DATA_BUS_IN-1 downto 0);
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ WR_EN_IN : in std_logic;
+ RD_EN_IN : in std_logic;
+ RCNT_OUT : out std_logic_vector(9 downto 0);
+ EMPTY_OUT : out std_logic;
+ FULL_OUT : out std_logic);
+ end component;
+
+ component cts_fpga2_reg_mem
+ port (
+ WrAddress : in std_logic_vector(12 downto 0);
+ RdAddress : in std_logic_vector(12 downto 0);
+ Data : in std_logic_vector(31 downto 0);
+ WE : in std_logic;
+ RdClock : in std_logic;
+ RdClockEn : in std_logic;
+ Reset : in std_logic;
+ WrClock : in std_logic;
+ WrClockEn : in std_logic;
+ Q : out std_logic_vector(31 downto 0));
+ end component;
+
+ signal unknown_addr,unknown_addr_pulse : std_logic;
+ signal saved_mode : std_logic;
+ signal saved_address : std_logic_vector(15 downto 0);
+ signal saved_data : std_logic_vector(31 downto 0);
+ signal data_out : std_logic_vector(31 downto 0);
+ signal data_out_select_int : integer range 0 to 255:=0;
+
+ signal ack_out_synch_a : std_logic;
+ signal ack_out_synch_b : std_logic;
+ signal ack_out_synch_c : std_logic;
+ signal ack_out_synch_d : std_logic;
+ signal ack_out_synch_e : std_logic;
+
+ signal rw_register_i : std_logic_vector(RW_REGISTERS_NUMBER*32 -1 downto 0);
+
+ --registers from fpga1
+ signal reg_mem_data : std_logic_vector(31 downto 0);
+ signal down_data_all_cntr_up, down_data_all_rst, down_data_all_rst_a, down_data_all_rst_b, down_data_empty, down_data_full: std_logic;
+ signal down_data_all_cntr, down_data_all_cntr_sync : std_logic_vector(12 downto 0);
+ signal down_data_out_i : std_logic_vector(31 downto 0);
+ signal cts_fpga2_reg_mem_wr_en, cts_fpga2_reg_mem_wr_en_sync : std_logic;
+ signal cts_fpga2_reg_mem_addr : std_logic_vector(12 downto 0);
+ signal reg_fifo_rst : std_logic;
+ signal reg_fifo_rst_pulse : std_logic;
+
+ --rw reg to fpga1
+ signal slow_data_cntr, slow_data_cntr_sync : std_logic_vector(0 downto 0);
+ signal rw_reg_cntr_rst, rw_reg_cntr_rst_fsm, rw_reg_cntr_up, rw_reg_cntr_up_fsm : std_logic;
+ signal rw_reg_cntr : std_logic_vector(7 downto 0);
+ signal rw_reg_data : std_logic_vector(63 downto 0);
+ type RW_DATA_SEND is (IDLE, RW_REG_PREPARE_A, RW_REG_SEND);
+ signal RW_DATA_SEND_CURRENT, RW_DATA_SEND_NEXT : RW_DATA_SEND;
+ signal rw_reg_integer_cntr : integer range 0 to 64:=0;
+ signal rw_data_out_i, rw_data_out_fsm : std_logic_vector(UP_WIDTH - 1 downto 0);
+ signal rw_data_valid_out_i, rw_data_valid_out_fsm, rw_data_valid_out_tmp, rw_data_valid_out_sync : std_logic;
+ signal rw_data_send_debug, rw_data_send_debug_fsm : std_logic_vector(3 downto 0);
+
+begin
+
+ SAVE_REQUEST : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ saved_mode <= '0';
+ saved_address <= (others => '0');
+ saved_data <= (others => '0');
+ elsif REGIO_READ_ENABLE_IN = '1' then
+ saved_mode <= '1';
+ saved_address <= REGIO_ADDR_IN;
+ saved_data <= REGIO_DATA_IN;
+ elsif REGIO_WRITE_ENABLE_IN = '1' then
+ saved_mode <= '0';
+ saved_address <= REGIO_ADDR_IN;
+ saved_data <= REGIO_DATA_IN;
+ else
+ saved_mode <= saved_mode;
+ saved_address <= saved_address;
+ saved_data <= saved_data;
+ end if;
+ end if;
+ end process SAVE_REQUEST;
+
+ SET_UNKNOWN_ADDR_OUT : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ unknown_addr <= '0';
+-- elsif saved_mode = '1' and saved_address(15 downto 8) = x"A0" and (saved_address(7 downto 0) < RW_REGISTERS_NUMBER +192) then
+-- unknown_addr <= '0';
+-- elsif saved_mode = '1' and saved_address(15 downto 8) = x"A1" and saved_address(7 downto 0) < SPECIAL_REGISTERS_NUMBER then
+-- unknown_addr <= '0';
+-- elsif saved_mode = '0' and saved_address(15 downto 8) = x"A0" and saved_address(7 downto 0) > x"c0" and saved_address(7 downto 0) < 191 + RW_REGISTERS_NUMBER then
+-- unknown_addr <= '0';
+ elsif (saved_address(15 downto 12) = x"A") or (saved_address(15 downto 12) = x"B") then
+ unknown_addr <= '0';
+ else
+ unknown_addr <= '1';
+ end if;
+ end if;
+ end process SET_UNKNOWN_ADDR_OUT;
+-- unknown_addr <= '0';
+
+-- THE_UNKNOWN_ADDR_PULSE: edge_to_pulse
+-- port map (
+-- clock => CLK,
+-- en_clk => '1',
+-- signal_in => unknown_addr,
+-- pulse => unknown_addr_pulse);
+
+ REGIO_UNKNOWN_ADDR_OUT <= unknown_addr and ack_out_synch_d; --'0'
+
+ CHANGE_ADDR_TO_INT : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ data_out_select_int <= 0;
+ else
+ data_out_select_int <= conv_integer(saved_address(3 downto 0));
+ end if;
+ end if;
+ end process CHANGE_ADDR_TO_INT;
+
+ SELECT_DATA_FOR_READ : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ data_out <= (others => '0');
+ elsif saved_address(15 downto 4) = x"A0f" and saved_address(3) = '0' and saved_mode = '1' then
+ data_out <= rw_register_i((data_out_select_int+1)*32-1 downto data_out_select_int*32);
+ elsif saved_address(15 downto 4) = x"A0f" and saved_address(3) = '1' and saved_mode = '1' then
+ data_out <= R_REGISTER_IN((data_out_select_int+1)*32-1 downto data_out_select_int*32);
+ else
+ data_out <= reg_mem_data;
+ end if;
+ end if;
+ end process SELECT_DATA_FOR_READ;
+
+ REGIO_DATA_OUT <= data_out;
+
+ SAVE_DATA : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ rw_register_i <= (others => '0');
+-- elsif saved_mode = '0' and ack_out_synch_d = '1' then
+ elsif saved_address(15 downto 4) = x"A0f" and saved_mode = '0' and ack_out_synch_d = '1' then
+ rw_register_i((data_out_select_int+1)*32-1 downto data_out_select_int*32) <= saved_data;
+ end if;
+ end if;
+ end process SAVE_DATA;
+
+ RW_REGISTER_OUT <= rw_register_i;
+
+ SET_ACK_OUT : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ ack_out_synch_a <= '0';
+ ack_out_synch_b <= '0';
+ ack_out_synch_c <= '0';
+ ack_out_synch_d <= '0';
+ ack_out_synch_e <= '0';
+ else
+ ack_out_synch_e <= ack_out_synch_d;
+ ack_out_synch_d <= ack_out_synch_c;
+ ack_out_synch_c <= ack_out_synch_b;
+ ack_out_synch_b <= ack_out_synch_a;
+ ack_out_synch_a <= REGIO_WRITE_ENABLE_IN or REGIO_READ_ENABLE_IN;
+ end if;
+ end if;
+ end process SET_ACK_OUT;
+
+ REGIO_NO_MORE_DATA_OUT <= ack_out_synch_e and (not unknown_addr);
+ REGIO_DATAREADY_OUT <= ack_out_synch_d and saved_mode and (not unknown_addr);
+ REGIO_WRITE_ACK_OUT <= ack_out_synch_d and (not (saved_mode)) and (not unknown_addr);
+
+ -----------------------------------------------------------------------------
+ -- registers from fpga1
+ -----------------------------------------------------------------------------
+
+ MAKE_FIFO_PULSE_RST: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => reg_fifo_rst,
+ pulse => reg_fifo_rst_pulse);
+
+ THE_CTS_FPGA2_LVL2_FIFO: cts_fpga2_lvl1_lvl2_fifo
+ generic map (
+ SIZE_OF_DATA_BUS_IN => DOWN_WIDTH,
+ FPGA_TYPE => 1)
+ port map (
+ RESET => reg_fifo_rst_pulse,
+ CLK => CLK,
+ FPGA1_CLK_IN => DOWN_CLK_IN,
+ DATA_IN => DOWN_DATA_IN,
+ DATA_OUT => down_data_out_i,
+ WR_EN_IN => DOWN_DATA_VALID_IN,
+ RD_EN_IN => '1',
+ RCNT_OUT => open,
+ EMPTY_OUT => down_data_empty,
+ FULL_OUT => down_data_full);
+
+ SYNC_DOWN : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ down_data_all_cntr_up <= '0';
+ else
+ down_data_all_cntr_up <= not down_data_empty;
+ end if;
+ end if;
+ end process SYNC_DOWN;
+
+ RESET_DATA_CNTR_DOWN : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or DOWN_DATA_VALID_IN = '0' then --(down_data_all_cntr = DOWN_R_REGISTERS_NUMBER + DOWN_SPECIAL_REGISTERS_NUMBER + DOWN_RW_REGISTERS_NUMBER) or then
+ reg_fifo_rst <= '1';
+ down_data_all_rst <= '1';
+ down_data_all_rst_a <= down_data_all_rst;
+ down_data_all_rst_b <= down_data_all_rst_a;
+ down_data_all_cntr_sync <= (others => '0');
+ else
+ reg_fifo_rst <= '0';
+ down_data_all_rst <= '0';
+ down_data_all_rst_a <= down_data_all_rst;
+ down_data_all_rst_b <= down_data_all_rst_a;
+ down_data_all_cntr_sync <= down_data_all_cntr;
+ end if;
+ end if;
+ end process RESET_DATA_CNTR_DOWN;
+
+ DATA_DOWN_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 13)
+ port map (
+ CLK => CLK,
+ RESET => down_data_all_rst_b,
+ COUNT_OUT => down_data_all_cntr,
+ UP_IN => down_data_all_cntr_up,
+ DOWN_IN => '0');
+
+ WRITE_REG_MEM_SYNC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ cts_fpga2_reg_mem_wr_en <= '0';
+ cts_fpga2_reg_mem_wr_en_sync <= '0';
+ cts_fpga2_reg_mem_addr <= (others => '0');
+
+ else
+ cts_fpga2_reg_mem_wr_en <= down_data_all_cntr_up;
+ cts_fpga2_reg_mem_wr_en_sync <= cts_fpga2_reg_mem_wr_en;
+ cts_fpga2_reg_mem_addr <= down_data_all_cntr(12 downto 0);
+ end if;
+ end if;
+ end process WRITE_REG_MEM_SYNC;
+
+ THE_CTS_FPGA2_REG_MEM: cts_fpga2_reg_mem
+ port map (
+ WrAddress => down_data_all_cntr_sync(12 downto 0),--cts_fpga2_reg_mem_addr,
+ RdAddress => saved_address(12 downto 0),
+ Data => down_data_out_i,
+ WE => cts_fpga2_reg_mem_wr_en,
+ RdClock => CLK,
+ RdClockEn => '1',
+ Reset => RESET,
+ WrClock => CLK,
+ WrClockEn => '1',
+ Q => reg_mem_data);
+
+ -----------------------------------------------------------------------------
+ -- rw registers from here (fpga 2 )to fpga 1
+ -----------------------------------------------------------------------------
+
+ RW_SLOW_DATA_SEND_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 1)
+ port map (
+ CLK => CLK,
+ RESET => RESET,--lvl1_slow_data_rst,
+ COUNT_OUT => slow_data_cntr,
+ UP_IN => '1',
+ DOWN_IN => '0');
+ RW_CLK_OUT <= slow_data_cntr(0);
+
+ THE_RW_REG_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => rw_reg_cntr_rst,
+ COUNT_OUT => rw_reg_cntr,
+ UP_IN => rw_reg_cntr_up,
+ DOWN_IN => '0');
+
+ SAVE_RW_REG : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ rw_reg_data <= (others => '0');
+ elsif ack_out_synch_b = '1' then
+ rw_reg_data <= saved_data &
+ x"0000" & saved_address;
+ end if;
+ end if;
+ end process SAVE_RW_REG;
+
+ RW_DATA_SEND_CLK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ RW_DATA_SEND_CURRENT <= IDLE;
+ rw_data_send_debug <= x"0";
+ rw_reg_integer_cntr <= 0;
+ rw_reg_cntr_rst <= '1';
+ rw_reg_cntr_up <= '0';
+ rw_data_out_i <= (others => '0');
+ rw_data_valid_out_i <= '0';
+ slow_data_cntr_sync(0) <= '0';
+ else
+ RW_DATA_SEND_CURRENT <= RW_DATA_SEND_NEXT;
+ rw_data_send_debug <= rw_data_send_debug_fsm;
+ rw_reg_integer_cntr <= conv_integer(rw_reg_cntr(5 downto 0));
+ rw_reg_cntr_rst <= rw_reg_cntr_rst_fsm;
+ rw_reg_cntr_up <= rw_reg_cntr_up_fsm;
+ rw_data_out_i <= rw_data_out_fsm;
+ rw_data_valid_out_i <= rw_data_valid_out_fsm;
+ slow_data_cntr_sync <= slow_data_cntr;
+ end if;
+ end if;
+ end process RW_DATA_SEND_CLK;
+
+ RW_DATA_OUT <= rw_data_out_i;
+ RW_DATA_VALID_OUT <= rw_data_valid_out_tmp;
+
+ RW_VALID_OUT_SYNC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ rw_data_valid_out_sync <= '0';
+ rw_data_valid_out_tmp <= '0';
+ else
+ rw_data_valid_out_sync <= rw_data_valid_out_i;
+ rw_data_valid_out_tmp <= rw_data_valid_out_i and rw_data_valid_out_sync;
+ end if;
+ end if;
+ end process RW_VALID_OUT_SYNC;
+
+
+ RW_DATA_SEND_PROC : process (CLK)
+ begin
+ rw_data_send_debug_fsm <= x"0";
+ rw_reg_cntr_rst_fsm <= '1';
+ rw_reg_cntr_up_fsm <= '0';
+ rw_data_out_fsm <= (others => '0');
+ rw_data_valid_out_fsm <= '0';
+
+ case (RW_DATA_SEND_CURRENT) is
+
+ when IDLE =>
+ rw_data_send_debug_fsm <= x"1";
+ if ack_out_synch_e = '1' and saved_address(15 downto 8) = x"A0" and saved_address(7 downto 0) < 240 and saved_address(7 downto 0) > 191 and saved_mode = '0' then
+ RW_DATA_SEND_NEXT <= RW_REG_PREPARE_A;
+ else
+ RW_DATA_SEND_NEXT <= IDLE;
+ end if;
+
+ when RW_REG_PREPARE_A =>
+ rw_data_send_debug_fsm <= x"2";
+ if slow_data_cntr(0) = '0' then
+ RW_DATA_SEND_NEXT <= RW_REG_SEND;
+ else
+ RW_DATA_SEND_NEXT <= RW_REG_PREPARE_A;
+ end if;
+
+ when RW_REG_SEND =>
+ rw_data_send_debug_fsm <= x"3";
+ rw_reg_cntr_up_fsm <= slow_data_cntr_sync(0);
+ rw_reg_cntr_rst_fsm <= '0';
+ rw_data_out_fsm <= rw_reg_data((UP_WIDTH*(rw_reg_integer_cntr+1))-1 downto UP_WIDTH*(rw_reg_integer_cntr));
+ if rw_reg_cntr = (2*(32/UP_WIDTH)) then
+ rw_data_valid_out_fsm <= '0';
+ RW_DATA_SEND_NEXT <= IDLE;
+ else
+ rw_data_valid_out_fsm <= '1';
+ RW_DATA_SEND_NEXT <= RW_REG_SEND;
+ end if;
+
+ when others =>
+ RW_DATA_SEND_NEXT <= IDLE;
+
+ end case;
+ end process RW_DATA_SEND_PROC;
+
+
+end cts_fpga2_reg_interface;
--- /dev/null
+[Device]
+Family=latticeecp2m
+PartType=LFE2M100E
+PartName=LFE2M100E-5F900C
+SpeedGrade=-5
+Package=FPBGA900
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=RAM_DP
+CoreRevision=6.1
+ModuleName=cts_fpga2_reg_mem
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=11/15/2010
+Time=16:50:28
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+RAddress=8192
+RData=32
+WAddress=8192
+WData=32
+enByte=0
+ByteSize=9
+adPipeline=0
+inPipeline=0
+outPipeline=1
+MOR=0
+InData=Registered
+AdControl=Registered
+MemFile=
+MemFormat=bin
+Reset=Sync
+GSR=Enabled
+Pad=0
+EnECC=0
+Optimization=Speed
+EnSleep=ENABLED
+Pipeline=0
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module Version: 6.1
+--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type bram -wp 10 -rp 0011 -rdata_width 32 -data_width 32 -num_rows 16384 -outdata REGISTERED -resetmode SYNC -cascade -1 -e
+
+-- Mon Jan 2 14:17:10 2012
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity cts_fpga2_reg_mem_a is
+ port (
+ WrAddress: in std_logic_vector(13 downto 0);
+ RdAddress: in std_logic_vector(13 downto 0);
+ Data: in std_logic_vector(31 downto 0);
+ WE: in std_logic;
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ WrClock: in std_logic;
+ WrClockEn: in std_logic;
+ Q: out std_logic_vector(31 downto 0));
+end cts_fpga2_reg_mem_a;
+
+architecture Structure of cts_fpga2_reg_mem_a is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute GSR : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_0_31 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_0_31 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_0_31 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_0_31 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_0_31 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_0_31 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_0_31 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_0_31 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_0_31 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_0_31 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_0_31 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_0_31 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_1_30 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_1_30 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_1_30 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_1_30 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_1_30 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_1_30 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_1_30 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_1_30 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_1_30 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_1_30 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_1_30 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_1_30 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_2_29 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_2_29 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_2_29 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_2_29 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_2_29 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_2_29 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_2_29 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_2_29 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_2_29 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_2_29 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_2_29 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_2_29 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_3_28 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_3_28 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_3_28 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_3_28 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_3_28 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_3_28 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_3_28 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_3_28 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_3_28 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_3_28 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_3_28 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_3_28 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_4_27 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_4_27 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_4_27 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_4_27 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_4_27 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_4_27 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_4_27 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_4_27 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_4_27 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_4_27 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_4_27 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_4_27 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_5_26 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_5_26 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_5_26 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_5_26 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_5_26 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_5_26 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_5_26 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_5_26 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_5_26 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_5_26 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_5_26 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_5_26 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_6_25 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_6_25 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_6_25 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_6_25 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_6_25 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_6_25 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_6_25 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_6_25 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_6_25 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_6_25 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_6_25 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_6_25 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_7_24 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_7_24 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_7_24 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_7_24 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_7_24 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_7_24 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_7_24 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_7_24 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_7_24 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_7_24 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_7_24 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_7_24 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_8_23 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_8_23 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_8_23 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_8_23 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_8_23 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_8_23 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_8_23 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_8_23 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_8_23 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_8_23 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_8_23 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_8_23 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_9_22 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_9_22 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_9_22 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_9_22 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_9_22 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_9_22 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_9_22 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_9_22 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_9_22 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_9_22 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_9_22 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_9_22 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_10_21 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_10_21 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_10_21 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_10_21 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_10_21 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_10_21 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_10_21 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_10_21 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_10_21 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_10_21 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_10_21 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_10_21 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_11_20 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_11_20 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_11_20 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_11_20 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_11_20 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_11_20 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_11_20 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_11_20 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_11_20 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_11_20 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_11_20 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_11_20 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_12_19 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_12_19 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_12_19 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_12_19 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_12_19 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_12_19 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_12_19 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_12_19 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_12_19 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_12_19 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_12_19 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_12_19 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_13_18 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_13_18 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_13_18 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_13_18 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_13_18 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_13_18 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_13_18 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_13_18 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_13_18 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_13_18 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_13_18 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_13_18 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_14_17 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_14_17 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_14_17 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_14_17 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_14_17 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_14_17 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_14_17 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_14_17 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_14_17 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_14_17 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_14_17 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_14_17 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_15_16 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_15_16 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_15_16 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_15_16 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_15_16 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_15_16 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_15_16 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_15_16 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_15_16 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_15_16 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_15_16 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_15_16 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_16_15 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_16_15 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_16_15 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_16_15 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_16_15 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_16_15 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_16_15 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_16_15 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_16_15 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_16_15 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_16_15 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_16_15 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_17_14 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_17_14 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_17_14 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_17_14 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_17_14 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_17_14 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_17_14 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_17_14 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_17_14 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_17_14 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_17_14 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_17_14 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_18_13 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_18_13 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_18_13 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_18_13 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_18_13 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_18_13 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_18_13 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_18_13 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_18_13 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_18_13 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_18_13 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_18_13 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_19_12 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_19_12 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_19_12 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_19_12 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_19_12 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_19_12 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_19_12 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_19_12 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_19_12 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_19_12 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_19_12 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_19_12 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_20_11 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_20_11 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_20_11 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_20_11 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_20_11 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_20_11 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_20_11 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_20_11 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_20_11 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_20_11 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_20_11 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_20_11 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_21_10 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_21_10 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_21_10 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_21_10 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_21_10 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_21_10 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_21_10 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_21_10 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_21_10 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_21_10 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_21_10 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_21_10 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_22_9 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_22_9 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_22_9 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_22_9 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_22_9 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_22_9 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_22_9 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_22_9 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_22_9 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_22_9 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_22_9 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_22_9 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_23_8 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_23_8 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_23_8 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_23_8 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_23_8 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_23_8 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_23_8 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_23_8 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_23_8 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_23_8 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_23_8 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_23_8 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_24_7 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_24_7 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_24_7 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_24_7 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_24_7 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_24_7 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_24_7 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_24_7 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_24_7 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_24_7 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_24_7 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_24_7 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_25_6 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_25_6 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_25_6 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_25_6 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_25_6 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_25_6 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_25_6 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_25_6 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_25_6 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_25_6 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_25_6 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_25_6 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_26_5 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_26_5 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_26_5 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_26_5 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_26_5 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_26_5 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_26_5 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_26_5 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_26_5 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_26_5 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_26_5 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_26_5 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_27_4 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_27_4 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_27_4 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_27_4 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_27_4 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_27_4 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_27_4 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_27_4 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_27_4 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_27_4 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_27_4 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_27_4 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_28_3 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_28_3 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_28_3 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_28_3 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_28_3 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_28_3 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_28_3 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_28_3 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_28_3 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_28_3 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_28_3 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_28_3 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_29_2 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_29_2 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_29_2 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_29_2 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_29_2 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_29_2 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_29_2 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_29_2 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_29_2 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_29_2 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_29_2 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_29_2 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_30_1 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_30_1 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_30_1 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_30_1 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_30_1 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_30_1 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_30_1 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_30_1 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_30_1 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_30_1 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_30_1 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_30_1 : label is "1";
+ attribute MEM_LPC_FILE of cts_fpga2_reg_mem_a_0_31_0 : label is "cts_fpga2_reg_mem_a.lpc";
+ attribute MEM_INIT_FILE of cts_fpga2_reg_mem_a_0_31_0 : label is "";
+ attribute CSDECODE_B of cts_fpga2_reg_mem_a_0_31_0 : label is "0b000";
+ attribute CSDECODE_A of cts_fpga2_reg_mem_a_0_31_0 : label is "0b000";
+ attribute WRITEMODE_B of cts_fpga2_reg_mem_a_0_31_0 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_fpga2_reg_mem_a_0_31_0 : label is "NORMAL";
+ attribute GSR of cts_fpga2_reg_mem_a_0_31_0 : label is "DISABLED";
+ attribute RESETMODE of cts_fpga2_reg_mem_a_0_31_0 : label is "SYNC";
+ attribute REGMODE_B of cts_fpga2_reg_mem_a_0_31_0 : label is "OUTREG";
+ attribute REGMODE_A of cts_fpga2_reg_mem_a_0_31_0 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_fpga2_reg_mem_a_0_31_0 : label is "1";
+ attribute DATA_WIDTH_A of cts_fpga2_reg_mem_a_0_31_0 : label is "1";
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ cts_fpga2_reg_mem_a_0_0_31: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>open, DOB2=>open,
+ DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_1_30: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(1),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(1), DOB1=>open, DOB2=>open,
+ DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_2_29: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(2),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(2), DOB1=>open, DOB2=>open,
+ DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_3_28: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(3),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(3), DOB1=>open, DOB2=>open,
+ DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_4_27: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(4),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(4), DOB1=>open, DOB2=>open,
+ DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_5_26: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(5),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(5), DOB1=>open, DOB2=>open,
+ DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_6_25: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(6),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(6), DOB1=>open, DOB2=>open,
+ DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_7_24: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(7),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(7), DOB1=>open, DOB2=>open,
+ DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_8_23: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(8),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(8), DOB1=>open, DOB2=>open,
+ DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_9_22: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(9),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(9), DOB1=>open, DOB2=>open,
+ DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
+ DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_10_21: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(10),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(10), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_11_20: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(11),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(11), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_12_19: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(12),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(12), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_13_18: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(13),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(13), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_14_17: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(14),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(14), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_15_16: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(15),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(15), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_16_15: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(16),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(16), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_17_14: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(17),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(17), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_18_13: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(18),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(18), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_19_12: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(19),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(19), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_20_11: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(20),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(20), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_21_10: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(21),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(21), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_22_9: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(22),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(22), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_23_8: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(23),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(23), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_24_7: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(24),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(24), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_25_6: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(25),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(25), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_26_5: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(26),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(26), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_27_4: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(27),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(27), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_28_3: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(28),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(28), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_29_2: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(29),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(29), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ cts_fpga2_reg_mem_a_0_30_1: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(30),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(30), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ cts_fpga2_reg_mem_a_0_31_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 1,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(31),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>WrAddress(0), ADA1=>WrAddress(1), ADA2=>WrAddress(2),
+ ADA3=>WrAddress(3), ADA4=>WrAddress(4), ADA5=>WrAddress(5),
+ ADA6=>WrAddress(6), ADA7=>WrAddress(7), ADA8=>WrAddress(8),
+ ADA9=>WrAddress(9), ADA10=>WrAddress(10),
+ ADA11=>WrAddress(11), ADA12=>WrAddress(12),
+ ADA13=>WrAddress(13), CEA=>WrClockEn, CLKA=>WrClock, WEA=>WE,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>RdAddress(0), ADB1=>RdAddress(1),
+ ADB2=>RdAddress(2), ADB3=>RdAddress(3), ADB4=>RdAddress(4),
+ ADB5=>RdAddress(5), ADB6=>RdAddress(6), ADB7=>RdAddress(7),
+ ADB8=>RdAddress(8), ADB9=>RdAddress(9), ADB10=>RdAddress(10),
+ ADB11=>RdAddress(11), ADB12=>RdAddress(12),
+ ADB13=>RdAddress(13), CEB=>RdClockEn, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open,
+ DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open,
+ DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
+ DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
+ DOA16=>open, DOA17=>open, DOB0=>Q(31), DOB1=>open,
+ DOB2=>open, DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open,
+ DOB7=>open, DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
+ DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
+ DOB16=>open, DOB17=>open);
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of cts_fpga2_reg_mem_a is
+ for Structure
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+
+
+
+entity cts_fpga2_to_fpga1 is
+
+ generic (
+ LVL1_SIZE_OF_DATA_BUS_IN : natural;
+ LVL2_SIZE_OF_DATA_BUS_IN : natural
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ FPGA1_CLK_IN : in std_logic;
+ --lvl1 from fpga1 to fpga2 to cts endpoint
+ LVL1_DATA_IN : in std_logic_vector(LVL1_SIZE_OF_DATA_BUS_IN-1 downto 0);
+ LVL1_DATA_VALID_IN : in std_logic;
+ LVL1_DATA_FINISHED_IN : in std_logic;
+ LVL1_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL1_RND_CODE_OUT : out std_logic_vector(7 downto 0);
+ LVL1_CODE_OUT : out std_logic_vector(3 downto 0);
+ LVL1_TRIGGER_OUT : out std_logic;
+ --lvl1 from fpga1 to fpga2 to data endpoint
+ LVL1_DATA_OUT : out std_logic_vector(31 downto 0);
+ LVL1_DATA_VALID_OUT : out std_logic;
+ LVL1_DATA_TRIGGER_IN : in std_logic;
+ LVL1_TRIGGER_RELEASE_OUT : out std_logic;
+ LVL1_DATA_FINISHED_OUT : out std_logic;
+ --lvl2
+ LVL2_DATA_IN : in std_logic_vector(LVL2_SIZE_OF_DATA_BUS_IN-1 downto 0);
+ LVL2_DATA_VALID_IN : in std_logic;
+ LVL2_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL2_RND_CODE_OUT : out std_logic_vector(7 downto 0);
+ LVL2_CODE_OUT : out std_logic_vector(3 downto 0);
+ LVL2_TRIGGER_OUT : out std_logic;
+ EB_IP_ID_OUT : out std_logic_vector(3 downto 0);
+ LVL1_INFO_OUT : out std_logic_vector(15 downto 0);
+ CTS_FPGA2_TO_FPGA1_STASUS_0UT_0 : out std_logic_vector(31 downto 0)
+ );
+end cts_fpga2_to_fpga1;
+
+
+
+
+architecture cts_fpga2_to_fpga1 of cts_fpga2_to_fpga1 is
+
+ component cts_fpga2_lvl1_lvl2_fifo
+ generic (
+ SIZE_OF_DATA_BUS_IN : natural;
+ FPGA_TYPE : natural);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ FPGA1_CLK_IN : in std_logic;
+ DATA_IN : in std_logic_vector(SIZE_OF_DATA_BUS_IN-1 downto 0);
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ WR_EN_IN : in std_logic;
+ RD_EN_IN : in std_logic;
+ RCNT_OUT : out std_logic_vector(9 downto 0);
+ EMPTY_OUT : out std_logic;
+ FULL_OUT : out std_logic);
+ end component;
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+ component cts_align_signals
+ generic (
+ DELAY : natural;
+ VECTOR_WIDTH : natural);
+ port (
+ CLK : in std_logic;
+ SIGNAL_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ SIGNAL_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0));
+ end component;
+
+ type LVL1 is (IDLE, LVL1_TAKE_INFO_A, LVL1_TAKE_INFO_B, LVL1_TAKE_INFO_C, LVL1_SEND_DATA_A, LVL1_SEND_DATA_B);
+ signal LVL1_CURRENT, LVL1_NEXT : LVL1;
+ signal lvl1_rcnt_out_i : std_logic_vector(9 downto 0);
+ signal lvl1_rd_en_in_i, lvl1_rd_en_in_fsm: std_logic;
+ signal lvl1_rd_en_in_pulse : std_logic_vector(3 downto 0);
+ signal lvl1_data_valid_out_fsm : std_logic;
+ signal lvl1_data_valid_out_i, lvl1_data_valid_out_align : std_logic_vector(0 downto 0);
+
+ signal lvl1_delay_in, lvl1_delay_out_align : std_logic_vector(1 downto 0);
+
+ signal lvl1_empty_out, lvl1_full_out : std_logic;
+ signal lvl1_trigger_out_fsm : std_logic;
+ signal lvl1_trigger_out_i, lvl1_trigger_out_delayed : std_logic_vector(0 downto 0);
+ type lvl1_info_array is array (0 to 2) of std_logic_vector(31 downto 0);
+ signal lvl1_info : lvl1_info_array;
+ signal lvl1_data_out_i, lvl1_data_out_sync : std_logic_vector(31 downto 0);
+ signal saved_lvl1_data_finished, saved_lvl1_data_trigger : std_logic;
+ signal lvl1_data_valid_in_i,lvl1_data_finished_in_i : std_logic;
+ signal lvl1_data_finished_out_fsm, lvl1_data_finished_out_i, lvl1_trigger_release_out_i, lvl1_trigger_release_out_fsm : std_logic;
+
+ type LVL2 is (IDLE, LVL2_TAKE_INFO_A, LVL2_TAKE_INFO_B, LVL2_TAKE_INFO_C);
+ signal LVL2_CURRENT, LVL2_NEXT : LVL2;
+ signal lvl2_rcnt_out_i : std_logic_vector(9 downto 0);
+ signal lvl2_rd_en_in_i, lvl2_rd_en_in_fsm : std_logic;
+ signal lvl2_rd_en_in_pulse : std_logic_vector(3 downto 0);
+ signal lvl2_data_valid_out_i, lvl2_data_valid_out_fsm : std_logic;
+ signal lvl2_empty_out, lvl2_full_out : std_logic;
+ signal lvl2_trigger_out_fsm : std_logic;
+ signal lvl2_trigger_out_i, lvl2_trigger_out_delayed : std_logic_vector(0 downto 0);
+ type lvl2_info_array is array (0 to 2) of std_logic_vector(31 downto 0);
+ signal lvl2_info : lvl2_info_array;
+ signal lvl2_data_out_i, lvl2_data_out_sync : std_logic_vector(31 downto 0);
+
+begin
+
+
+-------------------------------------------------------------------------------
+-- lvl1
+-------------------------------------------------------------------------------
+ lvl1_data_valid_in_i <= LVL1_DATA_VALID_IN;
+
+ THE_CTS_FPGA2_LVL1_FIFO: cts_fpga2_lvl1_lvl2_fifo
+ generic map (
+ SIZE_OF_DATA_BUS_IN => LVL1_SIZE_OF_DATA_BUS_IN,
+ FPGA_TYPE => 1)
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ FPGA1_CLK_IN => FPGA1_CLK_IN,
+ DATA_IN => LVL1_DATA_IN,
+ DATA_OUT => lvl1_data_out_i,
+ WR_EN_IN => lvl1_data_valid_in_i,
+ RD_EN_IN => lvl1_rd_en_in_i,
+ RCNT_OUT => lvl1_rcnt_out_i,
+ EMPTY_OUT => lvl1_empty_out,
+ FULL_OUT => lvl1_full_out);
+ LVL1_DATA_OUT <= lvl1_data_out_i;
+
+ LVL1_ALIGN_SIGNALS : cts_align_signals
+ generic map (
+ DELAY => 4,
+ VECTOR_WIDTH => 1)
+ port map (
+ CLK => CLK,
+ SIGNAL_VECTOR_IN => lvl1_trigger_out_i,
+ SIGNAL_VECTOR_OUT => lvl1_trigger_out_delayed);
+
+ LVL1_DATA_VALID_ALIGN : cts_align_signals
+ generic map (
+ DELAY => 2,
+ VECTOR_WIDTH => 2)
+ port map (
+ CLK => CLK,
+ SIGNAL_VECTOR_IN => lvl1_delay_in,
+ SIGNAL_VECTOR_OUT => lvl1_delay_out_align);
+
+
+ LVL1_TRIGGER_OUT <= lvl1_trigger_out_delayed(0);
+ LVL1_DATA_VALID_OUT <= lvl1_delay_out_align(0);
+ LVL1_TRIGGER_RELEASE_OUT <= lvl1_trigger_release_out_i;
+ LVL1_DATA_FINISHED_OUT <= lvl1_delay_out_align(1);
+
+ LVL1_CLK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL1_CURRENT <= IDLE;
+ lvl1_rd_en_in_i <= '0';
+ lvl1_delay_in <= (others => '0');
+ lvl1_trigger_out_i(0) <= '0';
+ lvl1_trigger_release_out_i <= '0';
+ lvl1_data_finished_out_i <= '0';
+ else
+ LVL1_CURRENT <= LVL1_NEXT;
+ lvl1_rd_en_in_i <= lvl1_rd_en_in_fsm;
+ lvl1_delay_in(0) <= lvl1_data_valid_out_fsm;
+ lvl1_trigger_out_i(0) <= lvl1_trigger_out_fsm;
+ lvl1_trigger_release_out_i <= lvl1_trigger_release_out_fsm;
+ lvl1_delay_in(1) <= lvl1_data_finished_out_fsm;
+ end if;
+ end if;
+ end process LVL1_CLK;
+
+ LVL1_PROC : process (CLK)
+ begin
+ lvl1_rd_en_in_fsm <= '0';
+ lvl1_data_valid_out_fsm <= '0';
+ lvl1_trigger_out_fsm <= '0';
+ lvl1_trigger_release_out_fsm <= '0';
+ lvl1_data_finished_out_fsm <= '0';
+
+ case (LVL1_CURRENT) is
+
+ when IDLE =>
+ if lvl1_rcnt_out_i = 4 then
+ LVL1_NEXT <= LVL1_TAKE_INFO_A;
+ else
+ LVL1_NEXT <= IDLE;
+ end if;
+
+ when LVL1_TAKE_INFO_A =>
+ lvl1_rd_en_in_fsm <= '1';
+ LVL1_NEXT <= LVL1_TAKE_INFO_B;
+
+ when LVL1_TAKE_INFO_B =>
+ lvl1_rd_en_in_fsm <= '1';
+ LVL1_NEXT <= LVL1_TAKE_INFO_C;
+
+ when LVL1_TAKE_INFO_C =>
+ lvl1_trigger_out_fsm <= '1';
+ lvl1_rd_en_in_fsm <= '1';
+ LVL1_NEXT <= LVL1_SEND_DATA_A;
+
+ when LVL1_SEND_DATA_A =>
+ if saved_lvl1_data_finished = '1' and saved_lvl1_data_trigger ='1' then
+ lvl1_trigger_release_out_fsm <= '1';
+ LVL1_NEXT <= LVL1_SEND_DATA_B;
+ else
+ LVL1_NEXT <= LVL1_SEND_DATA_A;
+ end if;
+
+ when LVL1_SEND_DATA_B =>
+ if lvl1_rcnt_out_i = 2 then
+ lvl1_data_finished_out_fsm <= '1';
+ LVL1_NEXT <= IDLE;
+ else
+ lvl1_rd_en_in_fsm <= '1';
+ lvl1_data_valid_out_fsm <= '1';
+ LVL1_NEXT <= LVL1_SEND_DATA_B;
+ end if;
+
+ when others =>
+ LVL1_NEXT <= IDLE;
+
+ end case;
+ end process LVL1_PROC;
+
+
+
+ SAVE_LVL1_DATA_TRIGGER_IN : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or LVL1_CURRENT = LVL1_SEND_DATA_B then
+ saved_lvl1_data_trigger <= '0';
+ elsif LVL1_DATA_TRIGGER_IN = '1' then
+ saved_lvl1_data_trigger <= '1';
+ end if;
+ end if;
+ end process SAVE_LVL1_DATA_TRIGGER_IN;
+
+ lvl1_data_finished_in_i <= LVL1_DATA_FINISHED_IN;
+ SAVE_LVL1_DATA_FINISHED : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or LVL1_CURRENT = LVL1_SEND_DATA_B then
+ saved_lvl1_data_finished <= '0';
+ elsif lvl1_data_finished_in_i = '1' then
+ saved_lvl1_data_finished <= '1';
+ end if;
+ end if;
+ end process SAVE_LVL1_DATA_FINISHED;
+
+
+ LVL1_TRIGGER_INFO_PULSE: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl1_rd_en_in_i,
+ pulse => lvl1_rd_en_in_pulse(0));
+
+ LVL1_PULSES_FOR_SAVING_INFO : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_rd_en_in_pulse(1) <= '0';
+ lvl1_rd_en_in_pulse(2) <= '0';
+ lvl1_data_out_sync <= (others => '0');
+ else
+ lvl1_rd_en_in_pulse(1) <= lvl1_rd_en_in_pulse(0);
+ lvl1_rd_en_in_pulse(2) <= lvl1_rd_en_in_pulse(1);
+ lvl1_data_out_sync <= lvl1_data_out_i;
+ end if;
+ end if;
+ end process LVL1_PULSES_FOR_SAVING_INFO;
+
+ THE_LVL1_SAVE_INFO: for i in 0 to 2 generate
+ LVL1_SAVE_INFO : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_info(i) <= (others => '0');
+ elsif lvl1_rd_en_in_pulse(i) = '1' then
+ lvl1_info(i) <= lvl1_data_out_sync;
+ end if;
+ end if;
+ end process LVL1_SAVE_INFO;
+ end generate THE_LVL1_SAVE_INFO;
+
+ LVL1_INFO_OUT <= lvl1_info(2)(23 downto 8);
+ LVL1_RND_CODE_OUT <= lvl1_info(2)(7 downto 0);
+ LVL1_CODE_OUT <= lvl1_info(1)(3 downto 0);
+ LVL1_TRIGGER_TAG_OUT <= lvl1_info(0)(15 downto 0);
+
+-------------------------------------------------------------------------------
+-- lvl2
+-------------------------------------------------------------------------------
+ THE_CTS_FPGA2_LVL2_FIFO: cts_fpga2_lvl1_lvl2_fifo
+ generic map (
+ SIZE_OF_DATA_BUS_IN => LVL2_SIZE_OF_DATA_BUS_IN,
+ FPGA_TYPE => 1)
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ FPGA1_CLK_IN => FPGA1_CLK_IN,
+ DATA_IN => LVL2_DATA_IN,
+ DATA_OUT => lvl2_data_out_i,
+ WR_EN_IN => LVL2_DATA_VALID_IN,
+ RD_EN_IN => lvl2_rd_en_in_i,
+ RCNT_OUT => lvl2_rcnt_out_i,
+ EMPTY_OUT => lvl2_empty_out,
+ FULL_OUT => lvl2_full_out);
+
+ LVL2_ALIGN_SIGNALS : cts_align_signals
+ generic map (
+ DELAY => 4,
+ VECTOR_WIDTH => 1)
+ port map (
+ CLK => CLK,
+ SIGNAL_VECTOR_IN => lvl2_trigger_out_i,
+ SIGNAL_VECTOR_OUT => lvl2_trigger_out_delayed);
+
+ LVL2_TRIGGER_OUT <= lvl2_trigger_out_delayed(0);
+
+ LVL2_CLK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL2_CURRENT <= IDLE;
+ lvl2_rd_en_in_i <= '0';
+ lvl2_data_valid_out_i <= '0';
+ lvl2_trigger_out_i(0) <= '0';
+ else
+ LVL2_CURRENT <= LVL2_NEXT;
+ lvl2_rd_en_in_i <= lvl2_rd_en_in_fsm;
+ lvl2_data_valid_out_i <= lvl2_data_valid_out_fsm;
+ lvl2_trigger_out_i(0) <= lvl2_trigger_out_fsm;
+ end if;
+ end if;
+ end process LVL2_CLK;
+
+ LVL2_PROC : process (CLK)
+ begin
+ lvl2_rd_en_in_fsm <= '0';
+ lvl2_data_valid_out_fsm <= '0';
+ lvl2_trigger_out_fsm <= '0';
+
+ case (LVL2_CURRENT) is
+
+ when IDLE =>
+ if lvl2_rcnt_out_i = 3 then
+ LVL2_NEXT <= LVL2_TAKE_INFO_A;
+ else
+ LVL2_NEXT <= IDLE;
+ end if;
+
+ when LVL2_TAKE_INFO_A =>
+ lvl2_rd_en_in_fsm <= '1';
+ LVL2_NEXT <= LVL2_TAKE_INFO_B;
+
+ when LVL2_TAKE_INFO_B =>
+ lvl2_rd_en_in_fsm <= '1';
+ LVL2_NEXT <= LVL2_TAKE_INFO_C;
+
+ when LVL2_TAKE_INFO_C =>
+ lvl2_trigger_out_fsm <= '1';
+ lvl2_rd_en_in_fsm <= '1';
+ LVL2_NEXT <= IDLE;
+
+ when others =>
+ LVL2_NEXT <= IDLE;
+
+ end case;
+ end process LVL2_PROC;
+
+ LVL2_TRIGGER_INFO_PULSE: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl2_rd_en_in_i,
+ pulse => lvl2_rd_en_in_pulse(0));
+
+ LVL2_PULSES_FOR_SAVING_INFO : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_rd_en_in_pulse(1) <= '0';
+ lvl2_rd_en_in_pulse(2) <= '0';
+ lvl2_data_out_sync <= (others => '0');
+ else
+ lvl2_rd_en_in_pulse(1) <= lvl2_rd_en_in_pulse(0);
+ lvl2_rd_en_in_pulse(2) <= lvl2_rd_en_in_pulse(1);
+ lvl2_data_out_sync <= lvl2_data_out_i;
+
+ end if;
+ end if;
+ end process LVL2_PULSES_FOR_SAVING_INFO;
+
+ THE_LVL2_SAVE_INFO: for i in 0 to 2 generate
+ LVL2_SAVE_INFO : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl2_info(i) <= (others => '0');
+ elsif lvl2_rd_en_in_pulse(i) = '1' then
+ lvl2_info(i) <= lvl2_data_out_sync;
+ end if;
+ end if;
+ end process LVL2_SAVE_INFO;
+ end generate THE_LVL2_SAVE_INFO;
+
+ LVL2_RND_CODE_OUT <= lvl2_info(2)(7 downto 0);
+ LVL2_CODE_OUT <= lvl2_info(1)(3 downto 0);
+ LVL2_TRIGGER_TAG_OUT <= lvl2_info(0)(15 downto 0);
+ EB_IP_ID_OUT <= lvl2_info(0)(19 downto 16);
+end cts_fpga2_to_fpga1;
--- /dev/null
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
+<ispXCF version="17.0 Linux Beta">
+ <Comment></Comment>
+ <Chain>
+ <Comm>JTAG</Comm>
+ <Device>
+ <Pos>1</Pos>
+ <Vendor>NA</Vendor>
+ <Family>Generic JTAG Device</Family>
+ <Name>JTAG-NOP</Name>
+ <Package>All</Package>
+ <PON>JTAG-NOP</PON>
+ <Bypass>
+ <InstrLen>10</InstrLen>
+ <InstrVal>1111111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>2</Pos>
+ <Ref>cts_fpga1</Ref>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeSCM</Family>
+ <Name>LFSCM3GA40E</Name>
+ <IDCode>0x0a81a157</IDCode>
+ <Package>All</Package>
+ <PON>LFSCM3GA40EP1</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1447</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>3</Pos>
+ <Ref>cts_fpga2</Ref>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP2M</Family>
+ <Name>LFE2M100E</Name>
+ <IDCode>0x0127d043</IDCode>
+ <Package>900-ball fpBGA</Package>
+ <PON>LFE2M100E-XXF900</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/home/marek/ctsaddon/workdir/cts_fpga2.bit</File>
+ <MaskFile>/home/marek/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk</MaskFile>
+ <FileTime>8/13/2010 0:0:41</FileTime>
+ <Operation>Fast Program</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1311</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>4</Pos>
+ <Ref>power</Ref>
+ <Vendor>NA</Vendor>
+ <Family>Generic JTAG Device</Family>
+ <Name>JTAG-NOP</Name>
+ <Package>All</Package>
+ <PON>JTAG-NOP</PON>
+ <Bypass>
+ <InstrLen>4</InstrLen>
+ <InstrVal>1111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ </Option>
+ </Device>
+ </Chain>
+ <ProjectOptions>
+ <Program>SEQUENTIAL</Program>
+ <Process>ENTIRED CHAIN</Process>
+ <OperationOverride>No Override</OperationOverride>
+ <StartTAP>TLR</StartTAP>
+ <EndTAP>TLR</EndTAP>
+ <DeGlitch value="TRUE"/>
+ <VerifyUsercode value="TRUE"/>
+ <PinSetting>
+ TMS LOW;
+ TCK LOW;
+ TDI LOW;
+ TDO LOW;
+ CableEN HIGH;
+ </PinSetting>
+ </ProjectOptions>
+</ispXCF>
--- /dev/null
+<?xml version='1.0' encoding='utf-8' ?>
+<!DOCTYPE ispXCF SYSTEM "IspXCF.dtd" >
+<ispXCF version="17.0 Linux Beta">
+ <Comment></Comment>
+ <Chain>
+ <Comm>JTAG</Comm>
+ <Device>
+ <Pos>1</Pos>
+ <Ref>cts_fpga1</Ref>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeSCM</Family>
+ <Name>LFSCM3GA40E</Name>
+ <IDCode>0x0a81a157</IDCode>
+ <Package>All</Package>
+ <PON>LFSCM3GA40EP1</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1447</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>2</Pos>
+ <Ref>cts_fpga2</Ref>
+ <Vendor>Lattice</Vendor>
+ <Family>LatticeECP2M</Family>
+ <Name>LFE2M100E</Name>
+ <IDCode>0x0127d043</IDCode>
+ <Package>900-ball fpBGA</Package>
+ <PON>LFE2M100E-XXF900</PON>
+ <Bypass>
+ <InstrLen>8</InstrLen>
+ <InstrVal>11111111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <File>/home/marek/ctsaddon/workdir/cts_fpga2.bit</File>
+ <MaskFile>/home/marek/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk</MaskFile>
+ <FileTime>8/13/2010 0:0:41</FileTime>
+ <Operation>Fast Program</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <PreloadLength>1311</PreloadLength>
+ <IOVectorData>0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF</IOVectorData>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ <Usercode>0x00000000</Usercode>
+ <AccessMode>JTAG</AccessMode>
+ </Option>
+ </Device>
+ <Device>
+ <Pos>3</Pos>
+ <Ref>power</Ref>
+ <Vendor>NA</Vendor>
+ <Family>Generic JTAG Device</Family>
+ <Name>JTAG-NOP</Name>
+ <Package>All</Package>
+ <PON>JTAG-NOP</PON>
+ <Bypass>
+ <InstrLen>4</InstrLen>
+ <InstrVal>1111</InstrVal>
+ <BScanLen>1</BScanLen>
+ <BScanVal>0</BScanVal>
+ </Bypass>
+ <Operation>Bypass</Operation>
+ <Option>
+ <SVFVendor>JTAG STANDARD</SVFVendor>
+ <IOState>HighZ</IOState>
+ <OverideUES value="TRUE"/>
+ <TCKFrequency>1.000000 MHz</TCKFrequency>
+ <SVFProcessor>SVF Processor</SVFProcessor>
+ </Option>
+ </Device>
+ </Chain>
+ <ProjectOptions>
+ <Program>SEQUENTIAL</Program>
+ <Process>ENTIRED CHAIN</Process>
+ <OperationOverride>No Override</OperationOverride>
+ <StartTAP>TLR</StartTAP>
+ <EndTAP>TLR</EndTAP>
+ <DeGlitch value="TRUE"/>
+ <VerifyUsercode value="TRUE"/>
+ <PinSetting>
+ TMS LOW;
+ TCK LOW;
+ TDI LOW;
+ TDO LOW;
+ CableEN HIGH;
+ </PinSetting>
+ </ProjectOptions>
+</ispXCF>
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+
+entity cts_fpga2_trig_gen is
+
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ TRIGGER_IN : in std_logic;
+ TRIGGER_TYPE_IN : in std_logic;
+ TRIGGER_OUT : out std_logic
+ );
+end cts_fpga2_trig_gen;
+
+architecture cts_fpga2_trig_gen of cts_fpga2_trig_gen is
+ signal trigger_length_cntr : std_logic_vector(3 downto 0);
+begin
+
+ TIMER_FOR_TRIGGER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ trigger_length_cntr <= (others => '1');
+ TRIGGER_OUT <= '0';
+ elsif TRIGGER_IN = '1' and TRIGGER_TYPE_IN = '0' then
+ trigger_length_cntr <= (others => '0');
+ TRIGGER_OUT <= '1';
+ elsif trigger_length_cntr < x"a" then
+ trigger_length_cntr <= trigger_length_cntr + 1;
+ TRIGGER_OUT <= '1';
+ else
+ trigger_length_cntr <= trigger_length_cntr;
+ TRIGGER_OUT <= '0';
+ end if;
+ end if;
+ end process TIMER_FOR_TRIGGER;
+
+end cts_fpga2_trig_gen;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use work.version.all;
+use ieee.std_logic_arith.all;
+
+entity cts_one_clock is
+ generic (
+ VECTOR_WIDTH : natural := 8
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ ONE_CLOCK_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ ONE_CLOCK_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ ENABLE_IN : in std_logic
+ );
+end cts_one_clock;
+
+architecture cts_one_clock of cts_one_clock is
+ signal signal_out : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ signal there_was_clock : std_logic;
+ signal one_clock_vector_in_i : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+begin
+
+ SAVE_OLD_PULSE : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ there_was_clock <= ONE_CLOCK_VECTOR_IN(VECTOR_WIDTH - 1);
+ end if;
+ end process SAVE_OLD_PULSE;
+
+ one_clock_vector_in_i <= ONE_CLOCK_VECTOR_IN;
+
+ GENERATE_ONE_CLOCK: for i in 0 to VECTOR_WIDTH - 1 generate
+
+ FIRST: if i=0 generate
+ ONE_CLK_PROC_FIRST : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if one_clock_vector_in_i(i) = '1' and there_was_clock = '0' and ENABLE_IN = '1' then
+ signal_out(i) <= '1';
+ else
+ signal_out(i) <= '0';
+ end if;
+ end if;
+ end process ONE_CLK_PROC_FIRST;
+ end generate FIRST;
+
+ REST: if i>0 generate
+ ONE_CLK_PROC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if one_clock_vector_in_i(i) = '1' and one_clock_vector_in_i(i-1) = '0' and ENABLE_IN = '1' then
+ signal_out(i) <= '1';
+ else
+ signal_out(i) <= '0';
+ end if;
+ end if;
+ end process ONE_CLK_PROC;
+ end generate REST;
+
+ end generate GENERATE_ONE_CLOCK;
+
+ ONE_CLOCK_VECTOR_OUT <= signal_out;
+end cts_one_clock;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use work.version.all;
+use ieee.std_logic_arith.all;
+
+entity cts_polarity_check is
+
+ generic (
+ NUMBER_OF_SIGNALS : natural
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ SIGNAL_IN : in std_logic_vector(NUMBER_OF_SIGNALS - 1 downto 0);
+ SIGNAL_OUT : out std_logic_vector(NUMBER_OF_SIGNALS - 1 downto 0)
+ );
+end cts_polarity_check;
+
+architecture cts_polarity_check of cts_polarity_check is
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ signal main_polarity_cntr : std_logic_vector(11 downto 0);
+ type individual_polarity_cntr_array is array (0 to NUMBER_OF_SIGNALS) of std_logic_vector(11 downto 0);
+ signal individual_polarity_cntr : individual_polarity_cntr_array;
+ signal polarity_cntr_rst : std_logic;
+ signal polarity_warning : std_logic_vector(NUMBER_OF_SIGNALS - 1 downto 0);
+
+begin
+
+ MAIN_TIME_COUNT_FOR_POLARITY: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 12)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ COUNT_OUT => main_polarity_cntr,
+ UP_IN => '1',
+ DOWN_IN => '0');
+ MAKE_POLARITY_CNTR_RESET : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ polarity_cntr_rst <= '1';
+ elsif main_polarity_cntr = x"000" then
+ polarity_cntr_rst <= '1';
+ else
+ polarity_cntr_rst <= '0';
+ end if;
+ end if;
+ end process MAKE_POLARITY_CNTR_RESET;
+
+ CHECK_POLARITY: for i in 0 to NUMBER_OF_SIGNALS - 1 generate
+ INDIVIDUAL_POL_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 12)
+ port map (
+ CLK => CLK,
+ RESET => polarity_cntr_rst,
+ COUNT_OUT => individual_polarity_cntr(i),
+ UP_IN => SIGNAL_IN(i),
+ DOWN_IN => '0');
+
+ SET_POLARITY : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ polarity_warning(i) <= '0';
+ elsif individual_polarity_cntr(i)(11) = '1' and main_polarity_cntr = x"fff" then
+ polarity_warning(i) <= '1';
+ elsif individual_polarity_cntr(i)(11) = '0' and main_polarity_cntr = x"fff" then
+ polarity_warning(i) <= '0';
+ end if;
+ end if;
+ end process SET_POLARITY;
+ end generate CHECK_POLARITY;
+
+ SIGNAL_OUT <= polarity_warning;
+
+end cts_polarity_check;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.all;
+
+entity cts_readout is
+ generic (
+ CTS_TYPE : natural);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ --trigg box
+ DATA_READY_IN : in std_logic;
+ DATA_IN : in std_logic_vector (31 downto 0); --from trigg box
+ SEND_DATA_TOKEN_OUT : out std_logic; --start trigg box readout
+ RECEIVED_DATA_TOKEN_IN : in std_logic; --end trigg box readout
+ --lvl1
+ LVL1_BUSY_OUT : out std_logic;
+ LVL1_TRBNET_TRIGGER_IN : in std_logic;
+ LVL1_TAG_IN : in std_logic_vector(15 downto 0);
+ LVL1_CODE_IN : in std_logic_vector(3 downto 0);
+ LVL1_FINISHED_OUT : out std_logic;
+ --lvl2
+ LVL2_TRIGGER_IN : in std_logic; --_vector(1 downto 0);
+ LVL2_FINISHED_OUT : out std_logic;
+ LVL2_BUSY_OUT : out std_logic;
+ --ipu
+ IPU_READY_IN : in std_logic;
+ IPU_DATAREADY_OUT : out std_logic;
+ IPU_DATA_OUT : out std_logic_vector(31 downto 0);
+ --stat
+ DEBUG_REGISTER_00 : out std_logic_vector(31 downto 0);
+ DEBUG_REGISTER_01 : out std_logic_vector(31 downto 0);
+ DEBUG_REGISTER_02 : out std_logic_vector(31 downto 0);
+ --ctrl
+ DATA_VERSION : in std_logic_vector(7 downto 0)
+ );
+end cts_readout;
+
+architecture cts_readout of cts_readout is
+
+ component cts_readout_data_buff
+ port (
+ Data : in std_logic_vector(33 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(33 downto 0);
+ WCNT : out std_logic_vector(9 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+ end component;
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+
+ --lvl1
+ type LVL1_FSM is (IDLE, SEND_AND_WAIT_FOR_TOKEN, SAVE_DATA_MARKER, SAVE_HEADER_1, SAVE_HEADER_2, SAVE_TRBNET_HEADER_1, SAVE_HEADER_MARKER, WAIT_FOR_EMPTYING_BUFFERS);
+ signal LVL1_FSM_CURRENT, LVL1_FSM_NEXT : LVL1_FSM;
+
+ type LVL2_FSM is (IDLE, WAIT_FOR_BUSY_END, READOUT_HEADER_MARKER_1, READOUT_HEADER_MARKER_2, READOUT_HEADER_MARKER_3, SEND_HEADERS_AND_DATA, READOUT_DATA_MARKER_1, READOUT_DATA_MARKER_2, READOUT_DATA_MARKER_3, SEND_DATA);
+ signal LVL2_FSM_CURRENT, LVL2_FSM_NEXT : LVL2_FSM;
+ --data buffer
+ signal data_din, data_din_fsm, data_dout : std_logic_vector(33 downto 0);
+ signal data_wr_en, data_wr_en_fsm, data_rd_en, data_rd_en_fsm, data_empty, data_full : std_logic;
+ signal data_wcnt : std_logic_vector(9 downto 0);
+ --header buffer
+ signal hd_din, hd_din_fsm, hd_dout : std_logic_vector(33 downto 0);
+ signal hd_wr_en, hd_wr_en_fsm, hd_rd_en, hd_rd_en_fsm, hd_empty, hd_full : std_logic;
+ signal hd_wcnt : std_logic_vector(9 downto 0);
+ --lvl1 FSM
+ signal lvl1_busy_i, lvl1_busy_fsm, lvl1_data_token_i, lvl1_data_token_fsm, lvl1_memory_busy_i : std_logic;
+ signal lvl1_debug, lvl1_debug_fsm : std_logic_vector(3 downto 0);
+ signal words_in_event : std_logic_vector(15 downto 0);
+ --lvl2FSM
+ signal lvl2_busy_i, lvl2_busy_fsm : std_logic;
+ signal lvl2_debug, lvl2_debug_fsm : std_logic_vector(3 downto 0);
+ signal ipu_dataready_out_fsm : std_logic;
+ signal ipu_data_out_fsm : std_logic_vector(31 downto 0);
+ --debug
+ signal test_counter_0, test_counter_2 : std_logic_vector(15 downto 0);
+ signal test_counter_1, test_counter_3 : std_logic_vector(7 downto 0);
+ signal lvl1_busy_end_pulse, not_lvl1_busy, not_lvl2_busy, lvl2_busy_start_pulse, lvl2_busy_end_pulse : std_logic;
+begin
+
+ REG_SYNC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ DEBUG_REGISTER_00 <= (others => '0');
+ DEBUG_REGISTER_01 <= (others => '0');
+ DEBUG_REGISTER_02 <= (others => '0');
+ else
+ DEBUG_REGISTER_00(15 downto 0) <= words_in_event;
+ DEBUG_REGISTER_00(19 downto 16) <= data_empty & data_full & hd_empty & hd_full;
+ DEBUG_REGISTER_00(23 downto 20) <= '0' & lvl1_busy_i & lvl1_memory_busy_i & lvl2_busy_i;
+ DEBUG_REGISTER_00(27 downto 24) <= lvl1_debug;
+ DEBUG_REGISTER_00(31 downto 28) <= lvl2_debug;
+ DEBUG_REGISTER_01(9 downto 0) <= data_wcnt(9 downto 0);
+ DEBUG_REGISTER_01(25 downto 16) <= hd_wcnt(9 downto 0);
+ DEBUG_REGISTER_02 <= test_counter_3(7 downto 0) & test_counter_2(7 downto 0) & test_counter_1(7 downto 0) & test_counter_0(7 downto 0);
+ end if;
+ end if;
+ end process REG_SYNC;
+
+
+ COUNT_WORDS_IN_EVENT : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or LVL1_TRBNET_TRIGGER_IN = '1' then
+ words_in_event <= x"0002";
+ elsif DATA_READY_IN = '1' then
+ words_in_event <= words_in_event + 1;
+ end if;
+ end if;
+ end process COUNT_WORDS_IN_EVENT;
+
+ DATA_FIFO: cts_readout_data_buff
+ port map (
+ Data => data_din,
+ Clock => CLK,
+ WrEn => data_wr_en,
+ RdEn => data_rd_en,
+ Reset => RESET,
+ Q => data_dout,
+ WCNT => data_wcnt,
+ Empty => data_empty,
+ Full => data_full);
+
+ HEADER_FIFO: cts_readout_data_buff
+ port map (
+ Data => hd_din,
+ Clock => CLK,
+ WrEn => hd_wr_en,
+ RdEn => hd_rd_en,
+ Reset => RESET,
+ Q => hd_dout,
+ WCNT => hd_wcnt,
+ Empty => hd_empty,
+ Full => hd_full);
+
+ LVL1_BUSY_OUT <= lvl1_busy_i;
+ SEND_DATA_TOKEN_OUT <= lvl1_data_token_i;
+
+ LVL1_FSM_CLOCK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL1_FSM_CURRENT <= IDLE;
+ lvl1_busy_i <= '0';
+ lvl1_debug <= x"1";
+ lvl1_data_token_i <= '0';
+ data_wr_en <= '0';
+ data_din <= "00" & x"00000000";
+ hd_wr_en <= '0';
+ hd_din <= "00" & x"00000000";
+
+ else
+ LVL1_FSM_CURRENT <= LVL1_FSM_NEXT;
+ lvl1_busy_i <= lvl1_busy_fsm;
+ lvl1_debug <= lvl1_debug_fsm;
+ lvl1_data_token_i <= lvl1_data_token_fsm;
+ data_wr_en <= data_wr_en_fsm;
+ data_din <= data_din_fsm;
+ hd_wr_en <= hd_wr_en_fsm;
+ hd_din <= hd_din_fsm;
+
+ end if;
+ end if;
+ end process LVL1_FSM_CLOCK;
+
+ LVL1_FSM_PROC : process (CLK)
+ begin
+ lvl1_debug_fsm <= x"1";
+ lvl1_busy_fsm <= '1';
+ lvl1_data_token_fsm <= '0';
+ data_wr_en_fsm <= '0';
+ data_din_fsm <= "00" & x"00000000";
+ hd_wr_en_fsm <= '0';
+ hd_din_fsm <= "00" & x"00000000";
+
+ case (LVL1_FSM_CURRENT) is
+
+ when IDLE =>
+ lvl1_debug_fsm <= x"1";
+ lvl1_busy_fsm <= '0';
+ if LVL1_TRBNET_TRIGGER_IN = '1' then
+ LVL1_FSM_NEXT <= SEND_AND_WAIT_FOR_TOKEN;
+ else
+ LVL1_FSM_NEXT <= IDLE;
+ end if;
+
+ when SEND_AND_WAIT_FOR_TOKEN =>
+ lvl1_debug_fsm <= x"1";
+ lvl1_data_token_fsm <= '1';
+ data_wr_en_fsm <= DATA_READY_IN;
+ data_din_fsm <= "01" & DATA_IN;
+ if RECEIVED_DATA_TOKEN_IN = '1' then
+ LVL1_FSM_NEXT <= SAVE_DATA_MARKER;
+ else
+ LVL1_FSM_NEXT <= SEND_AND_WAIT_FOR_TOKEN;
+ end if;
+
+ when SAVE_DATA_MARKER =>
+ lvl1_debug_fsm <= x"2";
+ data_wr_en_fsm <= '1';
+ data_din_fsm <= (others => '0');
+ LVL1_FSM_NEXT <= SAVE_HEADER_1;
+
+ when SAVE_HEADER_1 =>
+ lvl1_debug_fsm <= x"3";
+ hd_wr_en_fsm <= '1';
+ hd_din_fsm <= "01" & x"0" & LVL1_CODE_IN & LVL1_TAG_IN(7 downto 0) & words_in_event;
+ LVL1_FSM_NEXT <= SAVE_HEADER_2;
+
+ when SAVE_HEADER_2 =>
+ lvl1_debug_fsm <= x"4";
+ hd_wr_en_fsm <= '1';
+ hd_din_fsm <= "01" & DATA_VERSION & x"0000" & x"00";
+ LVL1_FSM_NEXT <= SAVE_HEADER_MARKER;
+
+ when SAVE_HEADER_MARKER =>
+ lvl1_debug_fsm <= x"5";
+ hd_wr_en_fsm <= '1';
+ hd_din_fsm <= (others => '0');
+ if lvl1_memory_busy_i = '0' then
+ LVL1_FSM_NEXT <= IDLE;
+ else
+ LVL1_FSM_NEXT <= WAIT_FOR_EMPTYING_BUFFERS;
+ end if;
+
+ when WAIT_FOR_EMPTYING_BUFFERS =>
+ lvl1_debug_fsm <= x"6";
+ if lvl1_memory_busy_i = '0' then
+ LVL1_FSM_NEXT <= IDLE;
+ else
+ LVL1_FSM_NEXT <= WAIT_FOR_EMPTYING_BUFFERS;
+ end if;
+
+ when others =>
+ lvl1_debug_fsm <= x"f";
+ LVL1_FSM_NEXT <= IDLE;
+ end case;
+
+ end process LVL1_FSM_PROC;
+
+
+ --lvl2
+
+ LVL2_BUSY_OUT <= '0';--lvl2_busy_i;
+ LVL2_FSM_CLOCK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL2_FSM_CURRENT <= IDLE;
+ lvl2_debug <= x"1";
+ lvl2_busy_i <= '0';
+ hd_rd_en <= '0';
+ IPU_DATAREADY_OUT <= '0';
+ IPU_DATA_OUT <= (others => '0');
+ data_rd_en <= '0';
+ else
+ LVL2_FSM_CURRENT <= LVL2_FSM_NEXT;
+ lvl2_debug <= lvl2_debug_fsm;
+ lvl2_busy_i <= lvl2_busy_fsm;
+ hd_rd_en <= hd_rd_en_fsm;
+ IPU_DATAREADY_OUT <= ipu_dataready_out_fsm;
+ IPU_DATA_OUT <= ipu_data_out_fsm;
+ data_rd_en <= data_rd_en_fsm;
+ end if;
+ end if;
+ end process LVL2_FSM_CLOCK;
+
+ LVL2_FSM_PROC : process (CLK)
+ begin
+ lvl2_debug_fsm <= x"1";
+ lvl2_busy_fsm <= '1';
+ hd_rd_en_fsm <= '0';
+ ipu_dataready_out_fsm <= '0';
+ ipu_data_out_fsm <= (others => '0');
+ data_rd_en_fsm <= '0';
+
+ case (LVL2_FSM_CURRENT) is
+
+ when IDLE =>
+ lvl2_debug_fsm <= x"1";
+ lvl2_busy_fsm <= '0';
+ if LVL1_FSM_CURRENT = SAVE_HEADER_MARKER then
+ LVL2_FSM_NEXT <= WAIT_FOR_BUSY_END;
+ else
+ LVL2_FSM_NEXT <= IDLE;
+ end if;
+
+ when WAIT_FOR_BUSY_END =>
+ lvl2_debug_fsm <= x"2";
+ if IPU_READY_IN = '1' or CTS_TYPE = 1 then
+ LVL2_FSM_NEXT <= READOUT_HEADER_MARKER_1;
+ else
+ LVL2_FSM_NEXT <= WAIT_FOR_BUSY_END;
+ end if;
+
+ when READOUT_HEADER_MARKER_1 =>
+ lvl2_debug_fsm <= x"3";
+ if hd_dout(32) = '0' then
+ hd_rd_en_fsm <= '1';
+ LVL2_FSM_NEXT <= READOUT_HEADER_MARKER_2;
+ else
+ LVL2_FSM_NEXT <= SEND_HEADERS_AND_DATA;
+ end if;
+
+ when READOUT_HEADER_MARKER_2 =>
+ lvl2_debug_fsm <= x"4";
+ LVL2_FSM_NEXT <= READOUT_HEADER_MARKER_3;
+
+ when READOUT_HEADER_MARKER_3 =>
+ lvl2_debug_fsm <= x"4";
+ LVL2_FSM_NEXT <= READOUT_HEADER_MARKER_1;
+
+ when SEND_HEADERS_AND_DATA =>
+ lvl2_debug_fsm <= x"5";
+ hd_rd_en_fsm <= IPU_READY_IN;
+ ipu_dataready_out_fsm <= hd_dout(32);
+ ipu_data_out_fsm <= hd_dout(31 downto 0);
+ if hd_dout(32) = '0' then
+ LVL2_FSM_NEXT <= READOUT_DATA_MARKER_1;
+ else
+ LVL2_FSM_NEXT <= SEND_HEADERS_AND_DATA;
+ end if;
+
+ when READOUT_DATA_MARKER_1 =>
+ lvl2_debug_fsm <= x"6";
+ if data_dout(32) = '0' then
+ LVL2_FSM_NEXT <= READOUT_DATA_MARKER_2;
+ data_rd_en_fsm <= '1';
+ else
+ LVL2_FSM_NEXT <= SEND_DATA;
+ end if;
+ when READOUT_DATA_MARKER_2 =>
+ lvl2_debug_fsm <= x"7";
+ LVL2_FSM_NEXT <= READOUT_DATA_MARKER_3;
+
+ when READOUT_DATA_MARKER_3 =>
+ lvl2_debug_fsm <= x"7";
+ LVL2_FSM_NEXT <= READOUT_DATA_MARKER_1;
+
+ when SEND_DATA =>
+ lvl2_debug_fsm <= x"8";
+ ipu_data_out_fsm <= data_dout(31 downto 0);
+ ipu_dataready_out_fsm <= data_dout(32);
+ data_rd_en_fsm <= IPU_READY_IN;
+ if data_dout(32) = '0' then
+ LVL2_FSM_NEXT <= IDLE;
+ else
+ LVL2_FSM_NEXT <= SEND_DATA;
+ end if;
+
+ when others =>
+ lvl2_debug_fsm <= x"9";
+ LVL2_FSM_NEXT <= IDLE;
+
+ end case;
+ end process LVL2_FSM_PROC;
+
+
+ LVL1_STARTED_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 16)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ COUNT_OUT => test_counter_0,
+ UP_IN => LVL1_TRBNET_TRIGGER_IN,
+ DOWN_IN => '0');
+
+ not_lvl1_busy <= not lvl1_busy_i;
+ LVL1_BUSY_END_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_lvl1_busy,
+ pulse => lvl1_busy_end_pulse);
+
+ LVL1_FINISHED_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ COUNT_OUT => test_counter_1,
+ UP_IN => lvl1_busy_end_pulse,
+ DOWN_IN => '0');
+
+ LVL1_FINISHED_OUT <= lvl1_busy_end_pulse;
+
+
+ not_lvl2_busy <= not lvl2_busy_i;
+ LVL2_BUSY_END_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_lvl2_busy,
+ pulse => lvl2_busy_end_pulse);
+
+ LVL2_BUSY_START_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl2_busy_i,
+ pulse => lvl2_busy_start_pulse);
+
+-- LVL2_BUSY <= lvl2_busy_i;
+
+ LVL2_STARTED_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 16)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ COUNT_OUT => test_counter_2,
+ UP_IN => lvl2_busy_start_pulse,
+ DOWN_IN => '0');
+
+ LVL2_FINISHED_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ COUNT_OUT => test_counter_3,
+ UP_IN => lvl2_busy_end_pulse,
+ DOWN_IN => '0');
+
+ LVL2_FINISHED_OUT <= lvl2_busy_end_pulse;
+
+
+ LVL1_MEMOMRY_BUSY_PROC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_memory_busy_i <= '0';
+ elsif (data_wcnt(9)= '1') or (hd_wcnt(9) = '1') then
+ lvl1_memory_busy_i <= '1';
+ else
+ lvl1_memory_busy_i <= '0';
+ end if;
+ end if;
+ end process LVL1_MEMOMRY_BUSY_PROC;
+
+
+end cts_readout;
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA40EP1
+PartName=LFSCM3GA40EP1-7FF1020C
+SpeedGrade=-7
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=4.7
+ModuleName=cts_readout_data_buff
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=10/19/2010
+Time=17:01:55
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=34
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=1
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 4.7
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n cts_readout_data_buff -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 512 -width 34 -regout -no_enable -pe -1 -pf -1 -fill -e
+
+-- Tue Oct 19 17:01:55 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity cts_readout_data_buff is
+ port (
+ Data: in std_logic_vector(33 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(33 downto 0);
+ WCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end cts_readout_data_buff;
+
+architecture Structure of cts_readout_data_buff is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal rden_i_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co4: std_logic;
+ signal cnt_con: std_logic;
+ signal co3: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co3_1: std_logic;
+ signal scuba_vlo: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co4_1: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_2: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "cts_readout_data_buff.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t3: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ AND2_t1: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t0: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_1: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ pdp_ram_0_0_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>scuba_vhi, ADW1=>scuba_vhi, ADW2=>scuba_vhi,
+ ADW3=>scuba_vhi, ADW4=>scuba_vlo, ADW5=>wcount_0,
+ ADW6=>wcount_1, ADW7=>wcount_2, ADW8=>wcount_3,
+ ADW9=>wcount_4, ADW10=>wcount_5, ADW11=>wcount_6,
+ ADW12=>wcount_7, ADW13=>wcount_8, CEW=>wren_i, CLKW=>Clock,
+ WE=>scuba_vhi, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
+ ADR5=>rcount_0, ADR6=>rcount_1, ADR7=>rcount_2,
+ ADR8=>rcount_3, ADR9=>rcount_4, ADR10=>rcount_5,
+ ADR11=>rcount_6, ADR12=>rcount_7, ADR13=>rcount_8,
+ CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i, CSR1=>scuba_vlo,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
+ DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
+ DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
+ DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33),
+ DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
+ DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
+ DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
+ DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
+ DO34=>Q(16), DO35=>Q(17));
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_21: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC1=>fcount_9, PC0=>fcount_8, CON=>cnt_con,
+ CO=>co4, NC1=>ifcount_9, NC0=>ifcount_8);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ e_cmp_4: ALEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i, B0=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A1=>fcount_9, A0=>fcount_8, B1=>wren_i_inv, B0=>wren_i,
+ CI=>co3_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_3,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC1=>wcount_9, PC0=>wcount_8, CO=>co4_1,
+ NC1=>iwcount_9, NC0=>iwcount_8);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_4,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC1=>rcount_9, PC0=>rcount_8, CO=>co4_2,
+ NC1=>ircount_9, NC0=>ircount_8);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of cts_readout_data_buff is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use work.version.all;
+use ieee.std_logic_arith.all;
+
+entity cts_set_width is
+ generic (
+ VECTOR_WIDTH : natural:=4
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ WIDTH_IN : in std_logic_vector(3 downto 0);
+ SIGNAL_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ SIGNAL_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0)
+ );
+end cts_set_width;
+
+architecture cts_set_width of cts_set_width is
+
+ component cts_width_rom --no_sim--
+--sim-- component cts_width_rom_simulation
+ port (
+ Address : in std_logic_vector(8 downto 0);
+ OutClock : in std_logic;
+ OutClockEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(35 downto 0));
+ end component;
+--in
+ signal signal_in_i : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ signal decode : std_logic_vector(3 downto 0);
+
+--rom
+ signal address : std_logic_vector(8 downto 0):="000000000";
+ signal q : std_logic_vector(35 downto 0);
+
+--out
+
+ type signal_out_array_type is array (0 to 8) of std_logic_vector(35 downto 0);
+ signal signal_out_array : signal_out_array_type;
+ signal last_byte,signal_out_i : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ signal signal_out_tmp_a,signal_out_tmp_b : std_logic_vector(3 downto 0);
+
+begin
+
+ WIDTH_DECODE8 : if VECTOR_WIDTH = 8 generate
+ DECODE_INPUT : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ case SIGNAL_IN(7 downto 0) is
+ when x"80" => decode <= x"8";
+ when x"40" => decode <= x"7";
+ when x"20" => decode <= x"6";
+ when x"10" => decode <= x"5";
+ when x"08" => decode <= x"4";
+ when x"04" => decode <= x"3";
+ when x"02" => decode <= x"2";
+ when x"01" => decode <= x"1";
+ when others => decode <= x"0";
+ end case;
+ end if;
+ end process DECODE_INPUT;
+ end generate WIDTH_DECODE8;
+
+-- WIDTH_DECODE4 : if VECTOR_WIDTH = 4 generate
+-- DECODE_INPUT : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- case SIGNAL_IN(3 downto 0) is
+-- when x"8" => decode <= x"4";
+-- when x"4" => decode <= x"3";
+-- when x"2" => decode <= x"2";
+-- when x"1" => decode <= x"1";
+-- when others => decode <= x"0";
+-- end case;
+-- end if;
+-- end process DECODE_INPUT;
+-- end generate WIDTH_DECODE4;
+
+
+-- SYNCH_SIGNALS : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- address <= '0' & WIDTH_IN & decode;
+-- end if;
+-- end process SYNCH_SIGNALS;
+
+ WIDTH_DECODE4 : if VECTOR_WIDTH = 4 generate
+ DECODE_INPUT : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ case SIGNAL_IN(3 downto 0) is
+ when x"8" => address <= '0' & WIDTH_IN & x"4";
+ when x"4" => address <= '0' & WIDTH_IN & x"3";
+ when x"2" => address <= '0' & WIDTH_IN & x"2";
+ when x"1" => address <= '0' & WIDTH_IN & x"1";
+ when others => address <= '0' & WIDTH_IN & x"0";
+ end case;
+ end if;
+ end process DECODE_INPUT;
+ end generate WIDTH_DECODE4;
+
+
+ THE_CTS_WIDTH_ROM: cts_width_rom --no_sim--
+ --sim-- THE_CTS_WIDTH_ROM: cts_width_rom_simulation
+ port map (
+ Address => address,
+ OutClock => CLK,
+ OutClockEn => '1',
+ Reset => RESET,
+ Q => q);
+ --output of the memory is 4 signals (4*8bits)
+
+ OUT_WIDTH8: if VECTOR_WIDTH = 8 generate
+ MAKE_OUT_SIGNAL : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ signal_out_array(0) <= q;
+ signal_out_array(1) <= signal_out_array(0);
+ signal_out_array(2) <= signal_out_array(1);
+ signal_out_array(3) <= signal_out_array(2);
+ signal_out_array(4) <= signal_out_array(3);
+ end if;
+ end process MAKE_OUT_SIGNAL;
+
+ last_byte <= x"0" & signal_out_array(4)(35 downto 32);
+
+ SET_OUTPUT : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ signal_out_i <= signal_out_array(0)(7 downto 0) or
+ signal_out_array(1)(15 downto 8) or
+ signal_out_array(2)(23 downto 16) or
+ signal_out_array(3)(31 downto 24) or
+ last_byte;
+ end if;
+ end process SET_OUTPUT;
+ end generate OUT_WIDTH8;
+
+ OUT_WIDTH4: if VECTOR_WIDTH = 4 generate
+ MAKE_OUT_SIGNAL : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ signal_out_array(0) <= q;
+ signal_out_array(1) <= signal_out_array(0);
+ signal_out_array(2) <= signal_out_array(1);
+ signal_out_array(3) <= signal_out_array(2);
+ signal_out_array(4) <= signal_out_array(3);
+ signal_out_array(5) <= signal_out_array(4);
+ signal_out_array(6) <= signal_out_array(5);
+ signal_out_array(7) <= signal_out_array(6);
+ signal_out_array(8) <= signal_out_array(7);
+ end if;
+ end process MAKE_OUT_SIGNAL;
+
+ SET_OUTPUT_A : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ signal_out_tmp_a <= signal_out_array(0)(3 downto 0) or
+ signal_out_array(1)(7 downto 4) or
+ signal_out_array(2)(11 downto 8) or
+ signal_out_array(3)(15 downto 12) or
+ signal_out_array(4)(19 downto 16);
+ end if;
+ end process SET_OUTPUT_A;
+ SET_OUTPUT_B : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ signal_out_tmp_b <= signal_out_array(5)(23 downto 20) or
+ signal_out_array(6)(27 downto 24) or
+ signal_out_array(7)(31 downto 28) or
+ signal_out_array(8)(35 downto 32);
+ end if;
+ end process SET_OUTPUT_B;
+ SET_OUTPUT_END : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ signal_out_i <= signal_out_tmp_a or signal_out_tmp_b;
+ end if;
+ end process SET_OUTPUT_END;
+
+
+
+
+-- SET_OUTPUT : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- signal_out_i <= signal_out_array(0)(3 downto 0) or
+-- signal_out_array(1)(7 downto 4) or
+-- signal_out_array(2)(11 downto 8) or
+-- signal_out_array(3)(15 downto 12) or
+-- signal_out_array(4)(19 downto 16) or
+-- signal_out_array(5)(23 downto 20) or
+-- signal_out_array(6)(27 downto 24) or
+-- signal_out_array(7)(31 downto 28) or
+-- signal_out_array(8)(35 downto 32);
+-- end if;
+-- end process SET_OUTPUT;
+ end generate OUT_WIDTH4;
+
+ SIGNAL_OUT <= signal_out_i;
+
+end cts_set_width;
+
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use work.version.all;
+use ieee.std_logic_arith.all;
+
+entity cts_set_width_large is
+ generic (
+ VECTOR_WIDTH : natural:=4
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ WIDTH_IN : in std_logic_vector(3 downto 0);
+ SIGNAL_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ SIGNAL_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0)
+ );
+end cts_set_width_large;
+
+architecture cts_set_width_large of cts_set_width_large is
+
+ signal there_was_signal : std_logic;
+ signal detected_falling_edge : std_logic;
+ signal leading_edge, trailing_edge, trailing_edge_last : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ signal width_cntr, width_cntr_sync : std_logic_vector(3 downto 0);
+ signal out_signal : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ signal signal_in_sync_a, signal_in_sync_b : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+
+begin -- cts_set_width
+
+ SAVE_OLD_PULSE : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ there_was_signal <= SIGNAL_IN(VECTOR_WIDTH - 1);
+ end if;
+ end process SAVE_OLD_PULSE;
+
+ CHECK_FALLING_EDGE : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ detected_falling_edge <= '0';
+ elsif
+ (SIGNAL_IN(0) = '0' and there_was_signal = '1') or
+ (SIGNAL_IN(1) = '0' and SIGNAL_IN(0) = '1') or
+ (SIGNAL_IN(2) = '0' and SIGNAL_IN(1) = '1') or
+ (SIGNAL_IN(3) = '0' and SIGNAL_IN(2) = '1') then
+ detected_falling_edge <= '1';
+ else
+ detected_falling_edge <= '0';
+ end if;
+ end if;
+ end process CHECK_FALLING_EDGE;
+
+ VECTOR_IN_WIDTH4 : if VECTOR_WIDTH = 4 generate
+ CREATE_EDGES : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if detected_falling_edge = '1' then
+ case signal_in_sync_a(3 downto 0) is
+ when x"0" => --falling edge in previous word
+ leading_edge <= x"8";
+ trailing_edge <= x"f";
+
+ --first bit
+ when x"1" =>
+ leading_edge <= x"f";
+ trailing_edge <= x"1";
+
+ --2nd bit
+
+ when x"2" =>
+ leading_edge <= x"e";
+ trailing_edge <= x"3";
+
+ when x"3" =>
+ leading_edge <= x"f";
+ trailing_edge <= x"3";
+
+ --3rd bit
+
+ when x"4" =>
+ leading_edge <= x"c";
+ trailing_edge <= x"7";
+
+ when x"6" =>
+ leading_edge <= x"e";
+ trailing_edge <= x"7";
+
+ when x"7" =>
+ leading_edge <= x"f";
+ trailing_edge <= x"7";
+
+ --4th
+
+ when x"8" =>
+ leading_edge <= x"8";
+ trailing_edge <= x"f";
+
+ when x"c" =>
+ leading_edge <= x"c";
+ trailing_edge <= x"f";
+
+ when x"e" =>
+ leading_edge <= x"e";
+ trailing_edge <= x"f";
+
+ when x"f" =>
+ leading_edge <= x"f";
+ trailing_edge <= x"f";
+
+ when others =>
+ leading_edge <= x"f";
+ trailing_edge <= x"0";
+
+ end case;
+ end if;
+ end if;
+ end process CREATE_EDGES;
+ end generate VECTOR_IN_WIDTH4;
+
+
+ SIGNAL_IN_SYNC_PROC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ signal_in_sync_a <= SIGNAL_IN;
+ signal_in_sync_b <= signal_in_sync_a;
+ width_cntr_sync <= width_cntr;
+ trailing_edge_last <= trailing_edge;
+ end if;
+ end process SIGNAL_IN_SYNC_PROC;
+
+ COUNT_DOWN_FOR_WIDTH : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ width_cntr <= (others => '0');
+ elsif detected_falling_edge = '1' then
+ width_cntr <= WIDTH_IN;
+ elsif width_cntr > 0 then
+ width_cntr <= width_cntr - 1;
+ else
+ width_cntr <= width_cntr;
+ end if;
+ end if;
+ end process COUNT_DOWN_FOR_WIDTH;
+
+ SEND_OUT_SIGNAL : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ out_signal <= (others => '0');
+ elsif WIDTH_IN = 0 then
+ out_signal <= signal_in_sync_b;
+ elsif width_cntr_sync = 1 and width_cntr = 0 then
+ out_signal <= trailing_edge;
+ elsif width_cntr = 0 then
+ out_signal <= (others => '0');
+ elsif width_cntr = WIDTH_IN and width_cntr_sync = 0 then
+ out_signal <= leading_edge;
+ elsif width_cntr_sync = 1 and width_cntr /= 0 then
+ out_signal <= trailing_edge_last or leading_edge;
+ else
+ out_signal <= (others => '1');
+ end if;
+ end if;
+ end process SEND_OUT_SIGNAL;
+ SIGNAL_OUT <= out_signal;
+
+end cts_set_width_large;
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use work.version.all;
+use ieee.std_logic_arith.all;
+
+entity cts_simple_data_transport is
+
+ generic (
+ UP_WIDTH : natural;
+ DOWN_WIDTH : natural;
+
+ UP_RW_REGISTERS_NUMBER : natural;
+ UP_R_REGISTERS_NUMBER : natural;
+ UP_SPECIAL_REGISTERS_NUMBER : natural;
+
+ DOWN_RW_REGISTERS_NUMBER : natural;
+ DOWN_R_REGISTERS_NUMBER : natural;
+ DOWN_SPECIAL_REGISTERS_NUMBER : natural;
+
+ UP_CLK_SELECT : natural; --0 other component, 1 locally created
+ FPGA_TYPE : natural --0 Lattice SCM, 1 ECP2M
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+
+ DOWN_RW_REGISTER_OUT : out std_logic_vector(DOWN_RW_REGISTERS_NUMBER*32-1 downto 0);
+ DOWN_R_REGISTER_OUT : out std_logic_vector(DOWN_R_REGISTERS_NUMBER*32-1 downto 0);
+ DOWN_SPECIAL_REGISTER_OUT : out std_logic_vector(DOWN_SPECIAL_REGISTERS_NUMBER*32-1 downto 0);
+ DOWN_CLK_IN : in std_logic;
+ DOWN_DATA_IN : in std_logic_vector(DOWN_WIDTH - 1 downto 0);
+ DOWN_DATA_VALID_IN : in std_logic;
+ DOWN_ADDRESS_OUT : out std_logic_vector(7 downto 0);
+ DOWN_DATA_VALID_OUT : out std_logic;
+ DOWN_DATA_OUT : out std_logic_vector(31 downto 0);
+
+ UP_RW_REGISTER_IN : in std_logic_vector(UP_RW_REGISTERS_NUMBER*32-1 downto 0);
+ UP_R_REGISTER_IN : in std_logic_vector(UP_R_REGISTERS_NUMBER*32-1 downto 0);
+ UP_SPECIAL_REGISTER_IN : in std_logic_vector(UP_SPECIAL_REGISTERS_NUMBER*32-1 downto 0);
+ UP_SPECIAL_REGISTER_FINISHED_IN : in std_logic_vector(UP_SPECIAL_REGISTERS_NUMBER-1 downto 0);
+ UP_START_READ_STRUCTURE_OUT : out std_logic_vector(UP_SPECIAL_REGISTERS_NUMBER-1 downto 0);
+ UP_RD_EN_STRUCTURE_OUT : out std_logic_vector(UP_SPECIAL_REGISTERS_NUMBER-1 downto 0);
+ UP_CLK_OUT : out std_logic;
+ UP_CLK_IN : in std_logic;
+ UP_DATA_OUT : out std_logic_vector(UP_WIDTH - 1 downto 0);
+ UP_DATA_VALID_OUT : out std_logic;
+ -- rw reg from fpga 1
+ RW_ADDRESS_OUT : out std_logic_vector(31 downto 0);
+ RW_DATA_OUT : out std_logic_vector(31 downto 0);
+ RW_DATA_VALID_OUT : out std_logic
+ );
+end cts_simple_data_transport;
+
+architecture cts_simple_data_transport of cts_simple_data_transport is
+
+ component cts_fpga2_lvl1_lvl2_fifo
+ generic (
+ SIZE_OF_DATA_BUS_IN : natural;
+ FPGA_TYPE : natural);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ FPGA1_CLK_IN : in std_logic;
+ DATA_IN : in std_logic_vector(SIZE_OF_DATA_BUS_IN-1 downto 0);
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ WR_EN_IN : in std_logic;
+ RD_EN_IN : in std_logic;
+ RCNT_OUT : out std_logic_vector(9 downto 0);
+ EMPTY_OUT : out std_logic;
+ FULL_OUT : out std_logic);
+ end component;
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ --up
+ signal up_clk,up_clk_sync : std_logic_vector(0 downto 0);
+ type UP_SEND is (START, UP_SEND_R_A, UP_SEND_R_B, WAIT_A, PREPARE_SPECIAL, UP_SEND_SPECIAL_A, UP_SEND_SPECIAL_B, WAIT_B, UP_SEND_RW_A, UP_SEND_RW_B);
+ signal UP_SEND_CURRENT, UP_SEND_NEXT : UP_SEND;
+ signal up_clk_next : std_logic;
+ --r
+ signal r_data_cntr_int : integer range 0 to 5255 :=0;
+ signal r_data_cntr : std_logic_vector(11 downto 0);
+ signal r_data_cntr_up, r_data_cntr_up_fsm, r_data_cntr_rst, r_data_cntr_rst_fsm : std_logic;
+ --rw
+ signal rw_data_cntr_int : integer range 0 to 5255 :=0;
+ signal rw_data_cntr : std_logic_vector(11 downto 0);
+ signal rw_data_cntr_up, rw_data_cntr_up_fsm, rw_data_cntr_rst, rw_data_cntr_rst_fsm : std_logic;
+ --special uses r_counters
+ signal up_data_valid_fsm, up_data_valid_i : std_logic;
+ signal up_data_fsm, up_data_i : std_logic_vector(UP_WIDTH - 1 downto 0);
+ signal up_rd_en_structure_out_i, up_rd_en_structure_out_fsm, start_read_structure_out_i, start_read_structure_out_fsm : std_logic_vector(UP_SPECIAL_REGISTERS_NUMBER - 1 downto 0);
+ signal up_special_register_finished_in_saved : std_logic;
+
+ --down
+
+ signal down_register_all : std_logic_vector((DOWN_R_REGISTERS_NUMBER + DOWN_SPECIAL_REGISTERS_NUMBER + DOWN_RW_REGISTERS_NUMBER)*32-1 downto 0);
+ signal down_data_empty, down_data_full, down_data_all_cntr_up, down_data_all_rst : std_logic;
+ signal down_data_all_cntr : std_logic_vector(7 downto 0);
+ signal down_data_out_i : std_logic_vector(31 downto 0);
+ signal down_data_empty_sync_a, down_data_empty_sync_b : std_logic;
+ signal down_data_bit_cntr : std_logic_vector(1 downto 0);
+ signal saved_address, saved_data : std_logic_vector(31 downto 0);
+ signal wait_cntr_rst, wait_cntr_up : std_logic;
+ signal wait_cntr : std_logic_vector(7 downto 0);
+ signal rw_data_valid_out_buf : std_logic;
+ signal reset_fifo_down : std_logic;
+
+begin
+
+ -----------------------------------------------------------------------------
+ -- UP
+ -----------------------------------------------------------------------------
+
+ UP_CLOCK_SELECTION_A: if UP_CLK_SELECT = 0 generate
+ up_clk(0) <= UP_CLK_IN;
+ end generate UP_CLOCK_SELECTION_A;
+
+ UP_CLOCK_SELECTION_B: if UP_CLK_SELECT = 1 generate
+ UP_CLK_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 1)
+ port map (
+ CLK => CLK,
+ RESET => RESET,--lvl1_slow_data_rst,
+ COUNT_OUT => up_clk,
+ UP_IN => '1',
+ DOWN_IN => '0');
+ end generate UP_CLOCK_SELECTION_B;
+
+ COUNTER_FOR_SENDING_R: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 12)
+ port map (
+ CLK => CLK,
+ RESET => r_data_cntr_rst,
+ COUNT_OUT => r_data_cntr,
+ UP_IN => r_data_cntr_up,
+ DOWN_IN => '0');
+
+ COUNTER_FOR_SENDING_RW: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 12)
+ port map (
+ CLK => CLK,
+ RESET => rw_data_cntr_rst,
+ COUNT_OUT => rw_data_cntr,
+ UP_IN => rw_data_cntr_up,
+ DOWN_IN => '0');
+
+ THE_WAIT_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => wait_cntr_rst,
+ COUNT_OUT => wait_cntr,
+ UP_IN => wait_cntr_up,
+ DOWN_IN => '0');
+
+
+ UP_CLK_FSM_PROC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ up_clk_next <= '0';
+ elsif up_clk(0) = '1' and up_clk_sync(0) = '0' then
+ up_clk_next <= '1';
+ else
+ up_clk_next <= '0';
+ end if;
+ end if;
+ end process UP_CLK_FSM_PROC;
+
+
+ SAVE_SPECIAL_REGISTER_FINISH : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or start_read_structure_out_i(0) = '1' then
+ up_special_register_finished_in_saved <= '0';
+ elsif UP_SPECIAL_REGISTER_FINISHED_IN(0) = '1' then
+ up_special_register_finished_in_saved <= '1';
+ end if;
+ end if;
+ end process SAVE_SPECIAL_REGISTER_FINISH;
+
+ UP_DATA_VALID_OUT <= up_data_valid_i;
+ UP_DATA_OUT <= up_data_i;
+ UP_START_READ_STRUCTURE_OUT <= start_read_structure_out_i;
+ UP_RD_EN_STRUCTURE_OUT <= up_rd_en_structure_out_i;
+
+ UP_SEND_CLK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ UP_SEND_CURRENT <= START;
+ wait_cntr_up <= '0';
+ wait_cntr_rst <= '1';
+ r_data_cntr_int <= 0;
+ r_data_cntr_up <= '0';
+ r_data_cntr_rst <= '1';
+ rw_data_cntr_int <= 0;
+ rw_data_cntr_up <= '0';
+ rw_data_cntr_rst <= '1';
+ up_data_valid_i <= '0';
+ up_data_i <= (others => '0');
+ start_read_structure_out_i <= (others => '0');
+ up_rd_en_structure_out_i <= (others => '0');
+ up_clk_sync(0) <= '0';
+ else
+ UP_SEND_CURRENT <= UP_SEND_NEXT;
+ wait_cntr_up <= r_data_cntr_rst;
+ wait_cntr_rst <= r_data_cntr_up;
+
+ r_data_cntr_int <= conv_integer(r_data_cntr(11 downto 0));
+ r_data_cntr_up <= r_data_cntr_up_fsm;
+ r_data_cntr_rst <= r_data_cntr_rst_fsm;
+ rw_data_cntr_int <= conv_integer(rw_data_cntr(11 downto 0));
+ rw_data_cntr_up <= rw_data_cntr_up_fsm;
+ rw_data_cntr_rst <= rw_data_cntr_rst_fsm;
+ up_data_valid_i <= up_data_valid_fsm;
+ up_data_i <= up_data_fsm;
+ start_read_structure_out_i <= start_read_structure_out_fsm;
+ up_rd_en_structure_out_i <= up_rd_en_structure_out_fsm;
+ up_clk_sync(0) <= up_clk(0);
+ end if;
+ end if;
+ end process UP_SEND_CLK;
+
+ UP_SEND_PROC : process (CLK)
+ begin
+
+ r_data_cntr_up_fsm <= '0';
+ r_data_cntr_rst_fsm <= '0';
+ rw_data_cntr_up_fsm <= '0';
+ rw_data_cntr_rst_fsm <= '0';
+ up_data_valid_fsm <= '1';
+ up_data_fsm <= (others => '0');
+ start_read_structure_out_fsm <= (others => '0');
+ up_rd_en_structure_out_fsm <= (others => '0');
+ case (UP_SEND_CURRENT) is
+
+ when START =>
+ up_data_valid_fsm <= '0';
+ if up_clk(0) = '0' and wait_cntr(6) = '1' then
+ r_data_cntr_up_fsm <= '1';
+ r_data_cntr_rst_fsm <= '0';
+ UP_SEND_NEXT <= UP_SEND_R_A;
+ else
+ r_data_cntr_rst_fsm <= '1';
+ UP_SEND_NEXT <= START;
+ end if;
+
+ --read registers
+ when UP_SEND_R_A =>
+
+ if up_clk(0) = '1' and r_data_cntr < ((UP_R_REGISTERS_NUMBER-1)*(32/UP_WIDTH)-1) then
+ up_data_fsm <= UP_R_REGISTER_IN((r_data_cntr_int+1)*UP_WIDTH-1 downto r_data_cntr_int*UP_WIDTH);
+ UP_SEND_NEXT <= UP_SEND_R_B;
+ elsif up_clk(0) = '1' then
+ UP_SEND_NEXT <= UP_SEND_R_B;
+ else
+ UP_SEND_NEXT <= UP_SEND_R_A;
+ end if;
+
+ when UP_SEND_R_B =>
+ if r_data_cntr < (UP_R_REGISTERS_NUMBER)*(32/UP_WIDTH)-1 then
+ r_data_cntr_up_fsm <= '1';
+ up_data_fsm <= UP_R_REGISTER_IN((r_data_cntr_int+1)*UP_WIDTH-1 downto r_data_cntr_int*UP_WIDTH);
+ UP_SEND_NEXT <= UP_SEND_R_A;
+ elsif r_data_cntr = (192*(32/UP_WIDTH)) then
+ r_data_cntr_rst_fsm <= '1';
+ rw_data_cntr_up_fsm <= '1';
+ UP_SEND_NEXT <= UP_SEND_RW_A;
+ else
+ r_data_cntr_up_fsm <= '1';
+ UP_SEND_NEXT <= UP_SEND_R_A;--UP_SEND_SPECIAL_A;
+ end if;
+
+ --write registers
+ when UP_SEND_RW_A =>
+
+ if up_clk(0) = '1' and rw_data_cntr < ((UP_RW_REGISTERS_NUMBER-1)*(32/UP_WIDTH)-1) then
+ up_data_fsm <= UP_RW_REGISTER_IN((rw_data_cntr_int+1)*UP_WIDTH-1 downto rw_data_cntr_int*UP_WIDTH);
+ UP_SEND_NEXT <= UP_SEND_RW_B;
+ elsif up_clk(0) = '1' then
+ UP_SEND_NEXT <= UP_SEND_RW_B;
+ else
+ UP_SEND_NEXT <= UP_SEND_RW_A;
+ end if;
+
+ when UP_SEND_RW_B =>
+ if rw_data_cntr < (UP_RW_REGISTERS_NUMBER)*(32/UP_WIDTH)-1 then
+ rw_data_cntr_up_fsm <= '1';
+ up_data_fsm <= UP_RW_REGISTER_IN((rw_data_cntr_int+1)*UP_WIDTH-1 downto rw_data_cntr_int*UP_WIDTH);
+ UP_SEND_NEXT <= UP_SEND_RW_A;
+ elsif rw_data_cntr = (63*(32/UP_WIDTH)) then
+ rw_data_cntr_rst_fsm <= '1';
+ start_read_structure_out_fsm(0) <= '1';
+ UP_SEND_NEXT <= PREPARE_SPECIAL;--UP_SEND_SPECIAL_A;--START;------------------firs step------------------------------UP_SEND_SPECIAL_A;
+ else
+ rw_data_cntr_up_fsm <= '1';
+ UP_SEND_NEXT <= UP_SEND_RW_A;
+ end if;
+
+ when PREPARE_SPECIAL =>
+
+ if rw_data_cntr = ((32/UP_WIDTH)*2 - 4) then
+ rw_data_cntr_rst_fsm <= '1';
+ UP_SEND_NEXT <= UP_SEND_SPECIAL_A;
+ else
+ rw_data_cntr_up_fsm <= '1';
+ UP_SEND_NEXT <= PREPARE_SPECIAL;
+ end if;
+
+ when UP_SEND_SPECIAL_A =>
+ up_data_fsm <= UP_SPECIAL_REGISTER_IN((r_data_cntr_int+1)*UP_WIDTH-1 downto r_data_cntr_int*UP_WIDTH);
+ if up_clk(0) = '1' then
+ UP_SEND_NEXT <= UP_SEND_SPECIAL_B;
+ else
+ UP_SEND_NEXT <= UP_SEND_SPECIAL_A;
+ end if;
+
+ when UP_SEND_SPECIAL_B =>
+ up_data_fsm <= UP_SPECIAL_REGISTER_IN((r_data_cntr_int+1)*UP_WIDTH-1 downto r_data_cntr_int*UP_WIDTH);
+ r_data_cntr_up_fsm <= '1';
+ if up_special_register_finished_in_saved = '1' then
+ r_data_cntr_rst_fsm <= '1';
+ UP_SEND_NEXT <= START;
+ elsif r_data_cntr = 32/UP_WIDTH - 1 then
+ r_data_cntr_rst_fsm <= '1';
+ up_rd_en_structure_out_fsm(0) <= '1';
+ UP_SEND_NEXT <= UP_SEND_SPECIAL_A;
+ else
+ UP_SEND_NEXT <= UP_SEND_SPECIAL_A;
+ end if;
+
+ when others =>
+ UP_SEND_NEXT <= START;
+
+ end case;
+ end process UP_SEND_PROC;
+
+ -----------------------------------------------------------------------------
+ -- DOWN
+ -----------------------------------------------------------------------------
+
+ THE_CTS_FPGA2_LVL2_FIFO: cts_fpga2_lvl1_lvl2_fifo
+ generic map (
+ SIZE_OF_DATA_BUS_IN => DOWN_WIDTH,
+ FPGA_TYPE => FPGA_TYPE)
+ port map (
+ RESET => reset_fifo_down,--RESET,
+ CLK => CLK,
+ FPGA1_CLK_IN => DOWN_CLK_IN,
+ DATA_IN => DOWN_DATA_IN,
+ DATA_OUT => down_data_out_i,
+ WR_EN_IN => DOWN_DATA_VALID_IN,
+ RD_EN_IN => '1',
+ RCNT_OUT => open,
+ EMPTY_OUT => down_data_empty,
+ FULL_OUT => down_data_full);
+
+
+ SET_RW_REG_DATA_VALID : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reset_fifo_down <= '1';
+ down_data_empty_sync_a <= down_data_empty;
+ down_data_empty_sync_b <= down_data_empty_sync_a;
+ else
+ reset_fifo_down <= rw_data_valid_out_buf;
+ down_data_empty_sync_a <= down_data_empty;
+ down_data_empty_sync_b <= down_data_empty_sync_a;
+ end if;
+ end if;
+ end process SET_RW_REG_DATA_VALID;
+
+ SET_BIT_CNTR : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or rw_data_valid_out_buf = '1' then
+ down_data_bit_cntr <= "00";
+ elsif down_data_empty_sync_b = '0' then
+ down_data_bit_cntr <= down_data_bit_cntr + 1;
+ else
+ down_data_bit_cntr <= down_data_bit_cntr;
+ end if;
+ end if;
+ end process SET_BIT_CNTR;
+
+ SAVE_RW_ADDRESS_AND_DATA : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ saved_address <= (others => '0');
+ saved_data <= (others => '0');
+ elsif down_data_bit_cntr = 0 and down_data_empty_sync_b = '0' then
+ saved_address <= down_data_out_i;
+ saved_data <= saved_data;
+ elsif down_data_bit_cntr = 1 and down_data_empty_sync_b = '0' then
+ saved_address <= saved_address;
+ saved_data <= down_data_out_i;
+ else
+ saved_address <= saved_address;
+ saved_data <= saved_data;
+ end if;
+ end if;
+ end process SAVE_RW_ADDRESS_AND_DATA;
+
+ RW_ADDRESS_OUT <= saved_address;
+ RW_DATA_OUT <= saved_data;
+
+ SEND_RW_REQUEST : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ rw_data_valid_out_buf <= '0';
+ elsif down_data_bit_cntr = 2 then
+ rw_data_valid_out_buf <= '1';
+ else
+ rw_data_valid_out_buf <= '0';
+ end if;
+ end if;
+ end process SEND_RW_REQUEST;
+
+ RW_DATA_VALID_OUT <= rw_data_valid_out_buf;
+-- SYNC_DOWN : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- down_data_all_cntr_up <= '0';
+-- else
+-- down_data_all_cntr_up <= not down_data_empty;
+-- end if;
+-- end if;
+-- end process SYNC_DOWN;
+
+-- RESET_DATA_CNTR_DOWN : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' or DOWN_DATA_VALID_IN = '0' then --(down_data_all_cntr = DOWN_R_REGISTERS_NUMBER + DOWN_SPECIAL_REGISTERS_NUMBER + DOWN_RW_REGISTERS_NUMBER) or then
+-- down_data_all_rst <= '1';
+-- else
+-- down_data_all_rst <= '0';
+-- end if;
+-- end if;
+-- end process RESET_DATA_CNTR_DOWN;
+
+-- DATA_DOWN_COUNTER: up_down_counter
+-- generic map (
+-- NUMBER_OF_BITS => 8)
+-- port map (
+-- CLK => CLK,
+-- RESET => down_data_all_rst,
+-- COUNT_OUT => down_data_all_cntr,
+-- UP_IN => down_data_all_cntr_up,
+-- DOWN_IN => '0');
+
+-- DOWN_ADDRESS_OUT <= down_data_all_cntr;
+-- DOWN_DATA_OUT <= down_data_out_i;
+-- DOWN_DATA_VALID_OUT <= down_data_all_cntr_up;
+
+
+-- MAKING_OUT_R_REGISTERS: for i in 0 to DOWN_R_REGISTERS_NUMBER - 1 generate
+-- MULTIPLEX_DOWN_R_DATA_OUT : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- down_register_all( (i+1)*32-1 downto i*32 ) <= (others => '0');
+-- elsif down_data_all_cntr = i then
+-- down_register_all( (i+1)*32-1 downto i*32 ) <= down_data_out_i;
+-- else
+-- down_register_all( (i+1)*32-1 downto i*32 ) <= down_register_all( (i+1)*32-1 downto i*32 );
+-- end if;
+-- end if;
+-- end process MULTIPLEX_DOWN_R_DATA_OUT;
+-- end generate MAKING_OUT_R_REGISTERS;
+
+-- MAKING_OUT_SPECIAL_REGISTERS: for i in DOWN_R_REGISTERS_NUMBER to DOWN_R_REGISTERS_NUMBER + DOWN_SPECIAL_REGISTERS_NUMBER - 1 generate
+-- MULTIPLEX_DOWN_SPECIAL_DATA_OUT : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- down_register_all( (i+1)*32-1 downto i*32 ) <= (others => '0');
+-- elsif down_data_all_cntr = i and down_data_out_i(31) = '1' then
+-- --31st bit is a marker for the new beam struckure
+-- down_register_all( (i+1)*32-1 downto i*32 ) <= down_data_out_i;
+-- else
+-- down_register_all( (i+1)*32-1 downto i*32 ) <= down_register_all( (i+1)*32-1 downto i*32 );
+-- end if;
+-- end if;
+-- end process MULTIPLEX_DOWN_SPECIAL_DATA_OUT;
+-- end generate MAKING_OUT_SPECIAL_REGISTERS;
+
+-- MAKING_OUT_RW_REGISTERS: for i in DOWN_R_REGISTERS_NUMBER + DOWN_SPECIAL_REGISTERS_NUMBER to DOWN_RW_REGISTERS_NUMBER + DOWN_SPECIAL_REGISTERS_NUMBER + DOWN_RW_REGISTERS_NUMBER - 1 generate
+-- MULTIPLEX_DOWN_RW_DATA_OUT : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- down_register_all( (i+1)*32-1 downto i*32 ) <= (others => '0');
+-- elsif down_data_all_cntr = i then
+-- down_register_all( (i+1)*32-1 downto i*32 ) <= down_data_out_i;
+-- else
+-- down_register_all( (i+1)*32-1 downto i*32 ) <= down_register_all( (i+1)*32-1 downto i*32 );
+-- end if;
+-- end if;
+-- end process MULTIPLEX_DOWN_RW_DATA_OUT;
+-- end generate MAKING_OUT_RW_REGISTERS;
+
+
+-- DOWN_R_REGISTER_OUT <= down_register_all((DOWN_R_REGISTERS_NUMBER)*32-1 downto 0);
+-- DOWN_SPECIAL_REGISTER_OUT <= down_register_all((DOWN_R_REGISTERS_NUMBER+DOWN_SPECIAL_REGISTERS_NUMBER)*32-1 downto DOWN_R_REGISTERS_NUMBER*32);
+-- DOWN_RW_REGISTER_OUT <= down_register_all((DOWN_R_REGISTERS_NUMBER+DOWN_SPECIAL_REGISTERS_NUMBER+DOWN_RW_REGISTERS_NUMBER)*32-1 downto (DOWN_R_REGISTERS_NUMBER+DOWN_SPECIAL_REGISTERS_NUMBER)*32);
+
+end cts_simple_data_transport;
+
--- /dev/null
+; Copyright 1991-2010 Mentor Graphics Corporation
+;
+; All Rights Reserved.
+;
+; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
+; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
+;
+
+[Library]
+std = $MODEL_TECH/../std
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+; to use Vital 1995 version of the standard
+; IEEE library must be mapped to the vital1995 library
+; one cannot use the vital1995 library directly because it assume that it
+; is the IEEE library. If vital1995 and vital2000 are being mixed together then
+; ieee must be mapped to vital1995 and vital200 mapped to vital2000
+; ieee = $MODEL_TECH/../vital1995
+; for compatiblity with previously the VITAL2000 maps to a seperate library from IEEE
+; if one should not reference vital from both the ieee library and the vital library becasue
+; the vital packages are effectively different. If one needs to reference both libraies the
+; vital2000 and ieee MUST be mapped to the same library either $MODEL_TECH/../ieee
+; or $MODEL_TECH/../vital2000
+vital2000 = $MODEL_TECH/../vital2000
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+sv_std = $MODEL_TECH/../sv_std
+mtiAvm = $MODEL_TECH/../avm
+mtiOvm = $MODEL_TECH/../ovm-2.1.1
+mtiUPF = $MODEL_TECH/../upf_lib
+mtiPA = $MODEL_TECH/../pa_lib
+floatfixlib = $MODEL_TECH/../floatfixlib
+mc2_lib = $MODEL_TECH/../mc2_lib
+;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release
+;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release
+;mvc_lib = $MODEL_TECH/../mvc_lib
+
+work = work
+sc = /opt/lattice/diamond/1.3/ispfpga/vhdl/data/orca5/mti/work
+scm = /opt/lattice/diamond/1.3/ispfpga/vhdl/data/orca5/mti/work
+pcsc_work = /opt/lattice/diamond/1.3/ispfpga/vhdl/data/orca5/mti/work
+ecp2 = /opt/lattice/diamond/1.3/ispfpga/vhdl/data/ecp2/mti/work
+ecp2m = /opt/lattice/diamond/1.3/ispfpga/vhdl/data/ecp2/mti/work
+[vcom]
+; VHDL93 variable selects language version as the default.
+; Default is VHDL-2002.
+; Value of 0 or 1987 for VHDL-1987.
+; Value of 1 or 1993 for VHDL-1993.
+; Default or value of 2 or 2002 for VHDL-2002.
+; Value of 3 or 2008 for VHDL-2008
+VHDL93 = 2002
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; The .ini file has Explicit enabled so that std_logic_signed/unsigned
+; will match the behavior of synthesis tools.
+Explicit = 1
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = 0
+
+; Turn off PSL assertion warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Keep silent about case statement static warnings.
+; Default is to give a warning.
+; NoCaseStaticError = 1
+
+; Keep silent about warnings caused by aggregates that are not locally static.
+; Default is to give a warning.
+; NoOthersStaticError = 1
+
+; Treat as errors:
+; case statement static warnings
+; warnings caused by aggregates that are not locally static
+; Overrides NoCaseStaticError, NoOthersStaticError settings.
+; PedanticErrors = 1
+
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+; RequireConfigForAllDefaultBinding = 1
+
+; Perform default binding at compile time.
+; Default is to do default binding at load time.
+; BindAtCompile = 1;
+
+; Inhibit range checking on subscripts of arrays. Range checking on
+; scalars defined with subtypes is inhibited by default.
+; NoIndexCheck = 1
+
+; Inhibit range checks on all (implicit and explicit) assignments to
+; scalar objects defined with subtypes.
+; NoRangeCheck = 1
+
+; Run the 0-in compiler on the VHDL source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the synthesis prefix to be honored for synthesis pragma recognition.
+; Default is "".
+; SynthPrefix = ""
+
+; Turn on code coverage in VHDL design units. Default is off.
+; Coverage = sbceft
+
+; Turn off code coverage in VHDL subprograms. Default is on.
+; CoverageSub = 0
+
+; Automatically exclude VHDL case statement OTHERS choice branches.
+; This includes OTHERS choices in selected signal assigment statements.
+; Default is to not exclude.
+; CoverExcludeDefault = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Inform code coverage optimizations to respect VHDL 'H' and 'L'
+; values on signals in conditions and expressions, and to not automatically
+; convert them to '1' and '0'. Default is to not convert.
+; CoverRespectHandL = 0
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a VHDL condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is provided by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Use this directory for compiler temporary files instead of "work/_temp"
+; CompilerTempDir = /tmp
+
+; Set this to cause the compilers to force data to be committed to disk
+; when the files are closed.
+; SyncCompilerFiles = 1
+
+; Add VHDL-AMS declarations to package STANDARD
+; Default is not to add
+; AmsStandard = 1
+
+; Range and length checking will be performed on array indices and discrete
+; ranges, and when violations are found within subprograms, errors will be
+; reported. Default is to issue warnings for violations, because subprograms
+; may not be invoked.
+; NoDeferSubpgmCheck = 0
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/report/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/report/UCDB etc. This does not affect ;
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+[vlog]
+; Turn off inclusion of debugging info within design units.
+; Default is to include debugging info.
+; NoDebug = 1
+
+; Turn on `protect compiler directive processing.
+; Default is to ignore `protect directives.
+; Protect = 1
+
+; Turn off "Loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Activate optimizations on expressions that do not involve signals,
+; waits, or function/procedure/task invocations. Default is off.
+; ScalarOpts = 1
+
+; Turns on lint-style checking.
+; Show_Lint = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn on bad option warning. Default is off.
+; Show_BadOptionWarning = 1
+
+; Revert back to IEEE 1364-1995 syntax, default is 0 (off).
+; vlog95compat = 1
+
+; Turn off PSL warning messages. Default is to show warnings.
+; Show_PslChecksWarnings = 0
+
+; Enable parsing of embedded PSL assertions. Default is enabled.
+; EmbeddedPsl = 0
+
+; Set the threshold for automatically identifying sparse Verilog memories.
+; A memory with depth equal to or more than the sparse memory threshold gets
+; marked as sparse automatically, unless specified otherwise in source code
+; or by +nosparse commandline option of vlog or vopt.
+; The default is 1M. (i.e. memories with depth equal
+; to or greater than 1M are marked as sparse)
+; SparseMemThreshold = 1048576
+
+; Run the 0-in compiler on the Verilog source files
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0-in compiler.
+; Default is "".
+; ZeroInOptions = ""
+
+; Set the synthesis prefix to be honored for synthesis pragma recognition.
+; Default is "".
+; SynthPrefix = ""
+
+; Set the option to treat all files specified in a vlog invocation as a
+; single compilation unit. The default value is set to 0 which will treat
+; each file as a separate compilation unit as specified in the P1800 draft standard.
+; MultiFileCompilationUnit = 1
+
+; Turn on code coverage in Verilog design units. Default is off.
+; Coverage = sbceft
+
+; Automatically exclude Verilog case statement default branches.
+; Default is to not automatically exclude defaults.
+; CoverExcludeDefault = 1
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a Verilog condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable or disable Focused Expression Coverage analysis for conditions and
+; expressions. Focused Expression Coverage data is provided by default when
+; expression and/or condition coverage is active.
+; CoverFEC = 0
+
+; Enable or disable UDP Coverage analysis for conditions and expressions.
+; UDP Coverage data is provided by default when expression and/or condition
+; coverage is active.
+; CoverUDP = 0
+
+; Enable or disable short circuit evaluation of conditions and expressions when
+; condition or expression coverage is active. Short circuit evaluation is enabled
+; by default.
+; CoverShortCircuit = 0
+
+
+; Turn on code coverage in VLOG `celldefine modules and modules included
+; using vlog -v and -y. Default is off.
+; CoverCells = 1
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Control compiler and VOPT optimizations that are allowed when
+; code coverage is on. This is a number from 1 to 4, with the following
+; meanings (the default is 3):
+; 1 -- Turn off all optimizations that affect coverage reports.
+; 2 -- Allow optimizations that allow large performance improvements
+; by invoking sequential processes only when the data changes.
+; This may make major reductions in coverage counts.
+; 3 -- In addition, allow optimizations that may change expressions or
+; remove some statements. Allow constant propagation. Allow VHDL
+; subprogram inlining and VHDL FF recognition.
+; 4 -- In addition, allow optimizations that may remove major regions of
+; code by changing assignments to built-ins or removing unused
+; signals. Change Verilog gates to continuous assignments.
+; CoverOpt = 3
+
+; Specify the override for the default value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then LRM default
+; value of 0 (zero) is used. This is a compile time option.
+; SVCrossNumPrintMissingDefault = 0
+
+; Setting following to 1 would cause creation of variables which
+; would represent the value of Coverpoint expressions. This is used
+; in conjunction with "SVCoverpointExprVariablePrefix" option
+; in the modelsim.ini
+; EnableSVCoverpointExprVariable = 0
+
+; Specify the override for the prefix used in forming the variable names
+; which represent the Coverpoint expressions. This is used in conjunction with
+; "EnableSVCoverpointExprVariable" option of the modelsim.ini
+; The default prefix is "expr".
+; The variable name is
+; variable name => <prefix>_<coverpoint name>
+; SVCoverpointExprVariablePrefix = expr
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross option.goal (defined to be 100 in the LRM).
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupGoalDefault = 100
+
+; Override for the default value of the SystemVerilog covergroup,
+; coverpoint, and cross type_option.goal (defined to be 100 in the LRM)
+; NOTE: It does not override specific assignments in SystemVerilog
+; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal"
+; in the [vsim] section can override this value.
+; SVCovergroupTypeGoalDefault = 100
+
+; Specify the override for the default value of "strobe" option for the
+; Covergroup Type. This is a compile time option which forces "strobe" to
+; a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero). NOTE: This can be overriden by a runtime
+; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section.
+; SVCovergroupStrobeDefault = 0
+
+; Specify the override for the default value of "merge_instances" option for
+; the Covergroup Type. This is a compile time option which forces
+; "merge_instances" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupMergeInstancesDefault = 0
+
+; Specify the override for the default value of "per_instance" option for the
+; Covergroup variables. This is a compile time option which forces "per_instance"
+; to a user specified default value and supersedes SystemVerilog specified
+; default value of '0'(zero).
+; SVCovergroupPerInstanceDefault = 0
+
+; Specify the override for the default value of "get_inst_coverage" option for the
+; Covergroup variables. This is a compile time option which forces
+; "get_inst_coverage" to a user specified default value and supersedes
+; SystemVerilog specified default value of '0'(zero).
+; SVCovergroupGetInstCoverageDefault = 0
+
+;
+; A space separated list of resource libraries that contain precompiled
+; packages. The behavior is identical to using the "-L" switch.
+;
+; LibrarySearchPath = <path/lib> [<path/lib> ...]
+LibrarySearchPath = mtiAvm mtiOvm mtiUPF
+
+; The behavior is identical to the "-mixedansiports" switch. Default is off.
+; MixedAnsiPorts = 1
+
+; Enable SystemVerilog 3.1a $typeof() function. Default is off.
+; EnableTypeOf = 1
+
+; Only allow lower case pragmas. Default is disabled.
+; AcceptLowerCasePragmaOnly = 1
+
+; Set the maximum depth permitted for a recursive include file nesting.
+; IncludeRecursionDepthMax = 5
+
+; Turn ON detection of FSMs having single bit current state variable.
+; FsmSingle = 1
+
+; Turn off reset state transitions in FSM.
+; FsmResetTrans = 0
+
+; Turn off detections of FSMs having x-assignment.
+; FsmXAssign = 0
+
+; Turn ON detection of FSM Implicit Transitions.
+; FsmImplicitTrans = 1
+
+; List of file suffixes which will be read as SystemVerilog. White space
+; in extensions can be specified with a back-slash: "\ ". Back-slashes
+; can be specified with two consecutive back-slashes: "\\";
+; SVFileExtensions = sv svp svh
+
+; This setting is the same as the vlog -sv command line switch.
+; Enables SystemVerilog features and keywords when true (1).
+; When false (0), the rules of IEEE Std 1364-2001 are followed and
+; SystemVerilog keywords are ignored.
+; Svlog = 0
+
+; Prints attribute placed upon SV packages during package import
+; when true (1). The attribute will be ignored when this
+; entry is false (0). The attribute name is "package_load_message".
+; The value of this attribute is a string literal.
+; Default is true (1).
+; PrintSVPackageLoadingAttribute = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Controls if untyped parameters that are initialized with values greater
+; than 2147483647 are mapped to generics of type INTEGER or ignored.
+; If mapped to VHDL Integers, values greater than 2147483647
+; are mapped to negative values.
+; Default is to map these parameter to generic of type INTEGER
+; ForceUnsignedToVHDLInteger = 1
+
+; Enable AMS wreal (wired real) extensions. Default is 0.
+; WrealType = 1
+
+[sccom]
+; Enable use of SCV include files and library. Default is off.
+; UseScv = 1
+
+; Add C++ compiler options to the sccom command line by using this variable.
+; CppOptions = -g
+
+; Use custom C++ compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; CppPath = /usr/bin/g++
+
+; Enable verbose messages from sccom. Default is off.
+; SccomVerbose = 1
+
+; sccom logfile. Default is no logfile.
+; SccomLogfile = sccom.log
+
+; Enable use of SC_MS include files and library. Default is off.
+; UseScMs = 1
+
+[vopt]
+; Turn on code coverage in vopt. Default is off.
+; Coverage = sbceft
+
+; Control compiler optimizations that are allowed when
+; code coverage is on. Refer to the comment for this in the [vlog] area.
+; CoverOpt = 3
+
+; Increase or decrease the maximum number of rows allowed in a UDP table
+; implementing a vopt condition coverage or expression coverage expression.
+; More rows leads to a longer compile time, but more expressions covered.
+; CoverMaxUDPRows = 192
+
+; Increase or decrease the maximum number of input patterns that are present
+; in FEC table. This leads to a longer compile time with more expressions
+; covered with FEC metric.
+; CoverMaxFECRows = 192
+
+; Enable code coverage reporting of code that has been optimized away.
+; The default is not to report.
+; CoverReportCancelled = 1
+
+; Do not show immediate assertions with constant expressions in
+; GUI/reports/UCDB etc. By default immediate assertions with constant
+; expressions are shown in GUI/reports/UCDB etc. This does not affect
+; evaluation of immediate assertions.
+; ShowConstantImmediateAsserts = 0
+
+; Set the maximum number of iterations permitted for a generate loop.
+; Restricting this permits the implementation to recognize infinite
+; generate loops.
+; GenerateLoopIterationMax = 100000
+
+; Set the maximum depth permitted for a recursive generate instantiation.
+; Restricting this permits the implementation to recognize infinite
+; recursions.
+; GenerateRecursionDepthMax = 200
+
+
+[vsim]
+; vopt flow
+; Set to turn on automatic optimization of a design.
+; Default is on
+VoptFlow = 1
+
+; vopt automatic SDF
+; If automatic design optimization is on, enables automatic compilation
+; of SDF files.
+; Default is on, uncomment to turn off.
+; VoptAutoSDFCompile = 0
+
+; Automatic SDF compilation
+; Disables automatic compilation of SDF files in flows that support it.
+; Default is on, uncomment to turn off.
+; NoAutoSDFCompile = 1
+
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+Resolution = ns
+
+; Disable certain code coverage exclusions automatically.
+; Assertions and FSM are exluded from the code coverage by default
+; Set AutoExclusionsDisable = fsm to enable code coverage for fsm
+; Set AutoExclusionsDisable = assertions to enable code coverage for assertions
+; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions
+; Or specify comma or space separated list
+;AutoExclusionsDisable = fsm,assertions
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+; Should generally be set to default.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 450 us
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Control PSL and Verilog Assume directives during simulation
+; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
+; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
+; SimulateAssumeDirectives = 1
+
+; Control the simulation of PSL and SVA
+; These switches can be overridden by the vsim command line switches:
+; -psl, -nopsl, -sva, -nosva.
+; Set SimulatePSL = 0 to disable PSL simulation
+; Set SimulatePSL = 1 to enable PSL simulation (default)
+; SimulatePSL = 1
+; Set SimulateSVA = 0 to disable SVA simulation
+; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
+; SimulateSVA = 1
+
+; Directives to license manager can be set either as single value or as
+; space separated multi-values:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; noqueue Do not wait in the license queue when a license is not available
+; viewsim Try for viewer license but accept simulator license(s) instead
+; of queuing for viewer license (PE ONLY)
+; noviewer Disable checkout of msimviewer and vsim-viewer license
+; features (PE ONLY)
+; noslvhdl Disable checkout of qhsimvh and vsim license features
+; noslvlog Disable checkout of qhsimvl and vsimvlog license features
+; nomix Disable checkout of msimhdlmix and hdlmix license features
+; nolnl Disable checkout of msimhdlsim and hdlsim license features
+; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license
+; features
+; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
+; hdlmix license features
+; Single value:
+; License = plus
+; Multi-value:
+; License = noqueue plus
+
+; Stop the simulator after a VHDL assertion message.
+; Or stop the simulator after SystemVerilog severity system task.
+; The severity of VHDL assertion or severity system task
+; should be higher or equal.
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; VHDL assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %i - Instance pathname with process
+; %O - Process name
+; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
+; %P - Instance or Region path without leaf process
+; %F - File
+; %L - Line number of assertion or, if assertion is in a subprogram, line
+; from which the call is made
+; %% - Print '%' character
+; If specific format for assertion level is defined, use its format.
+; If specific format is not defined for assertion level:
+; - and if failure occurs during elaboration, use MessageFormatBreakLine;
+; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
+; level), use MessageFormatBreak;
+; - otherwise, use MessageFormat.
+; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n"
+; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n"
+; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"
+
+; Error File - alternate file for storing error messages
+; ErrorFile = error.log
+
+
+; Simulation Breakpoint messages
+; This flag controls the display of function names when reporting the location
+; where the simulator stops do to a breakpoint or fatal error.
+; Example w/function name: # Break in Process ctr at counter.vhd line 44
+; Example wo/function name: # Break at counter.vhd line 44
+ShowFunctions = 1
+
+; Default radix for all windows and commands.
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; VSIM Shutdown file
+; Filename to save u/i formats and configurations.
+; ShutdownFile = restart.do
+; To explicitly disable auto save:
+; ShutdownFile = --disable-auto-save
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+; CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format.
+; For VHDL, PathSeparator = /
+; For Verilog, PathSeparator = .
+; Must not be the same character as DatasetSeparator.
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example: sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Specify a unique path separator for the Signal Spy set of functions.
+; The default will be to use the PathSeparator variable.
+; Must not be the same character as DatasetSeparator.
+; SignalSpyPathSeparator = /
+
+; Used to control parsing of HDL identifiers input to the tool.
+; This includes CLI commands, vsim/vopt/vlog/vcom options,
+; string arguments to FLI/VPI/DPI calls, etc.
+; If set to 1, accept either Verilog escaped Id syntax or
+; VHDL extended id syntax, regardless of source language.
+; If set to 0, the syntax of the source language must be used.
+; Each identifier in a hierarchical name may need different syntax,
+; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or
+; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom"
+; GenerousIdentifierParsing = 1
+
+; Disable VHDL assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Disable SystemVerilog assertion messages
+; IgnoreSVAInfo = 1
+; IgnoreSVAWarning = 1
+; IgnoreSVAError = 1
+; IgnoreSVAFatal = 1
+
+; Do not print any additional information from Severity System tasks.
+; Only the message provided by the user is printed along with severity
+; information.
+; SVAPrintOnlyUserMessage = 1;
+
+; Default force kind. May be freeze, drive, deposit, or default
+; or in other terms, fixed, wired, or charged.
+; A value of "default" will use the signal kind to determine the
+; force kind, drive for resolved signals, freeze for unresolved signals
+; DefaultForceKind = freeze
+
+; Control the iteration of events when a VHDL signal is forced to a value
+; This flag can be set to honour the signal update event in next iteration,
+; the default is to update and propagate in the same iteration.
+; ForceSigNextIter = 1
+
+
+; If zero, open files when elaborated; otherwise, open files on
+; first read or write. Default is 0.
+; DelayFileOpen = 1
+
+; Control VHDL files opened for write.
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control the number of VHDL files open concurrently.
+; This number should always be less than the current ulimit
+; setting for max file descriptors.
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; Control the number of hierarchical regions displayed as
+; part of a signal name shown in the Wave window.
+; A value of zero tells VSIM to display the full name.
+; The default is 0.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings when changing VHDL constants and generics
+; Default is 1 to generate warning messages
+; WarnConstantChange = 0
+
+; Turn off warnings from accelerated versions of the std_logic_arith,
+; std_logic_unsigned, and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from accelerated versions of the IEEE numeric_std
+; and numeric_bit packages.
+; NumericStdNoWarnings = 1
+
+; Use old-style (pre-6.6) VHDL FOR generate statement iteration names
+; in the design hierarchy.
+; This style is controlled by the value of the GenerateFormat
+; value described next. Default is to use new-style names, which
+; comprise the generate statement label, '(', the value of the generate
+; parameter, and a closing ')'.
+; Uncomment this to use old-style names.
+; OldVhdlForGenNames = 1
+
+; Control the format of the old-style VHDL FOR generate statement region
+; name for each iteration. Do not quote it.
+; The format string here must contain the conversion codes %s and %d,
+; in that order, and no other conversion codes. The %s represents
+; the generate statement label; the %d represents the generate parameter value
+; at a particular iteration (this is the position number if the generate parameter
+; is of an enumeration type). Embedded whitespace is allowed (but discouraged);
+; leading and trailing whitespace is ignored.
+; Application of the format must result in a unique region name over all
+; loop iterations for a particular immediately enclosing scope so that name
+; lookup can function properly. The default is %s__%d.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is 1 (compressed).
+; CheckpointCompressMode = 0
+
+; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper.
+; Use custom gcc compiler located at this path rather than the default path.
+; The path should point directly at a compiler executable.
+; DpiCppPath = <your-gcc-installation>/bin/gcc
+
+; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls.
+; The term "out-of-the-blue" refers to SystemVerilog export function calls
+; made from C functions that don't have the proper context setup
+; (as is the case when running under "DPI-C" import functions).
+; When this is enabled, one can call a DPI export function
+; (but not task) from any C code.
+; the setting of this variable can be one of the following values:
+; 0 : dpioutoftheblue call is disabled (default)
+; 1 : dpioutoftheblue call is enabled, but export call debug support is not available.
+; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available.
+; DpiOutOfTheBlue = 1
+
+; Specify whether continuous assignments are run before other normal priority
+; processes scheduled in the same iteration. This event ordering minimizes race
+; differences between optimized and non-optimized designs, and is the default
+; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set
+; ImmediateContinuousAssign to 0.
+; The default is 1 (enabled).
+; ImmediateContinuousAssign = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+
+; Which default VPI object model should the tool conform to?
+; The 1364 modes are Verilog-only, for backwards compatibility with older
+; libraries, and SystemVerilog objects are not available in these modes.
+;
+; In the absence of a user-specified default, the tool default is the
+; latest available LRM behavior.
+; Options for PliCompatDefault are:
+; VPI_COMPATIBILITY_VERSION_1364v1995
+; VPI_COMPATIBILITY_VERSION_1364v2001
+; VPI_COMPATIBILITY_VERSION_1364v2005
+; VPI_COMPATIBILITY_VERSION_1800v2005
+; VPI_COMPATIBILITY_VERSION_1800v2008
+;
+; Synonyms for each string are also recognized:
+; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995)
+; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001)
+; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005)
+; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005)
+; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008)
+
+
+; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005
+
+; Specify default options for the restart command. Options can be one
+; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
+; DefaultRestartOptions = -force
+
+; Turn on (1) or off (0) WLF file compression.
+; The default is 1 (compress WLF file).
+; WLFCompress = 0
+
+; Specify whether to save all design hierarchy (1) in the WLF file
+; or only regions containing logged signals (0).
+; The default is 0 (save only regions with logged signals).
+; WLFSaveAllRegions = 1
+
+; WLF file time limit. Limit WLF file by time, as closely as possible,
+; to the specified amount of simulation time. When the limit is exceeded
+; the earliest times get truncated from the file.
+; If both time and size limits are specified the most restrictive is used.
+; UserTimeUnits are used if time units are not specified.
+; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
+; WLFTimeLimit = 0
+
+; WLF file size limit. Limit WLF file size, as closely as possible,
+; to the specified number of megabytes. If both time and size limits
+; are specified then the most restrictive is used.
+; The default is 0 (no limit).
+; WLFSizeLimit = 1000
+
+; Specify whether or not a WLF file should be deleted when the
+; simulation ends. A value of 1 will cause the WLF file to be deleted.
+; The default is 0 (do not delete WLF file when simulation ends).
+; WLFDeleteOnQuit = 1
+
+; Specify whether or not a WLF file should be indexed during
+; simulation. If set to 0, the WLF file will not be indexed.
+; The default is 1, indexed the WLF file.
+; WLFIndex = 0
+
+; Specify whether or not a WLF file should be optimized during
+; simulation. If set to 0, the WLF file will not be optimized.
+; The default is 1, optimize the WLF file.
+; WLFOptimize = 0
+
+; Specify the name of the WLF file.
+; The default is vsim.wlf
+; WLFFilename = vsim.wlf
+
+; Specify whether to lock the WLF file using system lockd locking mechanism.
+; Locking the file prevents other invocations of ModelSim/Questa tools from
+; inadvertently overwriting the WLF file.
+; The default is 1, lock the WLF file.
+; WLFFileLock = 0
+
+; Specify the WLF reader cache size limit for each open WLF file.
+; The size is giving in megabytes. A value of 0 turns off the
+; WLF cache.
+; WLFSimCacheSize allows a different cache size to be set for
+; simulation WLF file independent of post-simulation WLF file
+; viewing. If WLFSimCacheSize is not set it defaults to the
+; WLFCacheSize setting.
+; The default WLFCacheSize setting is enabled to 256M per open WLF file.
+; WLFCacheSize = 2000
+; WLFSimCacheSize = 500
+
+; Specify the WLF file event collapse mode.
+; 0 = Preserve all events and event order. (same as -wlfnocollapse)
+; 1 = Only record values of logged objects at the end of a simulator iteration.
+; (same as -wlfcollapsedelta)
+; 2 = Only record values of logged objects at the end of a simulator time step.
+; (same as -wlfcollapsetime)
+; The default is 1.
+; WLFCollapseMode = 0
+
+; Specify whether WLF file logging can use threads on multi-processor machines
+; if 0, no threads will be used, if 1, threads will be used if the system has
+; more than one processor
+; WLFUseThreads = 1
+
+; Turn on/off undebuggable SystemC type warnings. Default is on.
+; ShowUndebuggableScTypeWarning = 0
+
+; Turn on/off unassociated SystemC name warnings. Default is off.
+; ShowUnassociatedScNameWarning = 1
+
+; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off.
+; ScShowIeeeDeprecationWarnings = 1
+
+; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off.
+; ScEnableScSignalWriteCheck = 1
+
+; Set SystemC default time unit.
+; Set to fs, ps, ns, us, ms, or sec with optional
+; prefix of 1, 10, or 100. The default is 1 ns.
+; The ScTimeUnit value is honored if it is coarser than Resolution.
+; If ScTimeUnit is finer than Resolution, it is set to the value
+; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns,
+; then the default time unit will be 1 ns. However if Resolution
+; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns.
+ScTimeUnit = ns
+
+; Set SystemC sc_main stack size. The stack size is set as an integer
+; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or
+; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends
+; on the amount of data on the sc_main() stack and the memory required
+; to succesfully execute the longest function call chain of sc_main().
+ScMainStackSize = 10 Mb
+
+; Turn on/off execution of remainder of sc_main upon quitting the current
+; simulation session. If the cumulative length of sc_main() in terms of
+; simulation time units is less than the length of the current simulation
+; run upon quit or restart, sc_main() will be in the middle of execution.
+; This switch gives the option to execute the remainder of sc_main upon
+; quitting simulation. The drawback of not running sc_main till the end
+; is memory leaks for objects created by sc_main. If on, the remainder of
+; sc_main will be executed ignoring all delays. This may cause the simulator
+; to crash if the code in sc_main is dependent on some simulation state.
+; Default is on.
+ScMainFinishOnQuit = 1
+
+; Set the SCV relationship name that will be used to identify phase
+; relations. If the name given to a transactor relation matches this
+; name, the transactions involved will be treated as phase transactions
+ScvPhaseRelationName = mti_phase
+
+; Customize the vsim kernel shutdown behavior at the end of the simulation.
+; Some common causes of the end of simulation are $finish (implicit or explicit),
+; sc_stop(), tf_dofinish(), and assertion failures.
+; This should be set to "ask", "exit", or "stop". The default is "ask".
+; "ask" -- In batch mode, the vsim kernel will abruptly exit.
+; In GUI mode, a dialog box will pop up and ask for user confirmation
+; whether or not to quit the simulation.
+; "stop" -- Cause the simulation to stay loaded in memory. This can make some
+; post-simulation tasks easier.
+; "exit" -- The simulation will abruptly exit without asking for any confirmation.
+; "final" -- Run SystemVerilog final blocks then behave as "stop".
+; Note: This variable can be overridden with the vsim "-onfinish" command line switch.
+OnFinish = ask
+
+; Print pending deferred assertion messages.
+; Deferred assertion messages may be scheduled after the $finish in the same
+; time step. Deferred assertions scheduled to print after the $finish are
+; printed before exiting with severity level NOTE since it's not known whether
+; the assertion is still valid due to being printed in the active region
+; instead of the reactive region where they are normally printed.
+; OnFinishPendingAssert = 1;
+
+; Print "simstats" result at the end of simulation before shutdown.
+; If this is enabled, the simstats result will be printed out before shutdown.
+; The default is off.
+; PrintSimStats = 1
+
+; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
+; AssertFile = assert.log
+
+; Run simulator in assertion debug mode. Default is off.
+; AssertionDebug = 1
+
+; Turn on/off PSL/SVA/VHDL assertion enable. Default is on.
+; AssertionEnable = 0
+
+; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1.
+; Any positive integer, -1 for infinity.
+; AssertionLimit = 1
+
+; Turn on/off PSL concurrent assertion pass log. Default is off.
+; The flag does not affect SVA
+; AssertionPassLog = 1
+
+; Turn on/off PSL concurrent assertion fail log. Default is on.
+; The flag does not affect SVA
+; AssertionFailLog = 0
+
+; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on.
+; AssertionFailLocalVarLog = 0
+
+; Set action type for PSL/SVA concurrent assertion fail action. Default is continue.
+; 0 = Continue 1 = Break 2 = Exit
+; AssertionFailAction = 1
+
+; Enable the active thread monitor in the waveform display when assertion debug is enabled.
+; AssertionActiveThreadMonitor = 1
+
+; Control how many waveform rows will be used for displaying the active threads. Default is 5.
+; AssertionActiveThreadMonitorLimit = 5
+
+; Assertion thread limit after which assertion would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for an assertion go
+; beyond this limit, the assertion would be either switched off or killed. This
+; limit applies to only assert directives.
+;AssertionThreadLimit = -1
+
+; Action to be taken once the assertion thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only assert directives.
+;AssertionThreadLimitAction = kill
+
+; Cover thread limit after which cover would be killed/switched off.
+; The default is -1 (unlimited). If the number of threads for a cover go
+; beyond this limit, the cover would be either switched off or killed. This
+; limit applies to only cover directives.
+;CoverThreadLimit = -1
+
+; Action to be taken once the cover thread limit is reached. Default
+; is kill. It can have a value of off or kill. In case of kill, all the existing
+; threads are terminated and no new attempts are started. In case of off, the
+; existing attempts keep on evaluating but no new attempts are started. This
+; variable applies to only cover directives.
+;CoverThreadLimitAction = kill
+
+
+; By default immediate assertions do not participate in Assertion Coverage calculations
+; unless they are executed. This switch causes all immediate assertions in the design
+; to participate in Assertion Coverage calculations, whether attempted or not.
+; UnattemptedImmediateAssertions = 0
+
+
+
+; As per strict 1850-2005 PSL LRM, an always property can either pass
+; or fail. However, by default, Questa reports multiple passes and
+; multiple fails on top always/never property (always/never operator
+; is the top operator under Verification Directive). The reason
+; being that Questa reports passes and fails on per attempt of the
+; top always/never property. Use the following flag to instruct
+; Questa to strictly follow LRM. With this flag, all assert/never
+; directives will start an attempt once at start of simulation.
+; The attempt can either fail, match or match vacuously.
+; For e.g. if always is the top operator under assert, the always will
+; keep on checking the property at every clock. If the property under
+; always fails, the directive will be considered failed and no more
+; checking will be done for that directive. A top always property,
+; if it does not fail, will show a pass at end of simulation.
+; The default value is '0' (i.e. zero is off). For example:
+; PslOneAttempt = 1
+
+; Specify the number of clock ticks to represent infinite clock ticks.
+; This affects eventually!, until! and until_!. If at End of Simulation
+; (EOS) an active strong-property has not clocked this number of
+; clock ticks then neither pass or fail (vacuous match) is returned
+; else respective fail/pass is returned. The default value is '0' (zero)
+; which effectively does not check for clock tick condition. For example:
+; PslInfinityThreshold = 5000
+
+; Control how many thread start times will be preserved for ATV viewing for a given assertion
+; instance. Default is -1 (ALL).
+; ATVStartTimeKeepCount = -1
+
+; Turn on/off code coverage
+; CodeCoverage = 0
+
+; Count all code coverage condition and expression truth table rows that match.
+; CoverCountAll = 1
+
+; Turn off automatic inclusion of VHDL integers in toggle coverage. Default
+; is to include them.
+; ToggleNoIntegers = 1
+
+; Set the maximum number of values that are collected for toggle coverage of
+; VHDL integers. Default is 100;
+; ToggleMaxIntValues = 100
+
+; Set the maximum number of values that are collected for toggle coverage of
+; Verilog real. Default is 100;
+; ToggleMaxRealValues = 100
+
+; Turn on automatic inclusion of Verilog integers in toggle coverage, except
+; for enumeration types. Default is to include them.
+; ToggleVlogIntegers = 0
+
+; Turn on automatic inclusion of Verilog real type in toggle coverage, except
+; for shortreal types. Default is to not include them.
+; ToggleVlogReal = 1
+
+; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays
+; and VHDL arrays-of-arrays in toggle coverage.
+; Default is to not include them.
+; ToggleFixedSizeArray = 1
+
+; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays,
+; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage.
+; This leads to a longer simulation time with bigger arrays covered with toggle coverage.
+; Default is 1024.
+; ToggleMaxFixedSizeArray = 1024
+
+; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized
+; one-dimensional packed vectors for toggle coverage. Default is 0.
+; TogglePackedAsVec = 0
+
+; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for
+; toggle coverage. Default is 0.
+; ToggleVlogEnumBits = 0
+
+; Limit the widths of registers automatically tracked for toggle coverage. Default is 128.
+; For unlimited width, set to 0.
+; ToggleWidthLimit = 128
+
+; Limit the counts that are tracked for toggle coverage. When all edges for a bit have
+; reached this count, further activity on the bit is ignored. Default is 1.
+; For unlimited counts, set to 0.
+; ToggleCountLimit = 1
+
+; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3.
+; Following is the toggle coverage calculation criteria based on extended toggle mode:
+; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z').
+; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'.
+; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions.
+; ExtendedToggleMode = 3
+
+; Turn on/off all PSL/SVA cover directive enables. Default is on.
+; CoverEnable = 0
+
+; Turn on/off PSL/SVA cover log. Default is off "0".
+; CoverLog = 1
+
+; Set "at_least" value for all PSL/SVA cover directives. Default is 1.
+; CoverAtLeast = 2
+
+; Set "limit" value for all PSL/SVA cover directives. Default is -1.
+; Any positive integer, -1 for infinity.
+; CoverLimit = 1
+
+; Specify the coverage database filename.
+; Default is "" (i.e. database is NOT automatically saved on close).
+; UCDBFilename = vsim.ucdb
+
+; Specify the maximum limit for the number of Cross (bin) products reported
+; in XML and UCDB report against a Cross. A warning is issued if the limit
+; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this
+; setting.
+; MaxReportRhsSVCrossProducts = 1000
+
+; Specify the override for the "auto_bin_max" option for the Covergroups.
+; If not specified then value from Covergroup "option" is used.
+; SVCoverpointAutoBinMax = 64
+
+; Specify the override for the value of "cross_num_print_missing"
+; option for the Cross in Covergroups. If not specified then value
+; specified in the "option.cross_num_print_missing" is used. This
+; is a runtime option. NOTE: This overrides any "cross_num_print_missing"
+; value specified by user in source file and any SVCrossNumPrintMissingDefault
+; specified in modelsim.ini.
+; SVCrossNumPrintMissing = 0
+
+; Specify whether to use the value of "cross_num_print_missing"
+; option in report and GUI for the Cross in Covergroups. If not specified then
+; cross_num_print_missing is ignored for creating reports and displaying
+; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing".
+; UseSVCrossNumPrintMissing = 0
+
+; Specify the override for the value of "strobe" option for the
+; Covergroup Type. If not specified then value in "type_option.strobe"
+; will be used. This is runtime option which forces "strobe" to
+; user specified value and supersedes user specified values in the
+; SystemVerilog Code. NOTE: This also overrides the compile time
+; default value override specified using "SVCovergroupStrobeDefault"
+; SVCovergroupStrobe = 0
+
+; Override for explicit assignments in source code to "option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault".
+; SVCovergroupGoal = 100
+
+; Override for explicit assignments in source code to "type_option.goal" of
+; SystemVerilog covergroup, coverpoint, and cross. It also overrides the
+; default value of "type_option.goal" (defined to be 100 in the SystemVerilog
+; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault".
+; SVCovergroupTypeGoal = 100
+
+; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage()
+; builtin functions, and report. This setting changes the default values of
+; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3
+; behavior if explicit assignments are not made on option.get_inst_coverage and
+; type_option.merge_instances by the user. There are two vsim command line
+; options, -cvg63 and -nocvg63 to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SVCovergroup63Compatibility = 0
+
+; Enforce the 6.5 default behavior of covergroup get_coverage() builtin
+; functions, GUI, and report. This setting changes the default values of
+; type_option.merge_instances to ensure the 6.5 default behavior if explicit
+; assignments are not made on type_option.merge_instances by the user.
+; There are two vsim command line options, -cvgmergeinstances and
+; -nocvgmergeinstances to override this setting from vsim command line.
+; The default value of this variable from release 6.6 onwards is 0. This default
+; drives compliance with the clarified behavior in the IEEE 1800-2009 standard.
+; SvCovergroupMergeInstancesDefault = 1
+
+; Enable or disable generation of more detailed information about the sampling
+; of covergroup, cross, and coverpoints. It provides the details of the number
+; of times the covergroup instance and type were sampled, as well as details
+; about why covergroup, cross and coverpoint were not covered. A non-zero value
+; is to enable this feature. 0 is to disable this feature. Default is 0
+; SVCovergroupSampleInfo = 0
+
+; Specify the maximum number of Coverpoint bins in whole design for
+; all Covergroups.
+; MaxSVCoverpointBinsDesign = 2147483648
+
+; Specify maximum number of Coverpoint bins in any instance of a Covergroup
+; MaxSVCoverpointBinsInst = 2147483648
+
+; Specify the maximum number of Cross bins in whole design for
+; all Covergroups.
+; MaxSVCrossBinsDesign = 2147483648
+
+; Specify maximum number of Cross bins in any instance of a Covergroup
+; MaxSVCrossBinsInst = 2147483648
+
+; Set weight for all PSL/SVA cover directives. Default is 1.
+; CoverWeight = 2
+
+; Check vsim plusargs. Default is 0 (off).
+; 0 = Don't check plusargs
+; 1 = Warning on unrecognized plusarg
+; 2 = Error and exit on unrecognized plusarg
+; CheckPlusargs = 1
+
+; Load the specified shared objects with the RTLD_GLOBAL flag.
+; This gives global visibility to all symbols in the shared objects,
+; meaning that subsequently loaded shared objects can bind to symbols
+; in the global shared objects. The list of shared objects should
+; be whitespace delimited. This option is not supported on the
+; Windows or AIX platforms.
+; GlobalSharedObjectList = example1.so example2.so example3.so
+
+; Run the 0in tools from within the simulator.
+; Default is off.
+; ZeroIn = 1
+
+; Set the options to be passed to the 0in runtime tool.
+; Default value set to "".
+; ZeroInOptions = ""
+
+; Initial seed for the random number generator of the root thread (SystemVerilog).
+; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch.
+; The default value is 0.
+; Sv_Seed = 0
+
+; Specify the solver "engine" that vsim will select for constrained random
+; generation.
+; Valid values are:
+; "auto" - automatically select the best engine for the current
+; constraint scenario
+; "bdd" - evaluate all constraint scenarios using the BDD solver engine
+; "act" - evaluate all constraint scenarios using the ACT solver engine
+; While the BDD solver engine is generally efficient with constraint scenarios
+; involving bitwise logical relationships, the ACT solver engine can exhibit
+; superior performance with constraint scenarios involving large numbers of
+; random variables related via arithmetic operators (+, *, etc).
+; NOTE: At this time, the "auto" setting is equivalent to the "bdd" setting.
+; NOTE: This variable can be overridden with the vsim "-solveengine" command
+; line switch.
+; The default value is "auto".
+; SolveEngine = auto
+
+; Specify if the solver should attempt to ignore overflow/underflow semantics
+; for arithmetic constraints (multiply, addition, subtraction) in order to
+; improve performance. The "solveignoreoverflow" attribute can be specified on
+; a per-call basis to randomize() to override this setting.
+; The default value is 0 (overflow/underflow is not ignored). Set to 1 to
+; ignore overflow/underflow.
+; SolveIgnoreOverflow = 0
+
+; Specifies the maximum size that a dynamic array may be resized to by the
+; solver. If the solver attempts to resize a dynamic array to a size greater
+; than the specified limit, the solver will abort with an error.
+; The default value is 2000. A value of 0 indicates no limit.
+; SolveArrayResizeMax = 2000
+
+; Error message severity when randomize() failure is detected (SystemVerilog).
+; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+; The default is 0 (no error).
+; SolveFailSeverity = 0
+
+; Enable/disable debug information for randomize() failures.
+; NOTE: This variable can be overridden with the vsim "-solvefaildbug" command
+; line switch.
+; The default is 0 (disabled). Set to 1 to enable.
+; SolveFailDebug = 0
+
+; Specify the maximum size of the solution graph generated by the BDD solver.
+; This value can be used to force the BDD solver to abort the evaluation of a
+; complex constraint scenario that cannot be evaluated with finite memory.
+; This value is specified in 1000s of nodes.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxSize = 10000
+
+; Specify the maximum number of evaluations that may be performed on the
+; solution graph by the BDD solver. This value can be used to force the BDD
+; solver to abort the evaluation of a complex constraint scenario that cannot
+; be evaluated in finite time. This value is specified in 10000s of evaluations.
+; The default value is 10000. A value of 0 indicates no limit.
+; SolveGraphMaxEval = 10000
+
+; Specify the maximum number of tests that the ACT solver may evaluate before
+; abandoning an attempt to solve a particular constraint scenario.
+; The default value is 1000000. A value of 0 indicates no limit.
+; SolveACTMaxTests = 1000000
+
+; Specify the number of times the ACT solver will retry to evaluate a constraint
+; scenario that fails due to the SolveACTMaxTests threshold.
+; The default value is 0 (no retry).
+; SolveACTRetryCount = 0
+
+; SolveSpeculateLevel controls whether or not the solver performs speculation
+; during the evaluation of a constraint scenario.
+; Speculation is an attempt to partition complex constraint scenarios by
+; choosing a 'speculation' subset of the variables and constraints. This
+; 'speculation' set is solved independently of the remaining constraints.
+; The solver then attempts to solve the remaining variables and constraints
+; (the 'dependent' set). If this attempt fails, the solver backs up and
+; re-solves the 'speculation' set, then retries the 'dependent' set.
+; Valid values are:
+; 0 - no speculation
+; 1 - enable speculation that maintains LRM specified distribution
+; 2 - enable other speculation - may yield non-LRM distribution
+; Currently, distribution constraints and solve-before constraints are
+; used in selecting the 'speculation' sets for speculation level 1. Non-LRM
+; compliant speculation includes random variables in condition expressions.
+; The default value is 0.
+; SolveSpeculateLevel = 0
+
+; By default, when speculation is enabled, the solver first tries to solve a
+; constraint scenario *without* speculation. If the solver fails to evaluate
+; the constraint scenario (due to time/memory limits) then the solver will
+; re-evaluate the constraint scenario with speculation. If SolveSpeculateFirst
+; is set to 1, the solver will skip the initial non-speculative attempt to
+; evaluate the constraint scenario. (Only applies when SolveSpeculateLevel is
+; non-zero)
+; The default value is 0.
+; SolveSpeculateFirst = 0
+
+; Specify the maximum bit width of a variable in a conditional expression that
+; may be considered as the basis for "conditional" speculation. (Only applies
+; when SolveSpeculateLevel=2)
+; The default value is 6.
+; SolveSpeculateMaxCondWidth = 6
+
+; Specify the maximum number of attempts to solve a speculative set of random
+; variables and constraints. Exceeding this limit will cause the solver to
+; abandon the current speculative set. (Only applies when SolveSpeculateLevel
+; is non-zero)
+; The default value is 100.
+; SolveSpeculateMaxIterations = 100
+
+; Specifies whether to attempt speculation on solve-before constraints or
+; distribution constraints first. A value of 0 specifies that solve-before
+; constraints are attempted first as the basis for speculative randomization.
+; A value of 1 specifies that distribution constraints are attempted first
+; as the basis for speculative randomization.
+; The default value is 0.
+; SolveSpeculateDistFirst = 0
+
+; If the non-speculative BDD solver fails to evaluate a constraint scenario
+; (due to time/memory limits) then the solver can be instructed to automatically
+; re-evaluate the constraint scenario with the ACT solver engine. Set
+; SolveACTbeforeSpeculate to 1 to enable this feature.
+; The default value is 0 (do not re-evaluate with the ACT solver).
+; SolveACTbeforeSpeculate = 0
+
+; Use SolveFlags to specify options that will guide the behavior of the
+; constraint solver. These options may improve the performance of the
+; constraint solver for some testcases, and decrease the performance of the
+; constraint solver for others.
+; Valid flags are:
+; i = disable bit interleaving for >, >=, <, <= constraints (BDD engine)
+; n = disable bit interleaving for all constraints (BDD engine)
+; r = reverse bit interleaving (BDD engine)
+; The default value is "" (no options).
+; SolveFlags =
+
+; Specify random sequence compatiblity with a prior letter release. This
+; option is used to get the same random sequences during simulation as
+; as a prior letter release. Only prior letter releases (of the current
+; number release) are allowed.
+; NOTE: Only those random sequence changes due to solver optimizations are
+; reverted by this variable. Random sequence changes due to solver bugfixes
+; cannot be un-done.
+; NOTE: This variable can be overridden with the vsim "-solverev" command
+; line switch.
+; Default value set to "" (no compatibility).
+; SolveRev =
+
+; Environment variable expansion of command line arguments has been depricated
+; in favor shell level expansion. Universal environment variable expansion
+; inside -f files is support and continued support for MGC Location Maps provide
+; alternative methods for handling flexible pathnames.
+; The following line may be uncommented and the value set to 1 to re-enable this
+; deprecated behavior. The default value is 0.
+; DeprecatedEnvironmentVariableExpansion = 0
+
+; Turn on/off collapsing of bus ports in VCD dumpports output
+DumpportsCollapse = 1
+
+; Location of Multi-Level Verification Component (MVC) installation.
+; The default location is the product installation directory.
+; MvcHome = $MODEL_TECH/...
+
+; Initialize SystemVerilog enums using the base type's default value
+; instead of the leftmost value.
+; EnumBaseInit = 1
+
+[lmc]
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software
+libsm = $MODEL_TECH/libsm.sl
+; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libsm = $MODEL_TECH/libsm.dll
+; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700)
+; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl
+; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000)
+; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o
+; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris)
+; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Windows NT)
+; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll
+; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so
+; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux)
+; libswift = $LMC_HOME/lib/linux.lib/libswift.so
+
+; The simulator's interface to Logic Modeling's hardware modeler SFI software
+libhm = $MODEL_TECH/libhm.sl
+; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT)
+; libhm = $MODEL_TECH/libhm.dll
+; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700)
+; libsfi = <sfi_dir>/lib/hp700/libsfi.sl
+; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000)
+; libsfi = <sfi_dir>/lib/rs6000/libsfi.a
+; Logic Modeling's hardware modeler SFI software (Sun4 Solaris)
+; libsfi = <sfi_dir>/lib/sun4.solaris/libsfi.so
+; Logic Modeling's hardware modeler SFI software (Windows NT)
+; libsfi = <sfi_dir>/lib/pcnt/lm_sfi.dll
+; Logic Modeling's hardware modeler SFI software (Linux)
+; libsfi = <sfi_dir>/lib/linux/libsfi.so
+
+[msg_system]
+; Change a message severity or suppress a message.
+; The format is: <msg directive> = <msg number>[,<msg number>...]
+; suppress can be used to achieve +nowarn<CODE> functionality
+; The format is: suppress = <CODE>,<msg number>,[<CODE>,<msg number>,...]
+; Examples:
+; note = 3009
+; warning = 3033
+; error = 3010,3016
+; fatal = 3016,3033
+; suppress = 3009,3016,3043
+; suppress = 3009,CNNODP,3043,TFMPC
+; suppress = 8683,8684
+; The command verror <msg number> can be used to get the complete
+; description of a message.
+
+; Control transcripting of Verilog display system task messages and
+; PLI/FLI print function call messages. The system tasks include
+; $display[bho], $strobe[bho], Smonitor{bho], and $write[bho]. They
+; also include the analogous file I/O tasks that write to STDOUT
+; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf,
+; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default
+; is to have messages appear only in the transcript. The other
+; settings are to send messages to the wlf file only (messages that
+; are recorded in the wlf file can be viewed in the MsgViewer) or
+; to both the transcript and the wlf file. The valid values are
+; tran {transcript only (default)}
+; wlf {wlf file only}
+; both {transcript and wlf file}
+; displaymsgmode = tran
+
+; Control transcripting of elaboration/runtime messages not
+; addressed by the displaymsgmode setting. The default is to
+; have messages appear in the transcript and recorded in the wlf
+; file (messages that are recorded in the wlf file can be viewed
+; in the MsgViewer). The other settings are to send messages
+; only to the transcript or only to the wlf file. The valid
+; values are
+; both {default}
+; tran {transcript only}
+; wlf {wlf file only}
+; msgmode = both
+[Project]
+; Warning -- Do not edit the project properties directly.
+; Property names are dynamic in nature and property
+; values have special syntax. Changing property data directly
+; can result in a corrupt MPF file. All project properties
+; can be modified through project window dialogs.
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 139
+Project_File_0 = /home/marek/trbv2/up_down_counter.vhd
+Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249045055 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 117 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_1 = /home/marek/trbnet/lattice/ecp2m/trb_net_fifo_16bit_bram_dualport.vhd
+Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1228404858 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 75 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_2 = /home/marek/trbnet/basics/ram.vhd
+Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 59 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_3 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_19x16_obuf.vhd
+Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277134650 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 81 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_4 = /home/marek/trbnet/basics/ram_16x8_dp.vhd
+Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 60 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_5 = /home/marek/ctsaddon/simulation/cts_simple_data_transport.vhd
+Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 40 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_6 = /home/marek/ctsaddon/simulation/cts_readout_data_buff.vhd
+Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_7 = /home/marek/trbnet/special/spi_master.vhd
+Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1286546951 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 113 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_8 = /home/marek/trbnet/trb_net_priority_arbiter.vhd
+Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 95 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_9 = /home/marek/ctsaddon/simulation/cts_cal_screset_gen.vhd
+Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_10 = /home/marek/ctsaddon/simulation/ram_register.vhd
+Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_11 = /home/marek/trbnet/lattice/ecp2m/trb_net_clock_generator.vhd
+Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 74 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_12 = /home/marek/trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd
+Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249570868 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 68 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_13 = /home/marek/trbnet/trb_net_sbuf6.vhd
+Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 98 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_14 = /home/marek/ctsaddon/simulation/cts_fpga2_reg_interface.vhd
+Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 36 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_15 = /home/marek/trbnet/special/handler_trigger_and_data.vhd
+Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1296638933 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 111 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_16 = /home/marek/trbnet/trb_net16_term.vhd
+Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1237891031 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 55 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_17 = /home/marek/trbnet/trb_net_dummy_fifo.vhd
+Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 93 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_18 = /home/marek/trbnet/trb_net_sbuf.vhd
+Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 97 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_19 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd
+Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 89 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_20 = /home/marek/trbnet/lattice/ecp2m/dll_in100_out100.vhd
+Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292267 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 67 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_21 = /home/marek/ctsaddon/simulation/cts_fpga1_to_fpga2.vhd
+Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 33 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_22 = /home/marek/trbnet/trb_net16_endpoint_hades_full_handler.vhd
+Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 101 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_23 = /home/marek/ctsaddon/simulation/pll_in200_out40.vhd
+Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 16 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_24 = /home/marek/ctsaddon/simulation/ddr2_16inputs.vhd
+Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_25 = /home/marek/ctsaddon/simulation/cts_width_rom.vhd
+Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_26 = /home/marek/trbnet/special/handler_lvl1.vhd
+Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014417 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 110 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_27 = /home/marek/trbnet/trb_net16_sbuf.vhd
+Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295625509 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 108 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_28 = /home/marek/trbv2/f_divider.vhd
+Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1259846036 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 116 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_29 = /home/marek/ctsaddon/simulation/scm_fifo_16bit_to_32bit.vhd
+Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 23 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_30 = /home/marek/trbnet/trb_net16_obuf_nodata.vhd
+Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248956644 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 54 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_31 = /home/marek/ctsaddon/simulation/cts_fpga2_to_fpga1.vhd
+Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 37 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_32 = /home/marek/ctsaddon/simulation/cts_fpga2.vhd
+Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 125 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_33 = /home/marek/ctsaddon/simulation/cts_eb_ip_switch.vhd
+Project_File_P_33 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 32 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_34 = /home/marek/ctsaddon/simulation/cts_witdh_rom_simulation.vhd
+Project_File_P_34 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321880898 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 133 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_35 = /home/marek/trbnet/special/spi_databus_memory.vhd
+Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1268245488 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 112 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_36 = /home/marek/trbnet/special/spi_slim.vhd
+Project_File_P_36 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875807 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 131 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_37 = /home/marek/trbnet/trb_net16_term_buf.vhd
+Project_File_P_37 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 56 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_38 = /home/marek/trbnet/basics/pulse_stretch.vhd
+Project_File_P_38 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277977616 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 129 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_39 = /home/marek/trbnet/trb_net16_iobuf.vhd
+Project_File_P_39 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 104 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_40 = /home/marek/trbnet/trb_net16_regIO.vhd
+Project_File_P_40 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295344067 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 106 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_41 = /home/marek/trbnet/trb_net16_ibuf.vhd
+Project_File_P_41 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 102 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_42 = /home/marek/ctsaddon/simulation/trb_net16_med_ecp_sfp_gbe.vhd
+Project_File_P_42 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 118 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_43 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd
+Project_File_P_43 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 79 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_44 = /home/marek/ctsaddon/simulation/cts_beam_structure.vhd
+Project_File_P_44 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321978606 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 138 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_45 = /home/marek/trbnet/trb_net16_ipudata.vhd
+Project_File_P_45 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760358 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 53 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_46 = /home/marek/ctsaddon/simulation/cts_fpga2_trig_gen.vhd
+Project_File_P_46 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 38 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_47 = /home/marek/trbnet/trb_net_CRC.vhd
+Project_File_P_47 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1235046634 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 92 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_48 = /home/marek/ctsaddon/simulation/ddr2_busses.vhd
+Project_File_P_48 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 135 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_49 = /home/marek/trbnet/trb_net16_io_multiplexer.vhd
+Project_File_P_49 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 103 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_50 = /home/marek/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd
+Project_File_P_50 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 72 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_51 = /home/marek/ctsaddon/simulation/delay_fifo.vhd
+Project_File_P_51 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 12 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_52 = /home/marek/ctsaddon/simulation/ddr2_3out_clkdiv.vhd
+Project_File_P_52 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_53 = /home/marek/ctsaddon/simulation/cts_polarity_check.vhd
+Project_File_P_53 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 39 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_54 = /home/marek/ctsaddon/simulation/cts_delay_large.vhd
+Project_File_P_54 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 25 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_55 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd
+Project_File_P_55 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1275387240 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 78 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_56 = /home/marek/trbnet/trb_net16_api_base.vhd
+Project_File_P_56 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 99 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_57 = /home/marek/ctsaddon/simulation/pll_in200_out400.vhd
+Project_File_P_57 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 17 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_58 = /home/marek/ctsaddon/simulation/cts_fpga2_reg_mem.vhd
+Project_File_P_58 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 41 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_59 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd
+Project_File_P_59 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 76 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_60 = /home/marek/trbnet/trb_net16_endpoint_hades_cts.vhd
+Project_File_P_60 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875836 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 132 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_61 = /home/marek/ctsaddon/simulation/cts_readout.vhd
+Project_File_P_61 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_62 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd
+Project_File_P_62 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248958666 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 124 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_63 = /home/marek/trbnet/trb_net16_dummy_fifo.vhd
+Project_File_P_63 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 52 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_64 = /home/marek/trbnet/trb_net_onewire_listener.vhd
+Project_File_P_64 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872784 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 128 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_65 = /home/marek/ctsaddon/simulation/cts_set_width_large.vhd
+Project_File_P_65 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 27 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_66 = /home/marek/trbnet/trb_net_pattern_gen.vhd
+Project_File_P_66 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1214858855 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 94 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_67 = /home/marek/ctsaddon/simulation/ecp2m_lvl2_trigger_buffer_fifo_1kW.vhd
+Project_File_P_67 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 42 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_68 = /home/marek/ctsaddon/simulation/dll_in400_out200.vhd
+Project_File_P_68 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 14 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_69 = /home/marek/ctsaddon/simulation/cts_components.vhd
+Project_File_P_69 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_70 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd
+Project_File_P_70 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760376 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 84 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_71 = /home/marek/trbnet/special/trb_net_reset_handler.vhd
+Project_File_P_71 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280937906 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 66 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_72 = /home/marek/ctsaddon/simulation/fifo_1bit_to_32bit.vhd
+Project_File_P_72 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 43 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_73 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl2.vhd
+Project_File_P_73 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 35 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_74 = /home/marek/ctsaddon/simulation/beam_structure_fifo.vhd
+Project_File_P_74 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 6 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_75 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd
+Project_File_P_75 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 71 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_76 = /home/marek/trbnet/trb_net_onewire.vhd
+Project_File_P_76 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872769 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 127 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_77 = /home/marek/ctsaddon/simulation/fifo_2bit_to_32bit.vhd
+Project_File_P_77 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 44 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_78 = /home/marek/trbv2/etrax_write_read_tb.vhd
+Project_File_P_78 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321461742 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 120 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_79 = /home/marek/trbnet/basics/ram_dp.vhd
+Project_File_P_79 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 62 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_80 = /home/marek/ctsaddon/simulation/scm_fifo_1bit_to_32bit.vhd
+Project_File_P_80 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 19 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_81 = /home/marek/ctsaddon/cts_fpga1_test.vhd
+Project_File_P_81 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321889254 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 119 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_82 = /home/marek/trbnet/trb_net16_regio_bus_handler.vhd
+Project_File_P_82 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 107 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_83 = /home/marek/ctsaddon/simulation/scm_fifo_2bit_to_32bit.vhd
+Project_File_P_83 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 20 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_84 = /home/marek/ctsaddon/simulation/fifo_4bit_to_32bit.vhd
+Project_File_P_84 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 45 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_85 = /home/marek/ctsaddon/simulation/ddr_lvl1_trigger.vhd
+Project_File_P_85 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 28 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_86 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x8k_oreg.vhd
+Project_File_P_86 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760377 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 85 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_87 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd
+Project_File_P_87 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249891632 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 123 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_88 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd
+Project_File_P_88 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1282206842 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 69 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_89 = /home/marek/trbnet/trb_net_sbuf5.vhd
+Project_File_P_89 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 49 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_90 = /home/marek/ctsaddon/simulation/scm_fifo_4bit_to_32bit.vhd
+Project_File_P_90 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 21 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_91 = /home/marek/trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd
+Project_File_P_91 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1267800223 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 115 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_92 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x256_oreg.vhd
+Project_File_P_92 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 88 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_93 = /home/marek/trbnet/special/handler_ipu.vhd
+Project_File_P_93 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304089906 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 109 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_94 = /home/marek/ctsaddon/simulation/version.vhd
+Project_File_P_94 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321458601 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_95 = /home/marek/ctsaddon/simulation/fifo16bit_synch.vhd
+Project_File_P_95 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_96 = /home/marek/ctsaddon/simulation/fifo_8bit_to_32bit.vhd
+Project_File_P_96 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 46 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_97 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_8b_16b_dualport.vhd
+Project_File_P_97 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1278661530 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 70 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_98 = /home/marek/ctsaddon/simulation/cts_fpga1_test_set_width.vhd
+Project_File_P_98 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321871053 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 126 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_99 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd
+Project_File_P_99 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760373 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 87 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_100 = /home/marek/trbnet/trb_net_priority_encoder.vhd
+Project_File_P_100 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1203091968 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 96 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_101 = /home/marek/ctsaddon/simulation/scm_fifo_8bit_to_32bit.vhd
+Project_File_P_101 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 22 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_102 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_lvl2_fifo.vhd
+Project_File_P_102 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454411 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 48 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_103 = /home/marek/ctsaddon/simulation/cts_downscale.vhd
+Project_File_P_103 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 31 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_104 = /home/marek/trbnet/trb_net16_obuf.vhd
+Project_File_P_104 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1302529528 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 105 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_105 = /home/marek/trbnet/trb_net16_term_ibuf.vhd
+Project_File_P_105 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 57 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_106 = /home/marek/ctsaddon/simulation/cts_align_signals.vhd
+Project_File_P_106 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 30 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_107 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd
+Project_File_P_107 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 82 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_108 = /home/marek/ctsaddon/simulation/cts_fpga1_tb.vhd
+Project_File_P_108 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977291 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 136 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_109 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd
+Project_File_P_109 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 77 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_110 = /home/marek/trbnet/basics/ram_16x16_dp.vhd
+Project_File_P_110 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1291756328 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 61 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_111 = /home/marek/ctsaddon/simulation/etrax_reg_mem.vhd
+Project_File_P_111 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 4 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_112 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_data_downscale.vhd
+Project_File_P_112 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 34 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_113 = /home/marek/ctsaddon/simulation/trb_net16_lsm_sfp.vhd
+Project_File_P_113 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 90 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_114 = /home/marek/ctsaddon/simulation/dll_edge.vhd
+Project_File_P_114 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 13 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_115 = /home/marek/ctsaddon/simulation/cts_fpga1.vhd
+Project_File_P_115 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321978014 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 1 cover_noshort 0 compile_to work compile_order 137 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_116 = /home/marek/trbnet/basics/signal_sync.vhd
+Project_File_P_116 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1253527273 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 65 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_117 = /home/marek/ctsaddon/simulation/multiplicity.vhd
+Project_File_P_117 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 29 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_118 = /home/marek/trbnet/basics/ram_dp_rw.vhd
+Project_File_P_118 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 63 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_119 = /home/marek/ctsaddon/simulation/ddr2_12out_clkdiv.vhd
+Project_File_P_119 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_120 = /home/marek/ctsaddon/simulation/cts_trigger_logic.vhd
+Project_File_P_120 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 3 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_121 = /home/marek/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd
+Project_File_P_121 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 73 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_122 = /home/marek/trbnet/trb_net16_trigger.vhd
+Project_File_P_122 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 58 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_123 = /home/marek/ctsaddon/simulation/trb_net_components.vhd
+Project_File_P_123 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 91 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_124 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd
+Project_File_P_124 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600671 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 122 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_125 = /home/marek/trbnet/lattice/ecp2m/pll_in100_out100.vhd
+Project_File_P_125 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 121 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_126 = /home/marek/trbnet/trb_net16_endpoint_hades_full.vhd
+Project_File_P_126 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 100 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_127 = /home/marek/ctsaddon/simulation/cts_one_clock.vhd
+Project_File_P_127 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 26 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_128 = /home/marek/ctsaddon/simulation/cts_delay.vhd
+Project_File_P_128 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 24 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_129 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd
+Project_File_P_129 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1271868444 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 114 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_130 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd
+Project_File_P_130 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 80 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_131 = /home/marek/trbnet/special/handler_data.vhd
+Project_File_P_131 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304328663 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 130 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_132 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd
+Project_File_P_132 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760366 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 86 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_133 = /home/marek/trbnet/basics/rom_16x8.vhd
+Project_File_P_133 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 64 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_134 = /home/marek/trbnet/trb_net_std.vhd
+Project_File_P_134 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 50 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_135 = /home/marek/ctsaddon/simulation/cts_set_width.vhd
+Project_File_P_135 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321977967 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 134 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_136 = /home/marek/trbnet/trb_net16_addresses.vhd
+Project_File_P_136 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1266500256 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 51 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_137 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd
+Project_File_P_137 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 83 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_File_138 = /home/marek/ctsaddon/simulation/fifo_16bit_to_32bit.vhd
+Project_File_P_138 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 47 dont_compile 0 cover_nosub 0 vhdl_use93 2002
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ProjectStatusDelay = 5000
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick =
+SYSTEMVERILOG_DoubleClick = Edit
+SYSTEMVERILOG_CustomDoubleClick =
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick =
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick =
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick =
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick =
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick =
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick =
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick =
+XML_DoubleClick = Edit
+XML_CustomDoubleClick =
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick =
+UCDB_DoubleClick = Edit
+UCDB_CustomDoubleClick =
+PROJECT_DoubleClick = Edit
+PROJECT_CustomDoubleClick =
+Project_Major_Version = 6
+Project_Minor_Version = 6
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.all;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+
+entity cts_trigger_logic is
+ generic (
+ TRIGGER_INPUTS_NUMBER : natural;
+ TRIGGER_OUTPUTS_NUMBER : natural;
+ CTS_NUMBER_IPU_DATA : natural;
+ SCALERS_NUMBER : natural;
+ VECTOR_WIDTH : natural;
+ CTS_MODE : natural;
+ RATE_MARKERS_NUMBER : natural
+
+ );
+ port (
+ CLK : in std_logic;
+ HIGH_FREQ_CLK : in std_logic;
+ CLK_100 : in std_logic;
+ RESET : in std_logic;
+ EMERGENCY_STOP : in std_logic;
+ TRIGGER_IN : in std_logic_vector(TRIGGER_INPUTS_NUMBER*4-1 downto 0);
+ INPUT_ENABLE_IN : in std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ DOWNSCALE_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
+ DELAY_TRIGGER_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER)-1) downto 0);
+ DELAY_LARGE_TRIGGER_REGISTER_IN : in std_logic_vector((8*(12)-1) downto 0);
+ WIDTH_REGISTER_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER+9)-1) downto 0);
+ WIDTH_REGISTER_LARGE_IN : in std_logic_vector((4*(TRIGGER_INPUTS_NUMBER+9)-1) downto 0);
+ TS_GATING_DISABLE_IN : in std_logic_vector((TRIGGER_INPUTS_NUMBER-1) downto 0);
+ TRIGGER_OUT_EN_IN : in std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ MULTIPLEXER_SELECT_IN : in std_logic_vector(27 downto 0);
+ MULTIPLEXER_OUT : out std_logic_vector(7 downto 0);
+ SCALER_OUT : out std_logic_vector(SCALERS_NUMBER*32-1 downto 0); --
+ SCALERS_FINISHED_IN : in std_logic;
+ SEND_SCALERS_OUT : out std_logic;
+ --now only after delay should be also after dsc (in new cts)
+ BEAM_INHIBIT_IN : in std_logic;
+ BEAM_START : in std_logic;
+ NO_TIMING_OUT : out std_logic;
+ --trigger interface to TRBNET
+ LVL1_LOCAL_BUSY_IN : in std_logic;
+ LVL1_TRBNET_BUSY_IN : in std_logic;
+ LVL1_TRIGGER_ACCEPTED_IN : in std_logic; --here
+ LVL1_TRIGGER_CODE_OUT : out std_logic_vector(3 downto 0);
+ LVL1_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL1_RND_NUMBER_OUT : out std_logic_vector(7 downto 0);
+ LVL1_TRIGGER_OUT : out std_logic;
+ LVL1_BUSY_OUT : out std_logic;
+ --trigger interface to IPU channel
+ LVL2_TRBNET_BUSY_IN : in std_logic;
+ LVL2_LOCAL_BUSY_IN : in std_logic;
+ LVL2_TRIGGER_OUT : out std_logic;
+ LVL2_TRIGGER_CODE_OUT : out std_logic_vector(3 downto 0);
+ LVL2_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL2_RND_NUMBER_OUT : out std_logic_vector(7 downto 0);
+ TRIGBOX_LVL1_TRIGGER_INFO_OUT : out std_logic_vector(3 downto 0);
+ -- data transmition to etrax
+ TOKEN_IN : in std_logic;
+ DATA_OUT : out std_logic_vector(31 downto 0);
+ DATA_VALID_OUT : out std_logic;
+ TOKEN_OUT : out std_logic;
+ SAVE_SCALERS_OUT : out std_logic;
+ SAVED_SCALERS_IN : in std_logic_vector(SCALERS_NUMBER*32 -1 downto 0);
+ FAST_TRIGGER_OUT_LVDS : out std_logic_vector(3 downto 0);
+ FAST_TRIGGER_OUT_PECL : out std_logic_vector(3 downto 0);
+ MDCA_TRIGGER_OUT : out std_logic_vector(3 downto 0);
+ MDCB_TRIGGER_OUT : out std_logic_vector(3 downto 0);
+ -- start rates per 1us and 100ns and signals for beam structure
+ HIGH_RATE_MARKERS_OUT : out std_logic_vector(RATE_MARKERS_NUMBER-1 downto 0);
+ LOW_RATE_MARKERS_OUT : out std_logic_vector(RATE_MARKERS_NUMBER - 1 downto 0);
+ HIGH_RATE_THRESHOLD_IN : in std_logic_vector(7 downto 0);
+ LOW_RATE_THRESHOLD_IN : in std_logic_vector(7 downto 0);
+ BEAM_STRUCTURE_OUT : out std_logic_vector(1 downto 0);
+ --debug & cntrl
+ TRIGGER_POLARITY : out std_logic_vector(TRIGGER_INPUTS_NUMBER - 1 downto 0);
+ TRIGGER_LOGIC_CTRL_IN_0 : in std_logic_vector(31 downto 0);
+ TRIGGER_LOGIC_CTRL_IN_1 : in std_logic_vector(31 downto 0);
+ TRIGGER_LOGIC_CTRL_IN_2 : in std_logic_vector(31 downto 0);
+ TRIGGER_LOGIC_DEBUG_OUT_0 : out std_logic_vector(31 downto 0);
+ TRIGGER_LOGIC_DEBUG_OUT_1 : out std_logic_vector(31 downto 0);
+ TRIGGER_LOGIC_DEBUG_OUT_2 : out std_logic_vector(4 downto 0)
+ );
+end cts_trigger_logic;
+
+architecture cts_trigger_logic of cts_trigger_logic is
+
+ component dll_in400_out200
+ port (
+ clk : in std_logic;
+ aluhold : in std_logic;
+ clkop : out std_logic;
+ clkos : out std_logic;
+ lock : out std_logic);
+ end component;
+
+ component cts_polarity_check
+ generic (
+ NUMBER_OF_SIGNALS : natural);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ SIGNAL_IN : in std_logic_vector(NUMBER_OF_SIGNALS - 1 downto 0);
+ SIGNAL_OUT : out std_logic_vector(NUMBER_OF_SIGNALS - 1 downto 0));
+ end component;
+
+ component cts_check_detector_rates
+ generic (
+ NUMBER_OF_INPUTS : natural);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ SIGNAL_IN : in std_logic_vector(NUMBER_OF_INPUTS - 1 downto 0);
+ HIGH_RATE_MARKERS_OUT : out std_logic_vector(NUMBER_OF_INPUTS - 1 downto 0);
+ LOW_RATE_MARKERS_OUT : out std_logic_vector(NUMBER_OF_INPUTS - 1 downto 0);
+ ONE_SEC_IN_RESET : in std_logic;
+ HIGH_RATE_THRESHOLD_IN : in std_logic_vector(7 downto 0);
+ LOW_RATE_THRESHOLD_IN : in std_logic_vector(7 downto 0));
+ end component;
+
+ component cts_align_signals
+ generic (
+ DELAY : natural;
+ VECTOR_WIDTH : natural
+ );
+ port (
+ CLK : in std_logic;
+ SIGNAL_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ SIGNAL_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0));
+ end component;
+
+ component ddr_lvl1_trigger
+ generic (
+ VECTOR_WIDTH : natural
+ );
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ CLK_100 : in std_logic;
+ CLK_400MHz : in std_logic;
+ CLK_40MHz_OUT : out std_logic;
+ TRIGGER_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ FAST_TRIGGER_OUT_LVDS : out std_logic_vector(3 downto 0);
+ FAST_TRIGGER_OUT_PECL : out std_logic_vector(3 downto 0);
+ MDCA_TRIGGER_OUT : out std_logic_vector(3 downto 0);
+ MDCB_TRIGGER_OUT : out std_logic_vector(3 downto 0);
+ LVL1_LOGICAL_TRIGG_OUT : out std_logic;
+ TRIGGER_IN : in std_logic;
+ CAL_MARKER_IN : in std_logic;
+ TRIGGER_WIDTH_IN : in std_logic_vector(3 downto 0);
+ FAST_TRIGGER_DELAY_IN : in std_logic_vector(3 downto 0);
+ MDCA_TRIGGER_DELAY_IN : in std_logic_vector(4 downto 0);
+ MDCB_TRIGGER_DELAY_IN : in std_logic_vector(4 downto 0);
+ LVL1_LOCAL_BUSY_IN : in std_logic;
+ LVL1_TRBNET_BUSY_IN : in std_logic;
+ LVL1_BUSY_OUT : out std_logic;
+ LVL1_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL1_RND_NUMBER_OUT : out std_logic_vector(7 downto 0);
+ LVL2_TRBNET_BUSY_IN : in std_logic;
+ LVL2_LOCAL_BUSY_IN : in std_logic;
+ LVL2_TRIGGER_OUT : out std_logic;
+ LVL2_TRIGGER_CODE_OUT : out std_logic_vector(3 downto 0);
+ LVL2_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL2_RND_NUMBER_OUT : out std_logic_vector(7 downto 0);
+ DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_0 : out std_logic_vector(31 downto 0);
+ DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_1 : out std_logic_vector(31 downto 0);
+ DDR_LVL1_TRIGGER_BUFFER_CTRL_IN_0 : in std_logic_vector(11 downto 0)
+ );
+ end component;
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ component delay port (
+ clk : in std_logic;
+ to_be_delayed : in std_logic;
+ delay_value : in std_logic_vector(3 downto 0);
+ delayed_pulse : out std_logic
+ );
+ end component;
+
+ component cts_delay_large --20ns -> 15ns
+ generic (
+ VECTOR_WIDTH : integer range 1 to 32);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ DELAY_IN : in std_logic_vector(7 downto 0);
+ DELAY_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ DELAY_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0));
+ end component;
+
+ component downscale port (
+ CLK : in std_logic;
+ disable : in std_logic;
+ to_be_downscaled : in std_logic;
+ downscale_value : in std_logic_vector(3 downto 0);
+ downscaled : out std_logic
+ );
+ end component;
+
+ component set_width port (
+ clk : in std_logic;
+ to_be_set : in std_logic;
+ width_value : in std_logic_vector(3 downto 0);
+ width_adjusted_pulse : out std_logic);
+ end component;
+
+ component new_downscale_ck
+ port(
+ downscale_value : in std_logic_vector(3 downto 0);
+ clk : in std_logic;
+ downscaled : out std_logic;
+ output_disable : in std_logic;
+ global_inhibit : in std_logic;
+ scaler_reset : out std_logic;
+ cal_inhibit : out std_logic;
+ cal_trigger : out std_logic
+ );
+ end component;
+
+ component beam_ramp
+ port(
+ clk_300mhz : in std_logic;
+ clk_50mhz : in std_logic;
+ input : in std_logic;
+ frequency_value : std_logic_vector(15 downto 0);
+ delay_value : in std_logic_vector(7 downto 0);
+ width_value_inhibit : in std_logic_vector(7 downto 0);
+ width_value_external : in std_logic_vector(7 downto 0);
+ output_inhibit : out std_logic;
+ output_external : out std_logic;
+ beam_ramp_debug : out std_logic_vector(31 downto 0)
+ );
+ end component;
+
+ component multiplicity
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ SIGNAL_IN : in std_logic_vector(5 downto 0);
+ SIGNAL_OUT : out std_logic_vector(8 downto 0)
+ );
+ end component;
+
+ component cts_cal_screset_gen
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ GLOBAL_INHIBIT_IN : in std_logic;
+ GEN_FREQ_IN : in std_logic_vector(27 downto 0);
+ GEN_OUT : out std_logic;
+ SCALER_RESET_OUT : out std_logic;
+ MDC_CAL_ENABLE_IN : in std_logic;
+ SHOWER_PED_DISABLE_IN : in std_logic;
+ SHOWER_PED_UPDATE_IN : in std_logic;
+ SHOWER_CAL_ENABLE_IN : in std_logic;
+ CAL_DEBUG_ENABLE_IN : in std_logic;
+ CAL_INHIBIT_OUT : out std_logic;
+ CAL_TRIGGERS_OUT : out std_logic;
+ CAL_CODE_OUT : out std_logic_vector;
+ BEAM_OFF_IN : in std_logic;
+ DEBUG_OUT : out std_logic_vector(31 downto 0));
+ end component;
+
+ component edge_clk
+ port (
+ clk : in std_logic;
+ clkop : out std_logic;
+ clkos : out std_logic;
+ lock : out std_logic);
+ end component;
+
+ component ddr_out_clk
+ port (
+ clk : in std_logic;
+ clkop : out std_logic;
+ clkos : out std_logic;
+ lock : out std_logic);
+ end component;
+
+ component ddr_in
+ port (
+ Data : in std_logic_vector(0 downto 0);
+ EClk : in std_logic;
+ SClk : in std_logic;
+ Rst : in std_logic;
+ Q : out std_logic_vector(7 downto 0);
+ Update : out std_logic_vector(0 downto 0));
+ end component;
+
+ component ddr_out
+ port (
+ Data : in std_logic_vector(7 downto 0);
+ EClk : in std_logic;
+ SClk : in std_logic;
+ Rst : in std_logic;
+ Q : out std_logic_vector(0 downto 0);
+ Update : out std_logic_vector(0 downto 0));
+ end component;
+
+ component ddr_out200MHz --5ns
+ port (
+ Data : in std_logic_vector(3 downto 0);
+ EClk : in std_logic;
+ SClk : in std_logic;
+ Rst : in std_logic;
+ Q : out std_logic_vector(0 downto 0);
+ Update : out std_logic_vector(0 downto 0));
+ end component;
+
+ component ddr_in200MHz --5ns
+ port (
+ Data : in std_logic_vector(0 downto 0);
+ EClk : in std_logic;
+ SClk : in std_logic;
+ Rst : in std_logic;
+ Q : out std_logic_vector(3 downto 0);
+ Update : out std_logic_vector(0 downto 0));
+ end component;
+
+ component cts_one_clock --5ns
+ generic (
+ VECTOR_WIDTH : integer range 1 to 8);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ ONE_CLOCK_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ ONE_CLOCK_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ ENABLE_IN : in std_logic
+ );
+ end component;
+
+ component cts_delay --15ns -> 10ns
+ generic (
+ VECTOR_WIDTH : integer range 1 to 8);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ DELAY_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ DELAY_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ DELAY_VALUE_IN : in std_logic_vector(3 downto 0));
+ end component;
+
+ component cts_downscale --25ns -> 20ns
+ generic (
+ VECTOR_WIDTH : integer range 1 to 8);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ DOWNSCALE_VALUE_IN : in std_logic_vector(3 downto 0);
+ DOWNSCALE_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ DOWNSCALE_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0));
+ end component;
+
+ component cts_set_width --35ns -> 30ns (additional 5 possible)
+ generic (
+ VECTOR_WIDTH : integer range 1 to 8);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ WIDTH_IN : in std_logic_vector(3 downto 0);
+ SIGNAL_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ SIGNAL_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0));
+ end component;
+
+ component cts_set_width_large --15ns
+ generic (
+ VECTOR_WIDTH : natural);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ WIDTH_IN : in std_logic_vector(3 downto 0);
+ SIGNAL_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ SIGNAL_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0));
+ end component;
+
+ component cts_one_clock_special
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ ONE_CLOCK_VECTOR_IN : in std_logic_vector(7 downto 0);
+ ONE_CLOCK_VECTOR_OUT : out std_logic_vector(7 downto 0));
+ end component;
+
+ component ddr_11inputs_400MHz
+ port (
+ Data : in std_logic_vector(10 downto 0);
+ EClk : in std_logic;
+ Rst : in std_logic;
+ SClk : out std_logic;
+ Q : out std_logic_vector(43 downto 0);
+ Update : out std_logic_vector(10 downto 0));
+ end component;
+
+ component fifo_synch_16inputs
+ port (
+ Data : in std_logic_vector(127 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(127 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+
+
+
+-- component sdr4x
+-- port (
+-- Data : in std_logic_vector(0 downto 0);
+-- EClk : in std_logic;
+-- SClk : in std_logic;
+-- Rst : in std_logic;
+-- Q : out std_logic_vector(3 downto 0);
+-- Update : out std_logic_vector(0 downto 0));
+-- end component;
+
+-- component ddr_in200MHz
+-- port (
+-- Data : in std_logic_vector(0 downto 0);
+-- EClk : in std_logic;
+-- SClk : in std_logic;
+-- Rst : in std_logic;
+-- Q : out std_logic_vector(3 downto 0);
+-- Update : out std_logic_vector(0 downto 0));
+-- end component;
+
+ signal input_to_fifo_sunch_a : std_logic_vector(43 downto 0);
+ signal output_from_fifo_sunch_a : std_logic_vector(((TRIGGER_INPUTS_NUMBER-1)*4+32) downto 0);
+ signal ddr_outvector : std_logic_vector((TRIGGER_INPUTS_NUMBER-1)*4+32 downto 0);
+ signal ddr_div_clk : std_logic_vector(4 downto 0);
+
+
+ signal clk_400_ref_a : std_logic;
+ signal clk_400_ref_b : std_logic;
+
+ signal pti_one_clock_in, pti_delayed_in, pti_sclaer_in, pti_ready_in, pti_downscaled_in, pti_set_width_in , pti_and_gts_in : std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0);
+ signal pti_one_clock_out, pti_delayed_out, pti_ready_out, pti_downscaled_out, pti_set_width_out, pti_and_gts_out, pti_and_gts_out_synch, pti_and_gts_out_saved : std_logic_vector(TRIGGER_INPUTS_NUMBER-1 downto 0) :=(others => '0');
+ signal start_veto_anticoincidence : std_logic;
+ signal cal_inhibit, cal_trigger, out_inhibit, out_inhibit_without_hv_ramp, beam_inhibit, bus_inhibit : std_logic;
+ signal cal_code : std_logic_vector(3 downto 0);
+ signal global_timing_signal_out, or_out, or_out_slow,or_out_slow_sync : std_logic;
+ signal tof_multiplicity : std_logic_vector(7 downto 0);
+ signal tof_multiplicity_all : std_logic;
+ signal multiplicity_out : std_logic_vector(8 downto 0);
+ signal tof_mdc_trigger : std_logic;
+ signal multiplexer_address_a, multiplexer_address_b,multiplexer_address_c, multiplexer_address_d : integer range 0 to 128 :=0;
+ signal multiplexer_sync_array_a,multiplexer_sync_array_b,multiplexer_sync_array_c,multiplexer_sync_array_d : std_logic_vector(7 downto 0);
+
+ signal multiplexers_in : std_logic_vector(66 downto 0);
+ type multiplexer_in_array_type is array (0 to 136) of std_logic_vector(VECTOR_WIDTH -1 downto 0);
+ signal multiplexer_in_array_a,multiplexer_in_array_b : multiplexer_in_array_type;
+ signal multiplexer_array_out_a,multiplexer_array_out_b,multiplexer_array_out_c,multiplexer_array_out_d : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ signal saved_latches : std_logic_vector(50 downto 0);
+
+ type event_data_type is array (0 to 16) of std_logic_vector(31 downto 0);
+ signal event_data : event_data_type;
+
+ signal reset_scalers, reset_scalers_sync : std_logic;
+ type LVL1_TEST is (IDLE, LVL1_A, LVL1_B, LVL1_C, LVL1_D, LVL1_E, LVL1_F);
+ signal LVL1_CURRENT, LVL1_NEXT : LVL1_TEST;
+ signal lvl1_trigger_code : std_logic_vector(3 downto 0);
+ signal lvl1_trigger_fsm : std_logic;
+ signal lvl1_trigger_out_fast : std_logic;
+ signal lvl1_end, lvl1_end_pulse : std_logic;
+ signal lvl1_busy_fsm : std_logic;
+ signal data_valid_fsm : std_logic;
+ signal data_out_i_fsm : std_logic_vector(31 downto 0);
+ signal lvl1_busy_end_fsm : std_logic;
+ signal lvl1_trigger_debug_fsm : std_logic_vector(3 downto 0);
+ signal lvl1_trigger,lvl1_trigger_pulse : std_logic;
+ signal lvl1_busy : std_logic;
+ signal data_valid : std_logic;
+ signal data_out_i : std_logic_vector(31 downto 0);
+ signal lvl1_busy_end : std_logic;
+ signal lvl1_trigger_debug : std_logic_vector(3 downto 0);
+ signal trigger_latch : std_logic_vector(31 downto 0);
+ signal internal_trigger : std_logic;
+ signal token_out_fsm, token_out_i : std_logic;
+ signal scaler_marker : std_logic;
+ signal data_send_cntr : std_logic_vector(7 downto 0);
+ signal data_send_up, data_send_up_fsm,data_send_reset,data_send_reset_fsm : std_logic;
+
+ signal mdc_cal_inhibit_out, mdc_cal_trigger_out, shower_cal_inhibit_out, shower_cal_trigger_out, shower_cal_save_out : std_logic;
+ signal int_counter : integer range 0 to 66 :=0;
+ signal data_valid_sync : std_logic;
+ constant HOW_MANY_DATA_TO_SEND : integer := 64;
+ signal accepting_latch_busy : std_logic;
+
+ type scaler_type is array (0 to SCALERS_NUMBER+2) of std_logic_vector(31 downto 0);
+ signal scalers : scaler_type;
+ type ipu_data is array (0 to CTS_NUMBER_IPU_DATA-1) of std_logic_vector(31 downto 0);
+ signal ipu_data_saved : ipu_data;
+ signal data_to_send : scaler_type;
+ signal no_timing : std_logic;
+ signal dummy_token : std_logic;
+ signal beam_inhibit_in_i : std_logic;
+ signal phys_trigger_out, phys_trigger_out_local_busy, cal_trigger_out, cal_trigger_out_synch : std_logic;
+ signal scalers_out_save_signal : std_logic;
+ signal scalers_out_save_pulse : std_logic;
+ signal scalers_out_up : std_logic_vector(TRIGGER_OUTPUTS_NUMBER-1 downto 0);
+ signal scalers_coincidence_out_up : std_logic_vector(TRIGGER_OUTPUTS_NUMBER-1 downto 0);
+
+ signal edge_clock_locked : std_logic;
+ signal CLK_800MHz : std_logic;
+ signal CLK_400MHz : std_logic;
+
+ type trigger_array_type is array (0 to TRIGGER_INPUTS_NUMBER - 1) of std_logic_vector(VECTOR_WIDTH -1 downto 0);
+ signal input_trigger_array,input_trigger_array_sync, input_trigger_array_sync_b : trigger_array_type;
+ signal pti_one_clock_in_array,pti_one_clock_out_array,pti_delayed_in_array,pti_delayed_out_array,pti_delayed_large_in_array,pti_delayed_large_out_array,pti_downscaled_in_array,pti_downscaled_out_array,pti_set_width_in_array,pti_set_width_large_in_array,pti_set_width_out_array,pti_set_width_small_out_array,pti_set_width_small_in_array,pti_set_width_large_out_array,one_clock_special_in,pti_and_gts_in_array,pti_and_gts_out_array : trigger_array_type;
+
+ signal update_out : std_logic_vector(TRIGGER_INPUTS_NUMBER - 1 downto 0);
+ signal scaler_in_for_fast_cts,downscale_in_for_fast_cts : std_logic_vector(SCALERS_NUMBER*2 - 1 downto 0);
+
+ signal multiplicity_in_array : std_logic_vector(5 downto 0);
+ signal tof_rpc_or, tof_rpc_sync, tof_rpc_fast, start_veto_anticoincidence_array,final_trigger_array,multiplicity_out_array : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+
+ type individual_multiplicity_out_array_type is array (0 to 9) of std_logic_vector(VECTOR_WIDTH -1 downto 0);
+ signal individual_multiplicity_out_array : individual_multiplicity_out_array_type;
+
+ type pti_and_gts_out_synch_array_type is array (0 to TRIGGER_OUTPUTS_NUMBER-1) of std_logic_vector(VECTOR_WIDTH -1 downto 0);
+ signal pti_and_gts_out_synch_array : pti_and_gts_out_synch_array_type;
+
+ signal veto_or_array,veto_or_array_out,start_or_array,start_or_array_out : std_logic_vector(VECTOR_WIDTH -1 downto 0);
+ signal out_or_array,or_out_array : std_logic_vector(TRIGGER_OUTPUTS_NUMBER-1 downto 0);
+
+ signal lvl1_busy_out_i : std_logic;
+ signal send_scalers, send_scalers_fsm : std_logic;
+ --special signals for delays
+ signal pti_and_gts_out_saved_array,start_downscaled_in_delayed,veto_width_out_delayed : std_logic_vector(VECTOR_WIDTH - 1 downto 0); --anticoincidence_signals
+ signal multiplicity_out_for_delay : std_logic_vector(8 downto 0);
+ signal multiplicity_out_array_delayed : std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+
+ --large delay signals
+
+ signal start_veto_large_delay_in, start_veto_large_delay_out : std_logic_vector(63 downto 0);
+ signal tof_large_delay_in, tof_large_delay_out, rpc_large_delay_in, rpc_large_delay_out : std_logic_vector(23 downto 0);
+ signal tof56_large_delay_in, tof56_large_delay_out, rpc56_large_delay_in, rpc56_large_delay_out : std_logic_vector(15 downto 0);
+
+ --signal for beam structure
+ signal start_signals_beam_straucture : std_logic_vector(7 downto 0);
+ signal individual_hist_signal_a, individual_hist_signal_b : std_logic;
+ --signal for polarity check
+ signal input_polarity_sinal, output_polarity_signal : std_logic_vector(TRIGGER_INPUTS_NUMBER - 1 downto 0);
+ --special scalers
+ signal trigg_relative_time, trigg_relative_time_saved : std_logic_vector(31 downto 0);
+ signal trigg_last_time, trigg_last_time_saved : std_logic_vector(31 downto 0);
+ signal trigg_anticoinc_time, trigg_anticoinc_time_saved : std_logic_vector(31 downto 0);
+ signal trigg_anticoinc : std_logic;
+
+begin
+ -- TRIGGER_IN
+ -- 7:0 TS
+ -- 15:8 Veto
+ -- 21:16 TOF
+ -- 27:22 RPC
+ -- 36:28 TOF Multiplicicty
+ -- 44:37 Physical triggers - only 4 now - for beam test 2010 june 32 external
+ -- 52:45 MDC not used curently
+ -- 53 TOF & MDC - not used currently
+
+ REWRITE_INPUT_VECTOR_TO_ARRAY: for i in 0 to TRIGGER_INPUTS_NUMBER-1 generate
+ input_trigger_array(i) <= TRIGGER_IN((i+1)*4-1 downto i*4);
+ end generate REWRITE_INPUT_VECTOR_TO_ARRAY;
+
+ MAKE_CORRECT_POLARIZATION : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ input_trigger_array_sync(0) <= not input_trigger_array(0);
+ input_trigger_array_sync(1) <= not input_trigger_array(1);
+ input_trigger_array_sync(2) <= not input_trigger_array(2);
+ input_trigger_array_sync(3) <= not input_trigger_array(3);
+ input_trigger_array_sync(4) <= not input_trigger_array(4);
+ input_trigger_array_sync(5) <= not input_trigger_array(5);
+ input_trigger_array_sync(6) <= not input_trigger_array(6);
+ input_trigger_array_sync(7) <= not input_trigger_array(7);
+ input_trigger_array_sync(8) <= not input_trigger_array(8);
+ input_trigger_array_sync(9) <= not input_trigger_array(9);
+ input_trigger_array_sync(10) <= not input_trigger_array(10);
+ input_trigger_array_sync(11) <= not input_trigger_array(11);
+ input_trigger_array_sync(12) <= not input_trigger_array(12);
+ input_trigger_array_sync(13) <= not input_trigger_array(13);
+ input_trigger_array_sync(14) <= not input_trigger_array(14);
+ input_trigger_array_sync(15) <= not input_trigger_array(15);
+ input_trigger_array_sync(16) <= not input_trigger_array(16);
+ input_trigger_array_sync(17) <= not input_trigger_array(17);
+ input_trigger_array_sync(18) <= not input_trigger_array(18);
+ input_trigger_array_sync(19) <= not input_trigger_array(19);
+ input_trigger_array_sync(20) <= not input_trigger_array(20);
+ input_trigger_array_sync(21) <= not input_trigger_array(21);
+ input_trigger_array_sync(22) <= not input_trigger_array(22);
+ input_trigger_array_sync(23) <= not input_trigger_array(23);
+ input_trigger_array_sync(24) <= not input_trigger_array(24);
+ input_trigger_array_sync(25) <= not input_trigger_array(25);
+ input_trigger_array_sync(26) <= not input_trigger_array(26);
+ input_trigger_array_sync(27) <= not input_trigger_array(27);
+ input_trigger_array_sync(28) <= input_trigger_array(28);
+ input_trigger_array_sync(29) <= input_trigger_array(29);
+ input_trigger_array_sync(30) <= input_trigger_array(30);
+ input_trigger_array_sync(31) <= input_trigger_array(31);
+ input_trigger_array_sync(32) <= input_trigger_array(32);
+ input_trigger_array_sync(33) <= input_trigger_array(33);
+ input_trigger_array_sync(34) <= input_trigger_array(34);
+ input_trigger_array_sync(35) <= input_trigger_array(35);
+ input_trigger_array_sync_b <= input_trigger_array_sync;
+ end if;
+ end process MAKE_CORRECT_POLARIZATION;
+ -- pti_one_clock_in_array <= input_trigger_array;
+ pti_one_clock_in_array <= input_trigger_array_sync_b;
+
+ --check polarity
+
+ SET_POLARITY: for i in 0 to TRIGGER_INPUTS_NUMBER - 1 generate
+ INDIVIDUAL_SIGNALS_FOR_POLARITY : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ input_polarity_sinal(i) <= '0';
+ elsif input_trigger_array_sync_b(i) > 0 then
+ input_polarity_sinal(i) <= '1';
+ else
+ input_polarity_sinal(i) <= '0';
+ end if;
+ end if;
+ end process INDIVIDUAL_SIGNALS_FOR_POLARITY;
+ end generate SET_POLARITY;
+
+ THE_CTS_POLARITY_CHECK: cts_polarity_check
+ generic map (
+ NUMBER_OF_SIGNALS => TRIGGER_INPUTS_NUMBER)
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ SIGNAL_IN => input_polarity_sinal,
+ SIGNAL_OUT => output_polarity_signal);
+
+ TRIGGER_POLARITY <= output_polarity_signal;
+
+ --beam structure
+-- MAKE_START_BEAM_STRUCTURE: for i in 0 to 7 generate
+-- SEND_INDIVIDUAL_START_BEAM_STRUCTURE : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- if RESET = '1' then
+-- start_signals_beam_straucture(i) <= '0';
+-- elsif input_trigger_array(i) > 0 then
+-- start_signals_beam_straucture(i) <= '1';
+-- else
+-- start_signals_beam_straucture(i) <= '0';
+-- end if;
+-- end if;
+-- end process SEND_INDIVIDUAL_START_BEAM_STRUCTURE;
+-- end generate MAKE_START_BEAM_STRUCTURE;
+-- START_BEAM_STRAUCTURE_OUT <= scaler_in_for_fast_cts(7 downto 0);--)pti_one_clock_out_array;--start_signals_beam_straucture;
+
+-------------------------------------------------------------------------------
+-- ONE CLK LONG
+-------------------------------------------------------------------------------
+ ONE_CLK_CONNECTION: for i in 0 to TRIGGER_INPUTS_NUMBER - 1 generate
+ THE_CTS_ONE_CLOCK: cts_one_clock
+ generic map (
+ VECTOR_WIDTH => VECTOR_WIDTH
+ )
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ ONE_CLOCK_VECTOR_IN => pti_one_clock_in_array(i),
+ ONE_CLOCK_VECTOR_OUT => pti_one_clock_out_array(i),
+ ENABLE_IN => INPUT_ENABLE_IN(i)
+ );
+ end generate ONE_CLK_CONNECTION;
+
+-------------------------------------------------------------------------------
+-- LARGE DELAYS
+-------------------------------------------------------------------------------
+
+ pti_delayed_large_in_array <= pti_one_clock_out_array;
+
+ -- --start veto
+
+ START_VETO_LARGE_DELAY_IN_OUT: for i in 0 to 15 generate
+ start_veto_large_delay_in((i+1)*4-1 downto i*4) <= pti_delayed_large_in_array(i);
+ pti_delayed_large_out_array(i) <= start_veto_large_delay_out ((i+1)*4-1 downto i*4);
+ end generate START_VETO_LARGE_DELAY_IN_OUT;
+
+ START_AND_VETO_LARGE_DELAY: for i in 0 to 1 generate
+ THE_CTS_DELAY_LARGE_START_VETO : cts_delay_large
+ generic map (
+ VECTOR_WIDTH => 32)
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ DELAY_IN => DELAY_LARGE_TRIGGER_REGISTER_IN((i+1)*8-1 downto i*8),
+ DELAY_VECTOR_IN => start_veto_large_delay_in((i+1)*32-1 downto i*32),
+ DELAY_VECTOR_OUT => start_veto_large_delay_out((i+1)*32-1 downto i*32));
+ end generate START_AND_VETO_LARGE_DELAY;
+
+ TOF_LARGE_DELAY_IN_OUT: for i in 0 to 5 generate
+ tof_large_delay_in((i+1)*4-1 downto i*4) <= pti_delayed_large_in_array(i+16);
+ pti_delayed_large_out_array(i+16) <= tof_large_delay_out ((i+1)*4-1 downto i*4);
+ end generate TOF_LARGE_DELAY_IN_OUT;
+
+
+ THE_CTS_DELAY_LARGE_TOF : cts_delay_large
+ generic map (
+ VECTOR_WIDTH => 24)
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ DELAY_IN => DELAY_LARGE_TRIGGER_REGISTER_IN(23 downto 16),
+ DELAY_VECTOR_IN => tof_large_delay_in,
+ DELAY_VECTOR_OUT => tof_large_delay_out);
+
+
+ RPC_LARGE_DELAY_IN_OUT: for i in 0 to 5 generate
+ rpc_large_delay_in((i+1)*4-1 downto i*4) <= pti_delayed_large_in_array(i+22);
+ pti_delayed_large_out_array(i+22) <= rpc_large_delay_out ((i+1)*4-1 downto i*4);
+ end generate RPC_LARGE_DELAY_IN_OUT;
+
+
+ THE_CTS_DELAY_LARGE_RPC : cts_delay_large
+ generic map (
+ VECTOR_WIDTH => 24)
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ DELAY_IN => DELAY_LARGE_TRIGGER_REGISTER_IN(31 downto 24),
+ DELAY_VECTOR_IN => rpc_large_delay_in,
+ DELAY_VECTOR_OUT => rpc_large_delay_out);
+
+ PT_LARGE_DELAY: for i in 0 to 7 generate
+ THE_CTS_DELAY_LARGE_START_VETO : cts_delay_large
+ generic map (
+ VECTOR_WIDTH => 4)
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ DELAY_IN => DELAY_LARGE_TRIGGER_REGISTER_IN((i+1+4)*8-1 downto (i+4)*8),
+ DELAY_VECTOR_IN => pti_delayed_large_in_array(28+i),
+ DELAY_VECTOR_OUT => pti_delayed_large_out_array(28+i));
+ end generate PT_LARGE_DELAY;
+
+
+-- --start veto
+-- START_VETO_LARGE_DELAY_IN_OUT: for i in 0 to 15 generate
+-- start_veto_large_delay_in((i+1)*8-1 downto i*8) <= pti_delayed_large_in_array(i);
+-- pti_delayed_large_out_array(i) <= start_veto_large_delay_out ((i+1)*8-1 downto i*8);
+-- end generate START_VETO_LARGE_DELAY_IN_OUT;
+
+-- START_AND_VETO_LARGE_DELAY: for i in 0 to 3 generate
+-- THE_CTS_DELAY_LARGE_START_VETO : cts_delay_large
+-- generic map (
+-- VECTOR_WIDTH => 32)
+-- port map (
+-- RESET => RESET,
+-- CLK => CLK,
+-- DELAY_IN => DELAY_LARGE_TRIGGER_REGISTER_IN((i+1)*8-1 downto i*8),
+-- DELAY_VECTOR_IN => start_veto_large_delay_in((i+1)*32-1 downto i*32),
+-- DELAY_VECTOR_OUT => start_veto_large_delay_out((i+1)*32-1 downto i*32));
+-- end generate START_AND_VETO_LARGE_DELAY;
+
+-- --tof 1 to 4
+
+-- TOF_LARGE_DELAY_IN_OUT: for i in 0 to 3 generate
+-- tof_large_delay_in((i+1)*8-1 downto i*8) <= pti_delayed_large_in_array(i+16);
+-- pti_delayed_large_out_array(i+16) <= tof_large_delay_out ((i+1)*8-1 downto i*8);
+-- end generate TOF_LARGE_DELAY_IN_OUT;
+
+
+-- THE_CTS_DELAY_LARGE_TOF_1TO4 : cts_delay_large
+-- generic map (
+-- VECTOR_WIDTH => 32)
+-- port map (
+-- RESET => RESET,
+-- CLK => CLK,
+-- DELAY_IN => DELAY_LARGE_TRIGGER_REGISTER_IN(39 downto 32),
+-- DELAY_VECTOR_IN => tof_large_delay_in,
+-- DELAY_VECTOR_OUT => tof_large_delay_out);
+
+-- --tof 5 to 6
+
+-- TOF56_LARGE_DELAY_IN_OUT: for i in 0 to 1 generate
+-- tof56_large_delay_in((i+1)*8-1 downto i*8) <= pti_delayed_large_in_array(i+20);
+-- pti_delayed_large_out_array(i+20) <= tof56_large_delay_out ((i+1)*8-1 downto i*8);
+-- end generate TOF56_LARGE_DELAY_IN_OUT;
+
+-- THE56_CTS_DELAY_LARGE_TOF_5TO6 : cts_delay_large
+-- generic map (
+-- VECTOR_WIDTH => 16)
+-- port map (
+-- RESET => RESET,
+-- CLK => CLK,
+-- DELAY_IN => DELAY_LARGE_TRIGGER_REGISTER_IN(47 downto 40),
+-- DELAY_VECTOR_IN => tof56_large_delay_in,
+-- DELAY_VECTOR_OUT => tof56_large_delay_out);
+
+-- --rpc 1 to 4
+
+-- RPC_LARGE_DELAY_IN_OUT: for i in 0 to 3 generate
+-- rpc_large_delay_in((i+1)*8-1 downto i*8) <= pti_delayed_large_in_array(i+22);
+-- pti_delayed_large_out_array(i+22) <= rpc_large_delay_out ((i+1)*8-1 downto i*8);
+-- end generate RPC_LARGE_DELAY_IN_OUT;
+
+
+-- THE_CTS_DELAY_LARGE_RPC_1TO4 : cts_delay_large
+-- generic map (
+-- VECTOR_WIDTH => 32)
+-- port map (
+-- RESET => RESET,
+-- CLK => CLK,
+-- DELAY_IN => DELAY_LARGE_TRIGGER_REGISTER_IN(39 downto 32),
+-- DELAY_VECTOR_IN => rpc_large_delay_in,
+-- DELAY_VECTOR_OUT => rpc_large_delay_out);
+
+-- --rpc 5 to 6
+
+-- RPC56_LARGE_DELAY_IN_OUT: for i in 0 to 1 generate
+-- rpc56_large_delay_in((i+1)*8-1 downto i*8) <= pti_delayed_large_in_array(i+26);
+-- pti_delayed_large_out_array(i+26) <= rpc56_large_delay_out ((i+1)*8-1 downto i*8);
+-- end generate RPC56_LARGE_DELAY_IN_OUT;
+
+-- THE56_CTS_DELAY_LARGE_RPC_5TO6 : cts_delay_large
+-- generic map (
+-- VECTOR_WIDTH => 16)
+-- port map (
+-- RESET => RESET,
+-- CLK => CLK,
+-- DELAY_IN => DELAY_LARGE_TRIGGER_REGISTER_IN(47 downto 40),
+-- DELAY_VECTOR_IN => rpc56_large_delay_in,
+-- DELAY_VECTOR_OUT => rpc56_large_delay_out);
+
+-- PT_LARGE_DELAY: for i in 0 to 3 generate
+
+-- THE_CTS_DELAY_LARGE_START_VETO : cts_delay_large
+-- generic map (
+-- VECTOR_WIDTH => 8)
+-- port map (
+-- RESET => RESET,
+-- CLK => CLK,
+-- DELAY_IN => DELAY_LARGE_TRIGGER_REGISTER_IN((i+1+8)*8-1 downto (i+8)*8),
+-- DELAY_VECTOR_IN => pti_delayed_large_in_array(28+i),
+-- DELAY_VECTOR_OUT => pti_delayed_large_out_array(28+i));
+
+-- end generate PT_LARGE_DELAY;
+
+-------------------------------------------------------------------------------
+-- SMALL DELAYS
+-------------------------------------------------------------------------------
+ pti_delayed_in_array <= pti_delayed_large_out_array;
+-- pti_delayed_in_array <= pti_one_clock_out_array;
+
+ DELAY_CONNECTION: for i in 0 to TRIGGER_INPUTS_NUMBER - 1 generate
+
+ THE_CTS_DELAY : cts_delay
+ generic map (
+ VECTOR_WIDTH => VECTOR_WIDTH
+ )
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ DELAY_VECTOR_IN => pti_delayed_in_array(i),
+ DELAY_VECTOR_OUT => pti_delayed_out_array(i),
+ DELAY_VALUE_IN => DELAY_TRIGGER_REGISTER_IN((i+1)*4-1 downto i*4)
+ );
+
+ end generate DELAY_CONNECTION;
+
+
+-------------------------------------------------------------------------------
+-- SCLAERS AFTER DELAY
+-------------------------------------------------------------------------------
+ RESET_SCALERS_SYNC_PROC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ reset_scalers_sync <= '0';
+ else
+ reset_scalers_sync <= reset_scalers;
+ end if;
+ end if;
+ end process RESET_SCALERS_SYNC_PROC;
+ SAVE_SCALERS_OUT <= reset_scalers;
+
+ SCALER_A_CONNECTION: for i in 0 to TRIGGER_INPUTS_NUMBER - 1 generate
+ LONG_SIGNAL_FOR_SCALERS : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ scaler_in_for_fast_cts(i) <= '0';
+ elsif pti_delayed_out_array(i) > 0 then
+ scaler_in_for_fast_cts(i) <= '1';
+ else
+ scaler_in_for_fast_cts(i) <= '0';
+ end if;
+ end if;
+ end process LONG_SIGNAL_FOR_SCALERS;
+
+ FAST_CTS_SCALER_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 32)
+ port map (
+ CLK => CLK,
+ RESET => reset_scalers_sync,
+ COUNT_OUT => scalers(i),
+ UP_IN => scaler_in_for_fast_cts(i),
+ DOWN_IN => '0');
+ end generate SCALER_A_CONNECTION;
+
+
+-- THE_CTS_CHECK_DETECTOR_RATES: cts_check_detector_rates
+-- generic map (
+-- NUMBER_OF_INPUTS => RATE_MARKERS_NUMBER)
+-- port map (
+-- RESET => RESET,
+-- CLK => CLK,
+-- SIGNAL_IN => scaler_in_for_fast_cts(7 downto 0),
+-- HIGH_RATE_MARKERS_OUT => HIGH_RATE_MARKERS_OUT,
+-- LOW_RATE_MARKERS_OUT => LOW_RATE_MARKERS_OUT,
+-- ONE_SEC_IN_RESET => reset_scalers_sync,
+-- HIGH_RATE_THRESHOLD_IN => HIGH_RATE_THRESHOLD_IN,
+-- LOW_RATE_THRESHOLD_IN => LOW_RATE_THRESHOLD_IN);
+
+-------------------------------------------------------------------------------
+--MULTIPLICITY - from TOF RPC after one clock, delay (input scalers in between)
+--outputs are one bit set (out of 8) the fastest wins
+-------------------------------------------------------------------------------
+
+ MULTIPLICITY_CONNECTION: for i in 0 to 5 generate
+ MULTIPLICITY_IN_PROC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ multiplicity_in_array(i) <= '0';
+ elsif (pti_set_width_out_array(16+i) > 0) or (pti_set_width_out_array(22+i) > 0) then
+ multiplicity_in_array(i) <= '1';
+ else
+ multiplicity_in_array(i) <= '0';
+ end if;
+ end if;
+ end process MULTIPLICITY_IN_PROC;
+ end generate MULTIPLICITY_CONNECTION;
+
+ THE_MULTIPLICITY : multiplicity
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ SIGNAL_IN => multiplicity_in_array, --TOF or RPC
+ SIGNAL_OUT => multiplicity_out_for_delay
+ );
+ multiplicity_out <= multiplicity_out_for_delay;
+
+ TOF_RPC_MAKE_OR_ALL : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ tof_rpc_or <= pti_set_width_out_array(16) or pti_set_width_out_array(17) or pti_set_width_out_array(18) or pti_set_width_out_array(19) or pti_set_width_out_array(20) or pti_set_width_out_array(21) or
+ pti_set_width_out_array(22) or pti_set_width_out_array(23) or pti_set_width_out_array(24) or pti_set_width_out_array(25) or pti_set_width_out_array(26) or pti_set_width_out_array(27);
+ tof_rpc_sync <= tof_rpc_or;
+ end if;
+ end process TOF_RPC_MAKE_OR_ALL;
+
+
+ MAKE_TOF_RPC_FASTEST_SIGNAL : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ tof_rpc_fast <= x"0";
+ elsif tof_rpc_sync = x"0" and tof_rpc_or /= x"0" then
+ tof_rpc_fast <= tof_rpc_or;
+ else
+ tof_rpc_fast <= tof_rpc_fast;
+ end if;
+ end if;
+ end process MAKE_TOF_RPC_FASTEST_SIGNAL;
+
+-- MULT_CTS_FASTEST_SIGNAL: cts_one_clock
+-- generic map (
+-- VECTOR_WIDTH => VECTOR_WIDTH
+-- )
+-- port map (
+-- RESET => RESET,
+-- CLK => CLK,
+-- ENABLE_IN => '1',
+-- ONE_CLOCK_VECTOR_IN => tof_rpc_fast,
+-- ONE_CLOCK_VECTOR_OUT => multiplicity_out_array);
+
+-- cts_align_signals_1: cts_align_signals
+-- generic map (
+-- DELAY => 3,
+-- VECTOR_WIDTH => VECTOR_WIDTH)
+-- port map (
+-- CLK => CLK,
+-- SIGNAL_VECTOR_IN => multiplicity_out_array,
+-- SIGNAL_VECTOR_OUT => multiplicity_out_array_delayed);
+
+ MULT_OUT_SIGNALS: for i in 0 to 8 generate
+ SET_MULT_OUT_PROC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ individual_multiplicity_out_array(i) <= (others => '0');
+ elsif multiplicity_out(i) = '1' then
+ individual_multiplicity_out_array(i) <= tof_rpc_fast;--multiplicity_out_array;
+ else
+ individual_multiplicity_out_array(i) <= (others => '0');
+ end if;
+ end if;
+ end process SET_MULT_OUT_PROC;
+ end generate MULT_OUT_SIGNALS;
+
+
+-------------------------------------------------------------------------------
+-- WIDTH - after multiplicity for TOF and RPC, afetr delay and one clk for
+-- start and veto, afetr delay, one clk and downscale for PT. All input signals
+-- are one clk long (1 bi set out of 8 bit signal)
+-------------------------------------------------------------------------------
+
+ -----------------------------------------------------------------------------
+ -- width with 1.25/5 ns change
+ -----------------------------------------------------------------------------
+ --multiplicity
+ pti_set_width_small_in_array(0) <= pti_downscaled_out_array(2);--(others => '0');--pti_delayed_out_array(0);
+ pti_set_width_small_in_array(1) <= pti_downscaled_out_array(3);--(others => '0');--pti_delayed_out_array(1);
+ pti_set_width_small_in_array(2) <= pti_downscaled_out_array(4);--(others => '0');--pti_delayed_out_array(2);
+ pti_set_width_small_in_array(3) <= pti_downscaled_out_array(5);--(others => '0');--pti_delayed_out_array(3);
+ pti_set_width_small_in_array(4) <= pti_downscaled_out_array(6);--(others => '0');--pti_delayed_out_array(4);
+ pti_set_width_small_in_array(5) <= pti_downscaled_out_array(7);--(others => '0');--pti_delayed_out_array(5);
+ pti_set_width_small_in_array(6) <= pti_downscaled_out_array(8);--(others => '0');--pti_delayed_out_array(6);
+ pti_set_width_small_in_array(7) <= pti_downscaled_out_array(9);--(others => '0');--pti_delayed_out_array(7);
+ pti_set_width_small_in_array(8) <= pti_downscaled_out_array(10);--(others => '0');--pti_delayed_out_array(8);
+ --empty
+ pti_set_width_small_in_array(9) <= (others => '0');--pti_delayed_out_array(9);
+ pti_set_width_small_in_array(10) <= (others => '0');--pti_delayed_out_array(10);
+ pti_set_width_small_in_array(11) <= (others => '0');--pti_delayed_out_array(11);
+ pti_set_width_small_in_array(12) <= (others => '0');--pti_delayed_out_array(12);
+ pti_set_width_small_in_array(13) <= (others => '0');--pti_delayed_out_array(13);
+ pti_set_width_small_in_array(14) <= (others => '0');--pti_delayed_out_array(14);
+ pti_set_width_small_in_array(15) <= (others => '0');--pti_delayed_out_array(15);
+ --tof
+ pti_set_width_small_in_array(16) <= pti_delayed_out_array(16);
+ pti_set_width_small_in_array(17) <= pti_delayed_out_array(17);
+ pti_set_width_small_in_array(18) <= pti_delayed_out_array(18);
+ pti_set_width_small_in_array(19) <= pti_delayed_out_array(19);
+ pti_set_width_small_in_array(20) <= pti_delayed_out_array(20);
+ pti_set_width_small_in_array(21) <= pti_delayed_out_array(21);
+ --rpc
+ pti_set_width_small_in_array(22) <= pti_delayed_out_array(22);
+ pti_set_width_small_in_array(23) <= pti_delayed_out_array(23);
+ pti_set_width_small_in_array(24) <= pti_delayed_out_array(24);
+ pti_set_width_small_in_array(25) <= pti_delayed_out_array(25);
+ pti_set_width_small_in_array(26) <= pti_delayed_out_array(26);
+ pti_set_width_small_in_array(27) <= pti_delayed_out_array(27);
+ --pt
+ pti_set_width_small_in_array(28) <= pti_downscaled_out_array(11);
+ pti_set_width_small_in_array(29) <= pti_downscaled_out_array(12);
+ pti_set_width_small_in_array(30) <= pti_downscaled_out_array(13);
+ pti_set_width_small_in_array(31) <= pti_downscaled_out_array(14);
+ pti_set_width_small_in_array(32) <= pti_downscaled_out_array(15);
+ pti_set_width_small_in_array(33) <= pti_downscaled_out_array(16);
+ pti_set_width_small_in_array(34) <= pti_downscaled_out_array(17);
+ pti_set_width_small_in_array(35) <= pti_downscaled_out_array(18);
+
+
+
+ WIDTH_CONNECTION: for i in 0 to TRIGGER_INPUTS_NUMBER - 1 generate
+ THE_CTS_SET_WIDTH : cts_set_width
+ generic map (
+ VECTOR_WIDTH => VECTOR_WIDTH
+ )
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ WIDTH_IN => WIDTH_REGISTER_IN((i+1)*4-1 downto i*4),
+ SIGNAL_IN => pti_set_width_small_in_array(i),
+ SIGNAL_OUT => pti_set_width_small_out_array(i)); --currently not used !!!!!!!!
+ end generate WIDTH_CONNECTION;
+
+
+ -------------------------------------------------------------------------------
+ -- width large with 5 ns change
+ -------------------------------------------------------------------------------
+
+-- pti_set_width_large_in_array <= pti_set_width_small_out_array;
+ pti_set_width_large_in_array <= pti_set_width_small_in_array;
+
+ WIDTH_LARGE_CONNECTION: for i in 0 to TRIGGER_INPUTS_NUMBER - 1 generate
+ THE_CTS_SET_WIDTH_LARGE : cts_set_width_large
+ generic map (
+ VECTOR_WIDTH => VECTOR_WIDTH
+ )
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ WIDTH_IN => WIDTH_REGISTER_LARGE_IN((i+1)*4-1 downto i*4),
+ SIGNAL_IN => pti_set_width_large_in_array(i),
+ SIGNAL_OUT => pti_set_width_large_out_array(i));
+ end generate WIDTH_LARGE_CONNECTION;
+
+ pti_set_width_out_array <= pti_set_width_large_out_array; --only large
+ --width is used
+ --here
+-- pti_set_width_out_array <= pti_set_width_small_out_array;
+
+-------------------------------------------------------------------------------
+-- DOWNSCALE -- all but start and veto signals are single bit (pulse) input
+-- signals, out is also a pulse. For start and veto fastest wins
+-------------------------------------------------------------------------------
+
+
+-- CLOCK_SIGNALS_FOR_ONE_CLOCK_SPECIAL : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- one_clock_special_in(0) <= pti_set_width_out_array(7) or pti_set_width_out_array(6) or pti_set_width_out_array(5) or pti_set_width_out_array(4) or pti_set_width_out_array(3) or pti_set_width_out_array(2) or pti_set_width_out_array(1) or pti_set_width_out_array(0); --START
+-- one_clock_special_in(1) <= pti_set_width_out_array(15) or pti_set_width_out_array(14) or pti_set_width_out_array(13) or pti_set_width_out_array(12) or pti_set_width_out_array(11) or pti_set_width_out_array(10) or pti_set_width_out_array(9) or pti_set_width_out_array(8);--VETO
+-- end if;
+-- end process CLOCK_SIGNALS_FOR_ONE_CLOCK_SPECIAL;
+
+ CLOCK_SIGNALS_FOR_ONE_CLOCK_SPECIAL : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ one_clock_special_in(0) <= pti_delayed_out_array(7) or pti_delayed_out_array(6) or pti_delayed_out_array(5) or pti_delayed_out_array(4) or pti_delayed_out_array(3) or pti_delayed_out_array(2) or pti_delayed_out_array(1) or pti_delayed_out_array(0); --START
+ one_clock_special_in(1) <= pti_delayed_out_array(15) or pti_delayed_out_array(14) or pti_delayed_out_array(13) or pti_delayed_out_array(12) or pti_delayed_out_array(11) or pti_delayed_out_array(10) or pti_delayed_out_array(9) or pti_delayed_out_array(8);--VETO
+ end if;
+ end process CLOCK_SIGNALS_FOR_ONE_CLOCK_SPECIAL;
+
+ ONE_CLOCK_SPECIAL_INPUTS: for i in 0 to 1 generate
+ THE_CTS_ONE_CLOCK_SPECIAL: cts_one_clock--_special
+ generic map (
+ VECTOR_WIDTH => VECTOR_WIDTH
+ )
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ ENABLE_IN => '1',
+ ONE_CLOCK_VECTOR_IN => one_clock_special_in(i),
+ ONE_CLOCK_VECTOR_OUT => pti_downscaled_in_array(i));
+ end generate ONE_CLOCK_SPECIAL_INPUTS;
+
+ pti_downscaled_in_array(2) <= individual_multiplicity_out_array(0);
+ pti_downscaled_in_array(3) <= individual_multiplicity_out_array(1);
+ pti_downscaled_in_array(4) <= individual_multiplicity_out_array(2);
+ pti_downscaled_in_array(5) <= individual_multiplicity_out_array(3);
+ pti_downscaled_in_array(6) <= individual_multiplicity_out_array(4);
+ pti_downscaled_in_array(7) <= individual_multiplicity_out_array(5);
+ pti_downscaled_in_array(8) <= individual_multiplicity_out_array(6);
+ pti_downscaled_in_array(9) <= individual_multiplicity_out_array(7);
+ pti_downscaled_in_array(10) <= individual_multiplicity_out_array(8);
+
+ pti_downscaled_in_array(11) <= pti_delayed_out_array(28);
+ pti_downscaled_in_array(12) <= pti_delayed_out_array(29);
+ pti_downscaled_in_array(13) <= pti_delayed_out_array(30);
+ pti_downscaled_in_array(14) <= pti_delayed_out_array(31);
+ pti_downscaled_in_array(15) <= pti_delayed_out_array(32);
+ pti_downscaled_in_array(16) <= pti_delayed_out_array(33);
+ pti_downscaled_in_array(17) <= pti_delayed_out_array(34);
+ pti_downscaled_in_array(18) <= pti_delayed_out_array(35);
+
+ DOWNSCALE_CONNECTION: for i in 0 to TRIGGER_INPUTS_NUMBER - 1 generate
+ THE_CTS_DOWNSCALE: cts_downscale
+ generic map (
+ VECTOR_WIDTH => VECTOR_WIDTH
+ )
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ DOWNSCALE_VALUE_IN => DOWNSCALE_REGISTER_IN((i+1)*4-1 downto i*4),
+ DOWNSCALE_VECTOR_IN => pti_downscaled_in_array(i),
+ DOWNSCALE_VECTOR_OUT => pti_downscaled_out_array(i));
+ end generate DOWNSCALE_CONNECTION;
+
+-------------------------------------------------------------------------------
+--SCALERS AFTER DSC
+-------------------------------------------------------------------------------
+
+
+ SCALER_B_CONNECTION: for i in 0 to TRIGGER_OUTPUTS_NUMBER - 1 generate
+ LONG_SIGNAL_FOR_SCALERS : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ scaler_in_for_fast_cts(i+TRIGGER_INPUTS_NUMBER) <= '0';
+ elsif pti_downscaled_out_array(i) > x"00" then
+ scaler_in_for_fast_cts(i+TRIGGER_INPUTS_NUMBER) <= '1';
+ else
+ scaler_in_for_fast_cts(i+TRIGGER_INPUTS_NUMBER) <= '0';
+ end if;
+ end if;
+ end process LONG_SIGNAL_FOR_SCALERS;
+
+ FAST_CTS_SCALER_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 32)
+ port map (
+ CLK => CLK,
+ RESET => reset_scalers_sync,
+ COUNT_OUT => scalers(TRIGGER_INPUTS_NUMBER+i),
+ UP_IN => scaler_in_for_fast_cts(i+TRIGGER_INPUTS_NUMBER),
+ DOWN_IN => '0');
+
+ end generate SCALER_B_CONNECTION;
+
+
+-------------------------------------------------------------------------------
+-- FINAL AND-OR LOGIC FUNCTION
+-------------------------------------------------------------------------------
+
+
+ START_ANTICOINCIDENCE_ALIGN_SIGNALS: cts_align_signals
+ generic map (
+ DELAY => 4,
+ VECTOR_WIDTH => VECTOR_WIDTH)
+ port map (
+ CLK => CLK,
+ SIGNAL_VECTOR_IN => pti_downscaled_in_array(0),
+ SIGNAL_VECTOR_OUT => start_downscaled_in_delayed);
+
+-- VETO_ANTICOINCIDENCE_ALIGN_SIGNALS: cts_align_signals
+-- generic map (
+-- DELAY => 6,
+-- VECTOR_WIDTH => VECTOR_WIDTH)
+-- port map (
+-- CLK => CLK,
+-- SIGNAL_VECTOR_IN => one_clock_special_in(1),
+-- SIGNAL_VECTOR_OUT => veto_width_out_delayed);
+
+ THE_VETO_CTS_SET_WIDTH: cts_set_width
+ generic map (
+ VECTOR_WIDTH => 4)
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ WIDTH_IN => TRIGGER_LOGIC_CTRL_IN_0(23 downto 20),
+ SIGNAL_IN => pti_downscaled_in_array(1),
+ SIGNAL_OUT => veto_width_out_delayed);
+
+ ANTICOINCIDENCE_SIGNALS_CLOCK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if TRIGGER_LOGIC_CTRL_IN_0(16) = '0' then
+ -- start_veto_anticoincidence_array <= start_downscaled_in_delayed and (not veto_width_out_delayed);
+ start_veto_anticoincidence_array <= pti_downscaled_in_array(0) and (not veto_width_out_delayed);
+ else
+ start_veto_anticoincidence_array <= multiplicity_out_array;
+ end if;
+ end if;
+ end process ANTICOINCIDENCE_SIGNALS_CLOCK;
+
+ pti_and_gts_in_array(0) <= pti_downscaled_out_array(0); --START
+ pti_and_gts_in_array(1) <= pti_downscaled_out_array(1); --VET0
+ pti_and_gts_in_array(2) <= pti_set_width_out_array(0); --MULT ...
+ pti_and_gts_in_array(3) <= pti_set_width_out_array(1);
+ pti_and_gts_in_array(4) <= pti_set_width_out_array(2);
+ pti_and_gts_in_array(5) <= pti_set_width_out_array(3);
+ pti_and_gts_in_array(6) <= pti_set_width_out_array(4);
+ pti_and_gts_in_array(7) <= pti_set_width_out_array(5);
+ pti_and_gts_in_array(8) <= pti_set_width_out_array(6);
+ pti_and_gts_in_array(9) <= pti_set_width_out_array(7);
+ pti_and_gts_in_array(10) <= pti_set_width_out_array(8); --MULT_END
+
+ pti_and_gts_in_array(11) <= pti_set_width_out_array(28); --PT
+ pti_and_gts_in_array(12) <= pti_set_width_out_array(29);
+ pti_and_gts_in_array(13) <= pti_set_width_out_array(30);
+ pti_and_gts_in_array(14) <= pti_set_width_out_array(31);
+ pti_and_gts_in_array(15) <= pti_set_width_out_array(32);
+ pti_and_gts_in_array(16) <= pti_set_width_out_array(33);
+ pti_and_gts_in_array(17) <= pti_set_width_out_array(34);
+ pti_and_gts_in_array(18) <= pti_set_width_out_array(35);
+
+
+ FAST_GENERATE_OUT_TRIGGERS : for i in 0 to TRIGGER_OUTPUTS_NUMBER - 1 generate
+ FAST_TS_V_SIGNALS: if i<2 generate
+ FAST_PTI_AND_GTS : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if TRIGGER_OUT_EN_IN(i) = '1' then
+ pti_and_gts_out_array(i) <= pti_and_gts_in_array(i);
+ else
+ pti_and_gts_out_array(i) <= (others => '0');
+ end if;
+ end if;
+ end process FAST_PTI_AND_GTS;
+ end generate FAST_TS_V_SIGNALS;
+ FAST_REST_SIGNALS: if i>1 generate
+ FAST_PTI_AND_GTS_AND_MDC_TOF_OUT : process(CLK)
+ begin
+ if rising_edge(CLK) then
+ if TRIGGER_OUT_EN_IN(i) = '1' and TS_GATING_DISABLE_IN(i-2) = '1' then
+ pti_and_gts_out_array(i) <= pti_and_gts_in_array(i);
+ elsif TRIGGER_OUT_EN_IN(i) = '1' and TS_GATING_DISABLE_IN(i-2) = '0' then
+ pti_and_gts_out_array(i) <= pti_and_gts_in_array(i) and start_veto_anticoincidence_array;
+ else
+ pti_and_gts_out_array(i) <= (others => '0');
+ end if;
+ end if;
+ end process FAST_PTI_AND_GTS_AND_MDC_TOF_OUT;
+ end generate FAST_REST_SIGNALS;
+ end generate FAST_GENERATE_OUT_TRIGGERS;
+
+ TRIGGER_OUT_CONNECTION: for i in 0 to TRIGGER_OUTPUTS_NUMBER - 1 generate
+ TRIGGER_OUT_SAVE : process (CLK, reset) --saving for latches
+ begin
+ if rising_edge(CLK) then
+ if reset = '1' or out_inhibit = '1' then
+ or_out_array(i) <= '0';
+ pti_and_gts_out_synch_array(i) <= (others => '0');
+ elsif (pti_and_gts_out_array(i) > 0) and (out_inhibit = '0') and (or_out_array = 0) then
+--here 5ns
+ or_out_array(i) <= '1';
+ pti_and_gts_out_synch_array(i) <= pti_and_gts_out_array(i);
+-- else
+-- or_out_array(i) <= '0';
+ end if;
+ end if;
+ end process TRIGGER_OUT_SAVE;
+ end generate TRIGGER_OUT_CONNECTION;
+
+ FAST_TRIGGER_OUT_OR : process (CLK, reset)
+ begin
+ if rising_edge(CLK) then
+ if reset = '1' then
+ or_out <= '0';
+ elsif or_out_array > 0 then
+ or_out <= '1';
+ else
+ or_out <= '0';
+ end if;
+ end if;
+ end process FAST_TRIGGER_OUT_OR;
+
+ SAVE_LATCH_VALUES : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or no_timing = '1' then --when cal the data is not real->latch=0
+ pti_and_gts_out_saved <= (others => '0');
+ elsif or_out = '1' and out_inhibit = '0' then
+ pti_and_gts_out_saved <= x"0000" & '0' & or_out_array;
+ else
+ pti_and_gts_out_saved <= pti_and_gts_out_saved;
+ end if;
+ end if;
+ end process SAVE_LATCH_VALUES;
+
+ FINAL_TRIGGER_OUT_SIGNAL : process (CLK, RESET) --creating final out signal
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ pti_and_gts_out_saved_array <= (others => '0');
+ elsif (out_inhibit = '0') and (or_out_array = 0) then
+ pti_and_gts_out_saved_array <= pti_and_gts_out_array(0) or pti_and_gts_out_array(1) or pti_and_gts_out_array(2) or pti_and_gts_out_array(3) or pti_and_gts_out_array(4) or pti_and_gts_out_array(5) or pti_and_gts_out_array(6) or pti_and_gts_out_array(7) or pti_and_gts_out_array(8) or pti_and_gts_out_array(9) or pti_and_gts_out_array(10) or pti_and_gts_out_array(11) or pti_and_gts_out_array(12) or pti_and_gts_out_array(13) or pti_and_gts_out_array(14) or pti_and_gts_out_array(15) or pti_and_gts_out_array(16) or pti_and_gts_out_array(17) or pti_and_gts_out_array(18) ;
+ end if;
+ end if;
+ end process FINAL_TRIGGER_OUT_SIGNAL;
+
+ -----------------------------------------------------------------------------
+ -- scalers after coincidence 17
+ -----------------------------------------------------------------------------
+
+ UPDATE_COINCIDENCE_SCALER_FAST_CTS_MODE: if CTS_MODE = 1 generate
+ FAST_UPDATE_COINCIDENCE_SCALERS: for i in 0 to TRIGGER_OUTPUTS_NUMBER - 1 - 2 generate
+
+ FAST_UPDATE_UP_SIGNAL_FOR_COINCIDENCE_SCALERS : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ scalers_coincidence_out_up(i) <= '0';
+ elsif pti_and_gts_out_array(i+2) > 0 and TS_GATING_DISABLE_IN(i) = '0' then
+ scalers_coincidence_out_up(i) <= '1';
+ else
+ scalers_coincidence_out_up(i) <= '0';
+ end if;
+ end if;
+ end process FAST_UPDATE_UP_SIGNAL_FOR_COINCIDENCE_SCALERS;
+
+ FAST_COINCIDENCE_SCALERS: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 19)
+ port map (
+ CLK => CLK,
+ RESET => reset_scalers_sync,
+ COUNT_OUT => scalers(TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+i)(18 downto 0), --
+ --36+19+19+17
+ UP_IN => scalers_coincidence_out_up(i),
+ DOWN_IN => '0');
+ scalers(TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+i)(31 downto 19) <= (others => '0');
+ end generate FAST_UPDATE_COINCIDENCE_SCALERS;
+ end generate UPDATE_COINCIDENCE_SCALER_FAST_CTS_MODE;
+
+ -----------------------------------------------------------------------------
+ -- scalers after accepting 19
+ -----------------------------------------------------------------------------
+ MAKE_OUT_SCALERS_SAVE_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl1_busy,-- scalers_out_save_signal,
+ pulse => scalers_out_save_pulse);
+
+ UPDATE_OUT_SCALER_FAST_CTS_MODE: if CTS_MODE = 1 generate
+ FAST_UPDATE_OUT_SCALERS: for i in 0 to TRIGGER_OUTPUTS_NUMBER - 1 generate
+
+ FAST_UPDATE_UP_SIGNAL_FOR_OUT_SCALERS : process (CLK)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ scalers_out_up(i) <= '0';
+ else
+ scalers_out_up(i) <= ( pti_and_gts_out_saved(i) and scalers_out_save_pulse and (not(internal_trigger)) );
+ end if;
+ end if;
+ end process FAST_UPDATE_UP_SIGNAL_FOR_OUT_SCALERS;
+
+ FAST_OUT_SCALERS: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 19)
+ port map (
+ CLK => CLK,
+ RESET => reset_scalers_sync,
+ COUNT_OUT => scalers(TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+i)(18 downto 0),
+ UP_IN => scalers_out_up(i),
+ DOWN_IN => '0');
+ scalers(TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+i)(31 downto 19) <= (others => '0');
+ end generate FAST_UPDATE_OUT_SCALERS;
+ end generate UPDATE_OUT_SCALER_FAST_CTS_MODE;
+
+ -----------------------------------------------------------------------------
+ -- trigger logic cal, real, test, pulser
+ -----------------------------------------------------------------------------
+
+ LVL1_CAL_TRIGGER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or lvl1_busy = '1' then --cal trigger send when busy='0'
+ cal_trigger_out <= '0';
+ elsif cal_trigger = '1' then
+ cal_trigger_out <= '1';
+ else
+ cal_trigger_out <= cal_trigger_out;
+ end if;
+ end if;
+ end process LVL1_CAL_TRIGGER;
+
+ FAST_HIGH_FREQ_CLK_TO_LOWER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or LVL1_CURRENT = LVL1_A then
+ or_out_slow <= '0';
+ elsif lvl1_trigger_pulse = '1' then
+ or_out_slow <= '1';
+ else
+ or_out_slow <= or_out_slow;
+ end if;
+ end if;
+ end process FAST_HIGH_FREQ_CLK_TO_LOWER;
+
+ MAKE_LVL1_LOGICAL_PULSE : edge_to_pulse
+ port map (
+ clock => CLK_100,
+ en_clk => '1',
+ signal_in => or_out_slow,
+ pulse => or_out_slow_sync);
+
+ LVL1_TRIGGER_OUT <= or_out_slow_sync;
+
+ LVL1_PHYSICS_TRIGGER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ phys_trigger_out <= '0';
+ elsif (((or_out = '1' and out_inhibit = '0') or (internal_trigger = '1' and out_inhibit = '0'))and(phys_trigger_out_local_busy='0')) or (internal_trigger = '1' and TRIGGER_LOGIC_CTRL_IN_0(31) = '1') then
+ phys_trigger_out <= '1';
+ else
+ phys_trigger_out <= '0';
+ end if;
+ end if;
+ end process LVL1_PHYSICS_TRIGGER;
+
+ LVL1_PHYSICS_TRIGGER_LOCAL_BUSY : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or lvl1_busy_out_i = '1' then
+ phys_trigger_out_local_busy <= '0';
+ elsif (or_out = '1' and out_inhibit = '0') or (internal_trigger = '1' and out_inhibit = '0') or (internal_trigger = '1' and TRIGGER_LOGIC_CTRL_IN_0(31) = '1') then
+ phys_trigger_out_local_busy <= '1';
+ end if;
+ end if;
+ end process LVL1_PHYSICS_TRIGGER_LOCAL_BUSY;
+
+
+ LVL1_TRIGGER_FINAL : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_trigger_out_fast <= '0';
+ else
+ lvl1_trigger_out_fast <= phys_trigger_out or cal_trigger_out;
+ end if;
+ end if;
+ end process LVL1_TRIGGER_FINAL;
+
+ CLK_400MHz <= HIGH_FREQ_CLK;
+
+ THE_DDR_LVL1_TRIGGER : ddr_lvl1_trigger
+ generic map (
+ VECTOR_WIDTH => VECTOR_WIDTH
+ )
+ port map (
+ RESET => RESET,
+ CLK => CLK,
+ CLK_100 => CLK_100,
+ CLK_400MHz => CLK_400MHz,
+ CLK_40MHz_OUT => open,
+ TRIGGER_VECTOR_IN => pti_and_gts_out_saved_array,
+ FAST_TRIGGER_OUT_LVDS => FAST_TRIGGER_OUT_LVDS,
+ FAST_TRIGGER_OUT_PECL => FAST_TRIGGER_OUT_PECL,
+ MDCA_TRIGGER_OUT => MDCA_TRIGGER_OUT,
+ MDCB_TRIGGER_OUT => MDCB_TRIGGER_OUT,
+ LVL1_LOGICAL_TRIGG_OUT => open, --LVL1_TRIGGER_OUT,
+ TRIGGER_IN => lvl1_trigger_out_fast,--lvl1_trigger_pulse,
+ CAL_MARKER_IN => no_timing,
+ TRIGGER_WIDTH_IN => TRIGGER_LOGIC_CTRL_IN_1(31 downto 28),
+ FAST_TRIGGER_DELAY_IN => x"0",
+ MDCA_TRIGGER_DELAY_IN => TRIGGER_LOGIC_CTRL_IN_1(21 downto 17),
+ MDCB_TRIGGER_DELAY_IN => TRIGGER_LOGIC_CTRL_IN_1(16 downto 12),
+ LVL1_LOCAL_BUSY_IN => lvl1_busy,
+ LVL1_TRBNET_BUSY_IN => LVL1_TRBNET_BUSY_IN,
+ LVL1_BUSY_OUT => lvl1_busy_out_i,
+ LVL1_TRIGGER_TAG_OUT => LVL1_TRIGGER_TAG_OUT,
+ LVL1_RND_NUMBER_OUT => LVL1_RND_NUMBER_OUT,
+ LVL2_TRBNET_BUSY_IN => LVL2_TRBNET_BUSY_IN,
+ LVL2_LOCAL_BUSY_IN => LVL2_LOCAL_BUSY_IN,
+ LVL2_TRIGGER_OUT => LVL2_TRIGGER_OUT,
+ LVL2_TRIGGER_CODE_OUT => LVL2_TRIGGER_CODE_OUT,
+ LVL2_TRIGGER_TAG_OUT => LVL2_TRIGGER_TAG_OUT,
+ LVL2_RND_NUMBER_OUT => LVL2_RND_NUMBER_OUT,
+ DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_0 => TRIGGER_LOGIC_DEBUG_OUT_0,
+ DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_1 => TRIGGER_LOGIC_DEBUG_OUT_1,
+ DDR_LVL1_TRIGGER_BUFFER_CTRL_IN_0 => TRIGGER_LOGIC_CTRL_IN_1(11 downto 0)
+ );
+
+ TRIGGER_LOGIC_DEBUG_OUT_2(3 downto 0) <= lvl1_trigger_debug;
+ TRIGGER_LOGIC_DEBUG_OUT_2(4) <= beam_inhibit_in_i;
+
+ beam_inhibit_in_i <= BEAM_INHIBIT_IN and TRIGGER_LOGIC_CTRL_IN_0(14);
+ out_inhibit <= lvl1_busy_out_i or cal_inhibit or (beam_inhibit_in_i and TRIGGER_LOGIC_CTRL_IN_0(15)) or TRIGGER_LOGIC_CTRL_IN_0(10) or (not EMERGENCY_STOP); --
+ out_inhibit_without_hv_ramp <= lvl1_busy_out_i or TRIGGER_LOGIC_CTRL_IN_0(10);-- SIGNAL_IN(0) ;
+
+ ------------------------------------------------------------------------------
+ -- special scalers
+ ------------------------------------------------------------------------------
+
+
+ --realtive time to the start of the beam
+ COUNT_SAVE_RELATIVE_TIME : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or BEAM_START = '1' then
+ trigg_relative_time <= (others => '0');
+ else
+ trigg_relative_time <= trigg_relative_time + 1;
+ end if;
+ end if;
+ end process COUNT_SAVE_RELATIVE_TIME;
+
+ SAVE_RELATIVE_TIME : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ trigg_relative_time_saved <= (others => '0');
+ elsif lvl1_trigger_out_fast = '1' then
+ trigg_relative_time_saved <= trigg_relative_time;
+ else
+ trigg_relative_time_saved <= trigg_relative_time_saved;
+ end if;
+ end if;
+ end process SAVE_RELATIVE_TIME;
+ scalers(TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER-2+1) <= trigg_relative_time_saved;
+
+ --time since the last trigger
+
+ COUNT_SAVE_LAST_TIME : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or lvl1_trigger_out_fast = '1' then
+ trigg_last_time <= (others => '0');
+ else
+ trigg_last_time <= trigg_last_time + 1;
+ end if;
+ end if;
+ end process COUNT_SAVE_LAST_TIME;
+
+ SAVE_LAST_TIME : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ trigg_last_time_saved <= (others => '0');
+ elsif phys_trigger_out = '1' or cal_trigger_out = '1' then
+ trigg_last_time_saved <= trigg_last_time;
+ else
+ trigg_last_time_saved <= trigg_last_time_saved;
+ end if;
+ end if;
+ end process SAVE_LAST_TIME;
+ scalers(TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER-2+2) <= trigg_last_time_saved;
+
+--time since the anticoincidence
+ ANTICOINC_SIGNAL : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ trigg_anticoinc <= '0';
+ elsif start_veto_anticoincidence_array > 0 then
+ trigg_anticoinc <= '1';
+ else
+ trigg_anticoinc <= '0';
+ end if;
+ end if;
+ end process ANTICOINC_SIGNAL;
+
+ COUNT_SAVE_ANTICOINC_TIME : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or trigg_anticoinc = '1' then
+ trigg_anticoinc_time <= (others => '0');
+ else
+ trigg_anticoinc_time <= trigg_anticoinc_time + 1;
+ end if;
+ end if;
+ end process COUNT_SAVE_ANTICOINC_TIME;
+
+ SAVE_ANTICOINC_TIME : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ trigg_anticoinc_time_saved <= (others => '0');
+ elsif start_veto_anticoincidence_array > 0 then
+ trigg_anticoinc_time_saved <= trigg_anticoinc_time;
+ else
+ trigg_anticoinc_time_saved <= trigg_anticoinc_time_saved;
+ end if;
+ end if;
+ end process SAVE_ANTICOINC_TIME;
+ scalers(TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER-2+3) <= trigg_anticoinc_time_saved;
+
+
+ ------------------------------------------------------------------------------
+ -- MULTIPLEXING
+ ------------------------------------------------------------------------------
+ --first multiplexer out pair (all possible connections)
+ MULTIPLEXING_PROC_A : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ multiplexer_address_a <= conv_integer(MULTIPLEXER_SELECT_IN(7 downto 0));
+ multiplexer_address_b <= conv_integer(MULTIPLEXER_SELECT_IN(15 downto 8));
+ multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER) <= start_downscaled_in_delayed;
+ multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+1) <= veto_width_out_delayed;
+ multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+2) <= start_veto_anticoincidence_array;
+ multiplexer_array_out_a <= multiplexer_in_array_a(multiplexer_address_a);
+ multiplexer_array_out_b <= multiplexer_in_array_a(multiplexer_address_b);
+ end if;
+ end process MULTIPLEXING_PROC_A;
+
+ MAKE_SIGNAL_A: for i in 0 to TRIGGER_INPUTS_NUMBER-1 generate
+ MULTIPLEXING_PROC_B : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ multiplexer_in_array_a(i) <= pti_one_clock_out_array(i);
+ multiplexer_in_array_a(i+TRIGGER_INPUTS_NUMBER) <= pti_delayed_out_array(i);
+ multiplexer_in_array_a(i+2*TRIGGER_INPUTS_NUMBER) <= pti_set_width_out_array(i);
+ end if;
+ end process MULTIPLEXING_PROC_B;
+ end generate MAKE_SIGNAL_A;
+
+ MAKE_SIGNAL_B: for i in 0 to TRIGGER_OUTPUTS_NUMBER - 1 generate
+ MULTIPLEXING_PROC_C : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ multiplexer_in_array_a(i+3*TRIGGER_INPUTS_NUMBER) <= pti_downscaled_out_array(i);
+ end if;
+ end process MULTIPLEXING_PROC_C;
+ end generate MAKE_SIGNAL_B;
+
+
+
+ SET_ALL_DDR_BITS: for i in 0 to 3 generate
+ multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+3)(i) <=lvl1_trigger_out_fast;
+ multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+4)(i) <= out_inhibit;
+ multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+5)(i) <= phys_trigger_out_local_busy;
+ multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+6)(i) <= beam_inhibit_in_i;
+ multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+7)(i) <= LVL2_TRBNET_BUSY_IN;
+ multiplexer_in_array_a(3*TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+8)(i) <= LVL2_LOCAL_BUSY_IN;
+ end generate SET_ALL_DDR_BITS;
+
+
+-- MULTIPLEX_WIDT8_A: if VECTOR_WIDTH = 8 generate
+-- MULTIPLEXER_DDR_OUT_A1: ddr_out
+-- port map (
+-- Data => multiplexer_array_out_a,
+-- EClk => CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => MULTIPLEXER_OUT(0 downto 0),
+-- Update => open);
+
+-- MULTIPLEXER_DDR_OUT_B1: ddr_out
+-- port map (
+-- Data => multiplexer_array_out_b,
+-- EClk => CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => MULTIPLEXER_OUT(1 downto 1),
+-- Update => open);
+-- end generate MULTIPLEX_WIDT8_A;
+
+-- MULTIPLEX_WIDT4_A: if VECTOR_WIDTH = 4 generate
+-- MULTIPLEXER_DDR_OUT_A2: ddr_out200MHz
+-- port map (
+-- Data => multiplexer_array_out_a,
+-- EClk => clk_400_ref_a,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => MULTIPLEXER_OUT(0 downto 0),
+-- Update => open);
+
+-- MULTIPLEXER_DDR_OUT_B2: ddr_out200MHz
+-- port map (
+-- Data => multiplexer_array_out_b,
+-- EClk => clk_400_ref_b,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => MULTIPLEXER_OUT(1 downto 1),
+-- Update => open);
+-- end generate MULTIPLEX_WIDT4_A;
+
+ MULTIPLEXER_OUT(3 downto 0) <= multiplexer_array_out_a;
+ MULTIPLEXER_OUT(7 downto 4) <= multiplexer_array_out_b;
+
+ SET_INDIVIDUAL_HIST_SIGNAL_A : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ individual_hist_signal_a <= '0';
+ elsif multiplexer_array_out_a > 0 then
+ individual_hist_signal_a <= '1';
+ else
+ individual_hist_signal_a <= '0';
+ end if;
+ end if;
+ end process SET_INDIVIDUAL_HIST_SIGNAL_A;
+
+ SET_INDIVIDUAL_HIST_SIGNAL_B : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ individual_hist_signal_b <= '0';
+ elsif multiplexer_array_out_b > 0 then
+ individual_hist_signal_b <= '1';
+ else
+ individual_hist_signal_b <= '0';
+ end if;
+ end if;
+ end process SET_INDIVIDUAL_HIST_SIGNAL_B;
+
+
+ SEND_SIGNALS_TO_HISTOGRAM : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ BEAM_STRUCTURE_OUT <= b"00";
+ else
+ BEAM_STRUCTURE_OUT(0) <= individual_hist_signal_a;
+ BEAM_STRUCTURE_OUT(1) <= individual_hist_signal_b;
+ end if;
+ end if;
+ end process SEND_SIGNALS_TO_HISTOGRAM;
+
+--second multiplexer out pair (all possible connections)
+-- MULTIPLEXING_PROC_B : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- multiplexer_address_c <= conv_integer(MULTIPLEXER_SELECT_IN(21 downto 16));
+-- multiplexer_address_d <= conv_integer(MULTIPLEXER_SELECT_IN(27 downto 22));
+-- multiplexer_in_array_b(3*15) <= start_downscaled_in_delayed;
+-- multiplexer_in_array_b(3*15+1) <= veto_width_out_delayed;
+-- multiplexer_in_array_b(3*15+2) <= start_veto_anticoincidence_array;
+-- multiplexer_in_array_b(3*15+3) <= pti_and_gts_out_saved_array;
+-- multiplexer_array_out_c <= multiplexer_in_array_b(multiplexer_address_c);
+-- multiplexer_array_out_d <= multiplexer_in_array_b(multiplexer_address_d);
+-- end if;
+-- end process MULTIPLEXING_PROC_B;
+
+-- MAKE_SIGNAL_C: for i in 0 to 15 generate
+-- MULTIPLEXING_PROC_C : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- multiplexer_in_array_b(i) <= pti_one_clock_out_array(i);
+-- multiplexer_in_array_b(i+TRIGGER_INPUTS_NUMBER) <= pti_delayed_out_array(i);
+-- multiplexer_in_array_b(i+2*TRIGGER_INPUTS_NUMBER) <= pti_set_width_out_array(i);
+-- end if;
+-- end process MULTIPLEXING_PROC_C;
+-- end generate MAKE_SIGNAL_C;
+
+-- MAKE_SIGNAL_D: for i in 0 to TRIGGER_OUTPUTS_NUMBER - 1 generate
+-- MULTIPLEXING_PROC_D : process (CLK, RESET)
+-- begin
+-- if rising_edge(CLK) then
+-- multiplexer_in_array_b(i+3*TRIGGER_INPUTS_NUMBER) <= pti_downscaled_out_array(i);
+-- end if;
+-- end process MULTIPLEXING_PROC_D;
+-- end generate MAKE_SIGNAL_D;
+
+-- MULTIPLEX_WIDT8_B: if VECTOR_WIDTH = 8 generate
+-- MULTIPLEXER_DDR_OUT_C1: ddr_out
+-- port map (
+-- Data => multiplexer_array_out_a,
+-- EClk => CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => MULTIPLEXER_OUT(0 downto 0),
+-- Update => open);
+
+-- MULTIPLEXER_DDR_OUT_D1: ddr_out
+-- port map (
+-- Data => multiplexer_array_out_b,
+-- EClk => CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => MULTIPLEXER_OUT(1 downto 1),
+-- Update => open);
+-- end generate MULTIPLEX_WIDT8_B;
+
+-- MULTIPLEX_WIDT4_B: if VECTOR_WIDTH = 4 generate
+-- MULTIPLEXER_DDR_OUT_C2: ddr_out200MHz
+-- port map (
+-- Data => multiplexer_array_out_a,
+-- EClk => CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => MULTIPLEXER_OUT(0 downto 0),
+-- Update => open);
+
+-- MULTIPLEXER_DDR_OUT_D2: ddr_out200MHz
+-- port map (
+-- Data => multiplexer_array_out_b,
+-- EClk => CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => MULTIPLEXER_OUT(1 downto 1),
+-- Update => open);
+-- end generate MULTIPLEX_WIDT4_B;
+
+-------------------------------------------------------------------------------
+-- LVL1 TRIGGER and DATA TRANSPORT
+-------------------------------------------------------------------------------
+
+ THE_CAL_SCRESET_GEN: cts_cal_screset_gen
+ port map (
+ CLK => CLK,--CLK_100,
+ RESET => RESET,
+ GLOBAL_INHIBIT_IN => out_inhibit_without_hv_ramp,
+ GEN_FREQ_IN => TRIGGER_LOGIC_CTRL_IN_2(27 downto 0), --freq select for internal trigger,
+ GEN_OUT => internal_trigger,
+ SCALER_RESET_OUT => reset_scalers,
+ MDC_CAL_ENABLE_IN => TRIGGER_LOGIC_CTRL_IN_0(5),
+ SHOWER_PED_DISABLE_IN => TRIGGER_LOGIC_CTRL_IN_0(7),
+ SHOWER_PED_UPDATE_IN => TRIGGER_LOGIC_CTRL_IN_0(6),
+ SHOWER_CAL_ENABLE_IN => TRIGGER_LOGIC_CTRL_IN_0(8),
+ CAL_DEBUG_ENABLE_IN => TRIGGER_LOGIC_CTRL_IN_0(9),
+ CAL_INHIBIT_OUT => cal_inhibit,
+ CAL_TRIGGERS_OUT => cal_trigger,
+ CAL_CODE_OUT => cal_code,
+ BEAM_OFF_IN => beam_inhibit_in_i,
+ DEBUG_OUT => open);
+
+
+ SEND_NO_TIMING_INFO : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or token_out_i = '1' then --token_out_i = '1' -- event
+ --finished, lvl1_end_pulse can
+ --not be used (previous event)
+ no_timing <= '0';
+ elsif cal_trigger = '1' or TRIGGER_LOGIC_CTRL_IN_0(4 downto 3) ="11" then
+ no_timing <= '1';
+ else
+ no_timing <= no_timing;
+ end if;
+ end if;
+ end process SEND_NO_TIMING_INFO;
+
+ NO_TIMING_OUT <= no_timing;
+
+ SET_TRIGG_CODE : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_trigger_code <= x"1";
+ elsif cal_trigger = '1' and TRIGGER_LOGIC_CTRL_IN_0(4) = '0' then
+ lvl1_trigger_code <= cal_code;
+ elsif TRIGGER_LOGIC_CTRL_IN_0(4) = '1' then
+ lvl1_trigger_code <= TRIGGER_LOGIC_CTRL_IN_0(3 downto 0);
+ elsif token_out_i = '1' then
+ lvl1_trigger_code <= x"1";
+ else
+ lvl1_trigger_code <= lvl1_trigger_code;
+ end if;
+ end if;
+ end process SET_TRIGG_CODE;
+
+ LVL1_TRIGGER_CODE_OUT <= lvl1_trigger_code;
+
+ MAKE_TRIGGER_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl1_trigger_out_fast,
+ pulse => lvl1_trigger_pulse);
+
+ lvl1_end <= not lvl1_busy;
+ MAKE_TRIGGER_END : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl1_end,
+ pulse => lvl1_end_pulse);
+
+ SAVE_DATA_TO_SEND_TO_TRB : process (CLK, reset) --only latch info - the rest
+ --is in the top entity
+ begin
+ if rising_edge(CLK) then
+ if reset = '1' then
+ data_to_send(0) <= (others => '0');
+ data_to_send(1) <= (others => '0');
+ else
+ data_to_send(0) <= pti_and_gts_out_saved(31 downto 0);
+ data_to_send(1) <= (others => '0');
+ end if;
+ end if;
+ end process SAVE_DATA_TO_SEND_TO_TRB;
+
+ SEND_SCALER_OUT: for i in 0 to SCALERS_NUMBER - 1 generate
+ SCALER_OUT((i+1)*32-1 downto i*32) <= scalers(i);
+ end generate SEND_SCALER_OUT;
+
+ SCALERS_MARKER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or LVL1_F = LVL1_CURRENT then
+ scaler_marker <= '0';
+ elsif reset_scalers = '1' then --check reset_scalers
+ scaler_marker <= '1';
+ else
+ scaler_marker <= scaler_marker;
+ end if;
+ end if;
+ end process SCALERS_MARKER;
+ -----------------------------------------------------------------------------
+ -- DATA TRANSPORT 100MHz
+ -----------------------------------------------------------------------------
+
+
+ LVL1_BUSY_OUT <= lvl1_busy;
+ SEND_SCALERS_OUT <= send_scalers;
+ LVL1_CLOCK : process (CLK_100, RESET)
+ begin
+ if rising_edge(CLK_100) then
+ if RESET = '1' then
+ LVL1_CURRENT <= IDLE;
+ lvl1_busy <= '0';
+ lvl1_trigger <= '0';
+ token_out_i <= '0';
+ data_valid <= '0';
+ data_valid_sync <= '0';
+ lvl1_trigger_debug <= x"1";
+ token_out_i <= '0';
+ int_counter <= conv_integer(data_send_cntr(7 downto 0));
+ send_scalers <= '0';
+ else
+ LVL1_CURRENT <= LVL1_NEXT;
+ lvl1_busy <= lvl1_busy_fsm;
+ lvl1_trigger <= lvl1_trigger_fsm;
+ data_out_i <= data_out_i_fsm;
+ data_valid <= data_valid_fsm;
+ data_valid_sync <= data_valid;
+ lvl1_trigger_debug <= lvl1_trigger_debug_fsm;
+ token_out_i <= token_out_fsm;
+ int_counter <= conv_integer(data_send_cntr(7 downto 0));
+ send_scalers <= send_scalers_fsm;
+ end if;
+ end if;
+ end process LVL1_CLOCK;
+
+ TOKEN_OUT <= token_out_i;
+ DATA_OUT <= data_out_i;
+ DATA_VALID_OUT <= data_valid;
+
+ LVL1_PROC : process (CLK_100)
+ begin
+ lvl1_trigger_fsm <= '0';
+ lvl1_busy_fsm <= '1';
+ data_valid_fsm <= '0';
+ data_out_i_fsm <= (others => '0');
+ lvl1_busy_end_fsm <= '0';
+ lvl1_trigger_debug_fsm <= x"0";
+ token_out_fsm <= '0';
+ send_scalers_fsm <= '0';
+ case (LVL1_CURRENT) is
+
+ when IDLE =>
+ lvl1_trigger_debug_fsm <= x"1";
+ lvl1_busy_fsm <= '0';
+ if LVL1_TRIGGER_ACCEPTED_IN = '1' then
+ LVL1_NEXT <= LVL1_A;
+ else
+ LVL1_NEXT <= IDLE;
+ end if;
+
+ when LVL1_A =>
+ lvl1_trigger_debug_fsm <= x"2";
+ lvl1_trigger_fsm <= '1';
+ if TOKEN_IN = '1' then
+ LVL1_NEXT <= LVL1_B;
+ else
+ LVL1_NEXT <= LVL1_A;
+ end if;
+
+ when LVL1_B =>
+ lvl1_trigger_debug_fsm <= x"4";
+ data_valid_fsm <= '1';
+ data_out_i_fsm <= data_to_send(0);
+ LVL1_NEXT <= LVL1_C;
+
+ when LVL1_C =>
+ lvl1_trigger_debug_fsm <= x"5";
+ data_valid_fsm <= '1';
+ data_out_i_fsm <= data_to_send(1);
+-- if scaler_marker = '0' then
+ if lvl1_trigger_code = x"E" then
+ LVL1_NEXT <= LVL1_D;
+ else
+ LVL1_NEXT <= LVL1_F;
+ end if;
+
+ when LVL1_D =>
+ lvl1_trigger_debug_fsm <= x"6";
+ send_scalers_fsm <= '1';
+ LVL1_NEXT <= LVL1_E;
+
+ when LVL1_E =>
+ lvl1_trigger_debug_fsm <= x"5";
+ if SCALERS_FINISHED_IN = '1' then
+ LVL1_NEXT <= LVL1_F;
+ else
+ LVL1_NEXT <= LVL1_E;
+ end if;
+
+ when LVL1_F =>
+ lvl1_trigger_debug_fsm <= x"5";
+ token_out_fsm <= '1';
+ lvl1_busy_end_fsm <= '1';
+ LVL1_NEXT <= IDLE;
+
+ when others =>
+ lvl1_trigger_debug_fsm <= x"0";
+ LVL1_NEXT <= IDLE;
+
+ end case;
+ end process LVL1_PROC;
+
+end cts_trigger_logic;
+
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA40EP1
+PartName=LFSCM3GA40EP1-7FF1020C
+SpeedGrade=-7
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=ROM
+CoreRevision=5.0
+ModuleName=cts_width_rom
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=07/23/2010
+Time=12:04:36
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+Address=512
+Data=36
+Write=0
+Read=0
+LUT=Sync
+Path=1
+MemFile=/home/marek/ctsaddon/cts_width_rom.mem
+MemFormat=hex
+GSR=Enabled
+EnECC=0
+Optimization=Speed
+Pipeline=0
--- /dev/null
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--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.0
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n cts_width_rom -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type bram -wp 00 -rp 1100 -num_rows 512 -data_width 36 -read_reg0 outreg -memfile /home/marek/ctsaddon/cts_width_rom.mem -memformat hex -sync_reset -cascade -1 -e
+
+-- Fri Jul 23 12:04:37 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity cts_width_rom is
+ port (
+ Address: in std_logic_vector(8 downto 0);
+ OutClock: in std_logic;
+ OutClockEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(35 downto 0));
+end cts_width_rom;
+
+architecture Structure of cts_width_rom is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component DP16KA
+ -- synopsys translate_off
+ generic (INITVAL_00 : in String; INITVAL_01 : in String;
+ INITVAL_02 : in String; INITVAL_03 : in String;
+ INITVAL_04 : in String; INITVAL_05 : in String;
+ INITVAL_06 : in String; INITVAL_07 : in String;
+ INITVAL_08 : in String; INITVAL_09 : in String;
+ INITVAL_0A : in String; INITVAL_0B : in String;
+ INITVAL_0C : in String; INITVAL_0D : in String;
+ INITVAL_0E : in String; INITVAL_0F : in String;
+ INITVAL_10 : in String; INITVAL_11 : in String;
+ INITVAL_12 : in String; INITVAL_13 : in String;
+ INITVAL_14 : in String; INITVAL_15 : in String;
+ INITVAL_16 : in String; INITVAL_17 : in String;
+ INITVAL_18 : in String; INITVAL_19 : in String;
+ INITVAL_1A : in String; INITVAL_1B : in String;
+ INITVAL_1C : in String; INITVAL_1D : in String;
+ INITVAL_1E : in String; INITVAL_1F : in String;
+ INITVAL_20 : in String; INITVAL_21 : in String;
+ INITVAL_22 : in String; INITVAL_23 : in String;
+ INITVAL_24 : in String; INITVAL_25 : in String;
+ INITVAL_26 : in String; INITVAL_27 : in String;
+ INITVAL_28 : in String; INITVAL_29 : in String;
+ INITVAL_2A : in String; INITVAL_2B : in String;
+ INITVAL_2C : in String; INITVAL_2D : in String;
+ INITVAL_2E : in String; INITVAL_2F : in String;
+ INITVAL_30 : in String; INITVAL_31 : in String;
+ INITVAL_32 : in String; INITVAL_33 : in String;
+ INITVAL_34 : in String; INITVAL_35 : in String;
+ INITVAL_36 : in String; INITVAL_37 : in String;
+ INITVAL_38 : in String; INITVAL_39 : in String;
+ INITVAL_3A : in String; INITVAL_3B : in String;
+ INITVAL_3C : in String; INITVAL_3D : in String;
+ INITVAL_3E : in String; INITVAL_3F : in String;
+ GSR : in String; WRITEMODE_B : in String;
+ WRITEMODE_A : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE_B : in String;
+ REGMODE_A : in String; DATA_WIDTH_B : in Integer;
+ DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute INITVAL_3F : string;
+ attribute INITVAL_3E : string;
+ attribute INITVAL_3D : string;
+ attribute INITVAL_3C : string;
+ attribute INITVAL_3B : string;
+ attribute INITVAL_3A : string;
+ attribute INITVAL_39 : string;
+ attribute INITVAL_38 : string;
+ attribute INITVAL_37 : string;
+ attribute INITVAL_36 : string;
+ attribute INITVAL_35 : string;
+ attribute INITVAL_34 : string;
+ attribute INITVAL_33 : string;
+ attribute INITVAL_32 : string;
+ attribute INITVAL_31 : string;
+ attribute INITVAL_30 : string;
+ attribute INITVAL_2F : string;
+ attribute INITVAL_2E : string;
+ attribute INITVAL_2D : string;
+ attribute INITVAL_2C : string;
+ attribute INITVAL_2B : string;
+ attribute INITVAL_2A : string;
+ attribute INITVAL_29 : string;
+ attribute INITVAL_28 : string;
+ attribute INITVAL_27 : string;
+ attribute INITVAL_26 : string;
+ attribute INITVAL_25 : string;
+ attribute INITVAL_24 : string;
+ attribute INITVAL_23 : string;
+ attribute INITVAL_22 : string;
+ attribute INITVAL_21 : string;
+ attribute INITVAL_20 : string;
+ attribute INITVAL_1F : string;
+ attribute INITVAL_1E : string;
+ attribute INITVAL_1D : string;
+ attribute INITVAL_1C : string;
+ attribute INITVAL_1B : string;
+ attribute INITVAL_1A : string;
+ attribute INITVAL_19 : string;
+ attribute INITVAL_18 : string;
+ attribute INITVAL_17 : string;
+ attribute INITVAL_16 : string;
+ attribute INITVAL_15 : string;
+ attribute INITVAL_14 : string;
+ attribute INITVAL_13 : string;
+ attribute INITVAL_12 : string;
+ attribute INITVAL_11 : string;
+ attribute INITVAL_10 : string;
+ attribute INITVAL_0F : string;
+ attribute INITVAL_0E : string;
+ attribute INITVAL_0D : string;
+ attribute INITVAL_0C : string;
+ attribute INITVAL_0B : string;
+ attribute INITVAL_0A : string;
+ attribute INITVAL_09 : string;
+ attribute INITVAL_08 : string;
+ attribute INITVAL_07 : string;
+ attribute INITVAL_06 : string;
+ attribute INITVAL_05 : string;
+ attribute INITVAL_04 : string;
+ attribute INITVAL_03 : string;
+ attribute INITVAL_02 : string;
+ attribute INITVAL_01 : string;
+ attribute INITVAL_00 : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute GSR : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute MEM_LPC_FILE of cts_width_rom_0_0_0 : label is "cts_width_rom.lpc";
+ attribute MEM_INIT_FILE of cts_width_rom_0_0_0 : label is "cts_width_rom.mem";
+ attribute INITVAL_3F of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FFFF3FFFF3FFFF3FFFF1FFFF0FFFF07FFF03FFF00000";
+ attribute INITVAL_3E of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FFFF3FFFF3FFFF1FFFF0FFFF07FFF03FFF01FFF00000";
+ attribute INITVAL_3D of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FFFF3FFFF1FFFF0FFFF07FFF03FFF01FFF00FFF00000";
+ attribute INITVAL_3C of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FFFF1FFFF0FFFF07FFF03FFF01FFF00FFF007FF00000";
+ attribute INITVAL_3B of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000001FFFF0FFFF07FFF03FFF01FFF00FFF007FF003FF00000";
+ attribute INITVAL_3A of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000000FFFF07FFF03FFF01FFF00FFF007FF003FF001FF00000";
+ attribute INITVAL_39 of cts_width_rom_0_0_0 : label is "0x0000000000000000000000000000000000007FFF03FFF01FFF00FFF007FF003FF001FF000FF00000";
+ attribute INITVAL_38 of cts_width_rom_0_0_0 : label is "0x0000000000000000000000000000000000003FFF01FFF00FFF007FF003FF001FF000FF0007F00000";
+ attribute INITVAL_37 of cts_width_rom_0_0_0 : label is "0x0000000000000000000000000000000000001FFF00FFF007FF003FF001FF000FF0007F0003F00000";
+ attribute INITVAL_36 of cts_width_rom_0_0_0 : label is "0x0000000000000000000000000000000000000FFF007FF003FF001FF000FF0007F0003F0001F00000";
+ attribute INITVAL_35 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000007FF003FF001FF000FF0007F0003F0001F0000F00000";
+ attribute INITVAL_34 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000003FF001FF000FF0007F0003F0001F0000F0000700000";
+ attribute INITVAL_33 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000001FF000FF0007F0003F0001F0000F000070000300000";
+ attribute INITVAL_32 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000FF0007F0003F0001F0000F00007000030000100000";
+ attribute INITVAL_31 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000000007F0003F0001F0000F0000700003000010000000000";
+ attribute INITVAL_30 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000000003F0001F0000F000070000300001000000000000000";
+ attribute INITVAL_2F of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000000001F0000F00007000030000100000000000000000000";
+ attribute INITVAL_2E of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000000000F0000700003000010000000000000000000000000";
+ attribute INITVAL_2D of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000070000300001000000000000000000000000000000";
+ attribute INITVAL_2C of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000030000100000000000000000000000000000000000";
+ attribute INITVAL_2B of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000010000000000000000000000000000000000000000";
+ attribute INITVAL_2A of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_29 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_28 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_27 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_26 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_25 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_24 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_23 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_22 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_21 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_20 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1F of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_1E of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_1D of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_1C of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_1B of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_1A of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_19 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_18 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_17 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_16 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_15 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_14 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_13 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_12 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_11 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000";
+ attribute INITVAL_10 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE1FFFF00000";
+ attribute INITVAL_0F of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC1FFFE0FFFF00000";
+ attribute INITVAL_0E of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF81FFFC0FFFE07FFF00000";
+ attribute INITVAL_0D of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE03FFF01FFF80FFFC07FFE03FFF00000";
+ attribute INITVAL_0C of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC03FFE01FFF00FFF807FFC03FFE01FFF00000";
+ attribute INITVAL_0B of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF803FFC01FFE00FFF007FF803FFC01FFE00FFF00000";
+ attribute INITVAL_0A of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000003FF801FFC00FFE007FF003FF801FFC00FFE007FF00000";
+ attribute INITVAL_09 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000001FF800FFC007FE003FF001FF800FFC007FE003FF00000";
+ attribute INITVAL_08 of cts_width_rom_0_0_0 : label is "0x000000000000000000000000000000000000FF8007FC003FE001FF000FF8007FC003FE001FF00000";
+ attribute INITVAL_07 of cts_width_rom_0_0_0 : label is "0x0000000000000000000000000000000000007F8003FC001FE000FF0007F8003FC001FE000FF00000";
+ attribute INITVAL_06 of cts_width_rom_0_0_0 : label is "0x0000000000000000000000000000000000003F8001FC000FE0007F0003F8001FC000FE0007F00000";
+ attribute INITVAL_05 of cts_width_rom_0_0_0 : label is "0x0000000000000000000000000000000000001F8000FC0007E0003F0001F8000FC0007E0003F00000";
+ attribute INITVAL_04 of cts_width_rom_0_0_0 : label is "0x0000000000000000000000000000000000000F80007C0003E0001F0000F80007C0003E0001F00000";
+ attribute INITVAL_03 of cts_width_rom_0_0_0 : label is "0x0000000000000000000000000000000000000780003C0001E0000F0000780003C0001E0000F00000";
+ attribute INITVAL_02 of cts_width_rom_0_0_0 : label is "0x0000000000000000000000000000000000000380001C0000E000070000380001C0000E0000700000";
+ attribute INITVAL_01 of cts_width_rom_0_0_0 : label is "0x0000000000000000000000000000000000000180000C00006000030000180000C000060000300000";
+ attribute INITVAL_00 of cts_width_rom_0_0_0 : label is "0x00000000000000000000000000000000000000800004000020000100000800004000020000100000";
+ attribute CSDECODE_B of cts_width_rom_0_0_0 : label is "0b000";
+ attribute CSDECODE_A of cts_width_rom_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of cts_width_rom_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of cts_width_rom_0_0_0 : label is "NORMAL";
+ attribute GSR of cts_width_rom_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of cts_width_rom_0_0_0 : label is "SYNC";
+ attribute REGMODE_B of cts_width_rom_0_0_0 : label is "OUTREG";
+ attribute REGMODE_A of cts_width_rom_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_B of cts_width_rom_0_0_0 : label is "18";
+ attribute DATA_WIDTH_A of cts_width_rom_0_0_0 : label is "18";
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ cts_width_rom_0_0_0: DP16KA
+ -- synopsys translate_off
+ generic map (INITVAL_3F=> "0x000000000000000000000000000000000003FFFF3FFFF3FFFF3FFFF1FFFF0FFFF07FFF03FFF00000",
+ INITVAL_3E=> "0x000000000000000000000000000000000003FFFF3FFFF3FFFF1FFFF0FFFF07FFF03FFF01FFF00000",
+ INITVAL_3D=> "0x000000000000000000000000000000000003FFFF3FFFF1FFFF0FFFF07FFF03FFF01FFF00FFF00000",
+ INITVAL_3C=> "0x000000000000000000000000000000000003FFFF1FFFF0FFFF07FFF03FFF01FFF00FFF007FF00000",
+ INITVAL_3B=> "0x000000000000000000000000000000000001FFFF0FFFF07FFF03FFF01FFF00FFF007FF003FF00000",
+ INITVAL_3A=> "0x000000000000000000000000000000000000FFFF07FFF03FFF01FFF00FFF007FF003FF001FF00000",
+ INITVAL_39=> "0x0000000000000000000000000000000000007FFF03FFF01FFF00FFF007FF003FF001FF000FF00000",
+ INITVAL_38=> "0x0000000000000000000000000000000000003FFF01FFF00FFF007FF003FF001FF000FF0007F00000",
+ INITVAL_37=> "0x0000000000000000000000000000000000001FFF00FFF007FF003FF001FF000FF0007F0003F00000",
+ INITVAL_36=> "0x0000000000000000000000000000000000000FFF007FF003FF001FF000FF0007F0003F0001F00000",
+ INITVAL_35=> "0x00000000000000000000000000000000000007FF003FF001FF000FF0007F0003F0001F0000F00000",
+ INITVAL_34=> "0x00000000000000000000000000000000000003FF001FF000FF0007F0003F0001F0000F0000700000",
+ INITVAL_33=> "0x00000000000000000000000000000000000001FF000FF0007F0003F0001F0000F000070000300000",
+ INITVAL_32=> "0x00000000000000000000000000000000000000FF0007F0003F0001F0000F00007000030000100000",
+ INITVAL_31=> "0x000000000000000000000000000000000000007F0003F0001F0000F0000700003000010000000000",
+ INITVAL_30=> "0x000000000000000000000000000000000000003F0001F0000F000070000300001000000000000000",
+ INITVAL_2F=> "0x000000000000000000000000000000000000001F0000F00007000030000100000000000000000000",
+ INITVAL_2E=> "0x000000000000000000000000000000000000000F0000700003000010000000000000000000000000",
+ INITVAL_2D=> "0x00000000000000000000000000000000000000070000300001000000000000000000000000000000",
+ INITVAL_2C=> "0x00000000000000000000000000000000000000030000100000000000000000000000000000000000",
+ INITVAL_2B=> "0x00000000000000000000000000000000000000010000000000000000000000000000000000000000",
+ INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1F=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_1E=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_1D=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_1C=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_1B=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_1A=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_19=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_18=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_17=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_16=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_15=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_14=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_13=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_12=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_11=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE3FFFF00000",
+ INITVAL_10=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC3FFFE1FFFF00000",
+ INITVAL_0F=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF83FFFC1FFFE0FFFF00000",
+ INITVAL_0E=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF03FFF81FFFC0FFFE07FFF00000",
+ INITVAL_0D=> "0x000000000000000000000000000000000003FF803FFC03FFE03FFF01FFF80FFFC07FFE03FFF00000",
+ INITVAL_0C=> "0x000000000000000000000000000000000003FF803FFC03FFE01FFF00FFF807FFC03FFE01FFF00000",
+ INITVAL_0B=> "0x000000000000000000000000000000000003FF803FFC01FFE00FFF007FF803FFC01FFE00FFF00000",
+ INITVAL_0A=> "0x000000000000000000000000000000000003FF801FFC00FFE007FF003FF801FFC00FFE007FF00000",
+ INITVAL_09=> "0x000000000000000000000000000000000001FF800FFC007FE003FF001FF800FFC007FE003FF00000",
+ INITVAL_08=> "0x000000000000000000000000000000000000FF8007FC003FE001FF000FF8007FC003FE001FF00000",
+ INITVAL_07=> "0x0000000000000000000000000000000000007F8003FC001FE000FF0007F8003FC001FE000FF00000",
+ INITVAL_06=> "0x0000000000000000000000000000000000003F8001FC000FE0007F0003F8001FC000FE0007F00000",
+ INITVAL_05=> "0x0000000000000000000000000000000000001F8000FC0007E0003F0001F8000FC0007E0003F00000",
+ INITVAL_04=> "0x0000000000000000000000000000000000000F80007C0003E0001F0000F80007C0003E0001F00000",
+ INITVAL_03=> "0x0000000000000000000000000000000000000780003C0001E0000F0000780003C0001E0000F00000",
+ INITVAL_02=> "0x0000000000000000000000000000000000000380001C0000E000070000380001C0000E0000700000",
+ INITVAL_01=> "0x0000000000000000000000000000000000000180000C00006000030000180000C000060000300000",
+ INITVAL_00=> "0x00000000000000000000000000000000000000800004000020000100000800004000020000100000",
+ CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "SYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vhi,
+ ADA3=>scuba_vhi, ADA4=>Address(0), ADA5=>Address(1),
+ ADA6=>Address(2), ADA7=>Address(3), ADA8=>Address(4),
+ ADA9=>Address(5), ADA10=>Address(6), ADA11=>Address(7),
+ ADA12=>Address(8), ADA13=>scuba_vlo, CEA=>OutClockEn,
+ CLKA=>OutClock, WEA=>scuba_vlo, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vhi, ADB1=>scuba_vhi, ADB2=>scuba_vlo,
+ ADB3=>scuba_vlo, ADB4=>Address(0), ADB5=>Address(1),
+ ADB6=>Address(2), ADB7=>Address(3), ADB8=>Address(4),
+ ADB9=>Address(5), ADB10=>Address(6), ADB11=>Address(7),
+ ADB12=>Address(8), ADB13=>scuba_vhi, CEB=>OutClockEn,
+ CLKB=>OutClock, WEB=>scuba_vlo, CSB0=>scuba_vlo,
+ CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>Q(0),
+ DOA1=>Q(1), DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5),
+ DOA6=>Q(6), DOA7=>Q(7), DOA8=>Q(8), DOA9=>Q(9), DOA10=>Q(10),
+ DOA11=>Q(11), DOA12=>Q(12), DOA13=>Q(13), DOA14=>Q(14),
+ DOA15=>Q(15), DOA16=>Q(16), DOA17=>Q(17), DOB0=>Q(18),
+ DOB1=>Q(19), DOB2=>Q(20), DOB3=>Q(21), DOB4=>Q(22),
+ DOB5=>Q(23), DOB6=>Q(24), DOB7=>Q(25), DOB8=>Q(26),
+ DOB9=>Q(27), DOB10=>Q(28), DOB11=>Q(29), DOB12=>Q(30),
+ DOB13=>Q(31), DOB14=>Q(32), DOB15=>Q(33), DOB16=>Q(34),
+ DOB17=>Q(35));
+
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of cts_width_rom is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:DP16KA use entity SCM.DP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module Version: 5.2
+--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n ddr2_12out_clkdiv -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type iol -mode out -width 12 -reg ddr -gear 2 -cdiv -cmode 0 -e
+
+-- Wed Nov 9 17:53:51 2011
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity ddr2_12out_clkdiv is
+ port (
+ Data: in std_logic_vector(47 downto 0);
+ EClk: in std_logic;
+ Rst: in std_logic;
+ SClk: out std_logic;
+ Q: out std_logic_vector(11 downto 0);
+ Update: out std_logic_vector(11 downto 0));
+ attribute dont_touch : boolean;
+ attribute dont_touch of ddr2_12out_clkdiv : entity is true;
+end ddr2_12out_clkdiv;
+
+architecture Structure of ddr2_12out_clkdiv is
+
+ -- internal signal declarations
+ signal ERst: std_logic;
+ signal SClk_t: std_logic;
+ signal buf_Q11: std_logic;
+ signal buf_Q10: std_logic;
+ signal buf_Q9: std_logic;
+ signal buf_Q8: std_logic;
+ signal buf_Q7: std_logic;
+ signal buf_Q6: std_logic;
+ signal buf_Q5: std_logic;
+ signal buf_Q4: std_logic;
+ signal buf_Q3: std_logic;
+ signal buf_Q2: std_logic;
+ signal buf_Q1: std_logic;
+ signal buf_Q0: std_logic;
+
+ -- local component declarations
+ component OB
+ port (I: in std_logic; O: out std_logic);
+ end component;
+ component ODDRX2A
+ -- synopsys translate_off
+ generic (LSRMODE : in String);
+ -- synopsys translate_on
+ port (DA0: in std_logic; DB0: in std_logic; DA1: in std_logic;
+ DB1: in std_logic; ECLK: in std_logic; SCLK: in std_logic;
+ RST: in std_logic; Q: out std_logic;
+ UPDATE: out std_logic);
+ end component;
+ component CLKDIV
+ -- synopsys translate_off
+ generic (DIV : in Integer);
+ -- synopsys translate_on
+ port (CLKI: in std_logic; LSR: in std_logic;
+ CLKO: out std_logic; ELSR: out std_logic);
+ end component;
+ attribute LSRMODE : string;
+ attribute DIV : string;
+ attribute LSRMODE of ud_11 : label is "EDGE";
+ attribute LSRMODE of ud_10 : label is "EDGE";
+ attribute LSRMODE of ud_9 : label is "EDGE";
+ attribute LSRMODE of ud_8 : label is "EDGE";
+ attribute LSRMODE of ud_7 : label is "EDGE";
+ attribute LSRMODE of ud_6 : label is "EDGE";
+ attribute LSRMODE of ud_5 : label is "EDGE";
+ attribute LSRMODE of ud_4 : label is "EDGE";
+ attribute LSRMODE of ud_3 : label is "EDGE";
+ attribute LSRMODE of ud_2 : label is "EDGE";
+ attribute LSRMODE of ud_1 : label is "EDGE";
+ attribute LSRMODE of ud_0 : label is "EDGE";
+ attribute DIV of ucdiv : label is "2";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ ud_11: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(11), DB0=>Data(23), DA1=>Data(35),
+ DB1=>Data(47), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q11, UPDATE=>Update(11));
+
+ ud_10: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(10), DB0=>Data(22), DA1=>Data(34),
+ DB1=>Data(46), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q10, UPDATE=>Update(10));
+
+ ud_9: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(9), DB0=>Data(21), DA1=>Data(33),
+ DB1=>Data(45), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q9, UPDATE=>Update(9));
+
+ ud_8: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(8), DB0=>Data(20), DA1=>Data(32),
+ DB1=>Data(44), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q8, UPDATE=>Update(8));
+
+ ud_7: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(7), DB0=>Data(19), DA1=>Data(31),
+ DB1=>Data(43), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q7, UPDATE=>Update(7));
+
+ ud_6: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(6), DB0=>Data(18), DA1=>Data(30),
+ DB1=>Data(42), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q6, UPDATE=>Update(6));
+
+ ud_5: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(5), DB0=>Data(17), DA1=>Data(29),
+ DB1=>Data(41), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q5, UPDATE=>Update(5));
+
+ ud_4: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(4), DB0=>Data(16), DA1=>Data(28),
+ DB1=>Data(40), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q4, UPDATE=>Update(4));
+
+ ud_3: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(3), DB0=>Data(15), DA1=>Data(27),
+ DB1=>Data(39), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q3, UPDATE=>Update(3));
+
+ ud_2: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(2), DB0=>Data(14), DA1=>Data(26),
+ DB1=>Data(38), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q2, UPDATE=>Update(2));
+
+ ud_1: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(1), DB0=>Data(13), DA1=>Data(25),
+ DB1=>Data(37), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q1, UPDATE=>Update(1));
+
+ ud_0: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(0), DB0=>Data(12), DA1=>Data(24),
+ DB1=>Data(36), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q0, UPDATE=>Update(0));
+
+ ucdiv: CLKDIV
+ -- synopsys translate_off
+ generic map (DIV=> 2)
+ -- synopsys translate_on
+ port map (CLKI=>EClk, LSR=>Rst, CLKO=>SClk_t, ELSR=>ERst);
+
+ buf_Q11_out_inst: OB
+ port map (I=>buf_Q11, O=>Q(11));
+
+ buf_Q10_out_inst: OB
+ port map (I=>buf_Q10, O=>Q(10));
+
+ buf_Q9_out_inst: OB
+ port map (I=>buf_Q9, O=>Q(9));
+
+ buf_Q8_out_inst: OB
+ port map (I=>buf_Q8, O=>Q(8));
+
+ buf_Q7_out_inst: OB
+ port map (I=>buf_Q7, O=>Q(7));
+
+ buf_Q6_out_inst: OB
+ port map (I=>buf_Q6, O=>Q(6));
+
+ buf_Q5_out_inst: OB
+ port map (I=>buf_Q5, O=>Q(5));
+
+ buf_Q4_out_inst: OB
+ port map (I=>buf_Q4, O=>Q(4));
+
+ buf_Q3_out_inst: OB
+ port map (I=>buf_Q3, O=>Q(3));
+
+ buf_Q2_out_inst: OB
+ port map (I=>buf_Q2, O=>Q(2));
+
+ buf_Q1_out_inst: OB
+ port map (I=>buf_Q1, O=>Q(1));
+
+ buf_Q0_out_inst: OB
+ port map (I=>buf_Q0, O=>Q(0));
+
+ SClk <= SClk_t;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of ddr2_12out_clkdiv is
+ for Structure
+ for all:OB use entity SCM.OB(V); end for;
+ for all:ODDRX2A use entity SCM.ODDRX2A(V); end for;
+ for all:CLKDIV use entity SCM.CLKDIV(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module Version: 5.2
+--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n ddr2_16inputs -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type iol -mode in -width 16 -reg ddr -gear 2 -cdiv -cmode 0 -del 0 -e
+
+-- Thu Nov 3 09:39:02 2011
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity ddr2_16inputs is
+ port (
+ Data: in std_logic_vector(15 downto 0);
+ EClk: in std_logic;
+ Rst: in std_logic;
+ SClk: out std_logic;
+ Q: out std_logic_vector(63 downto 0);
+ Update: out std_logic_vector(15 downto 0));
+ attribute dont_touch : boolean;
+ attribute dont_touch of ddr2_16inputs : entity is true;
+end ddr2_16inputs;
+
+architecture Structure of ddr2_16inputs is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal ERst: std_logic;
+ signal SClk_t: std_logic;
+ signal buf_Data15: std_logic;
+ signal buf_Data14: std_logic;
+ signal buf_Data13: std_logic;
+ signal buf_Data12: std_logic;
+ signal buf_Data11: std_logic;
+ signal buf_Data10: std_logic;
+ signal buf_Data9: std_logic;
+ signal buf_Data8: std_logic;
+ signal buf_Data7: std_logic;
+ signal buf_Data6: std_logic;
+ signal buf_Data5: std_logic;
+ signal buf_Data4: std_logic;
+ signal buf_Data3: std_logic;
+ signal buf_Data2: std_logic;
+ signal buf_Data1: std_logic;
+ signal buf_Data0: std_logic;
+
+ -- local component declarations
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component IB
+ port (I: in std_logic; O: out std_logic);
+ end component;
+ component IDDRX2A
+ -- synopsys translate_off
+ generic (AILRST : in String:="DISABLED"; LSRMODE : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; ECLK: in std_logic; SCLK: in std_logic;
+ RST: in std_logic; RSTAIL: in std_logic;
+ RUNAIL: in std_logic; QA0: out std_logic;
+ QB0: out std_logic; QA1: out std_logic;
+ QB1: out std_logic; UPDATE: out std_logic;
+ LOCK: out std_logic);
+ end component;
+ component CLKDIV
+ -- synopsys translate_off
+ generic (DIV : in Integer);
+ -- synopsys translate_on
+ port (CLKI: in std_logic; LSR: in std_logic;
+ CLKO: out std_logic; ELSR: out std_logic);
+ end component;
+ attribute AIL : string;
+ attribute LSRMODE : string;
+ attribute DIV : string;
+ attribute AIL of ud_15 : label is "OFF";
+ attribute LSRMODE of ud_15 : label is "EDGE";
+ attribute AIL of ud_14 : label is "OFF";
+ attribute LSRMODE of ud_14 : label is "EDGE";
+ attribute AIL of ud_13 : label is "OFF";
+ attribute LSRMODE of ud_13 : label is "EDGE";
+ attribute AIL of ud_12 : label is "OFF";
+ attribute LSRMODE of ud_12 : label is "EDGE";
+ attribute AIL of ud_11 : label is "OFF";
+ attribute LSRMODE of ud_11 : label is "EDGE";
+ attribute AIL of ud_10 : label is "OFF";
+ attribute LSRMODE of ud_10 : label is "EDGE";
+ attribute AIL of ud_9 : label is "OFF";
+ attribute LSRMODE of ud_9 : label is "EDGE";
+ attribute AIL of ud_8 : label is "OFF";
+ attribute LSRMODE of ud_8 : label is "EDGE";
+ attribute AIL of ud_7 : label is "OFF";
+ attribute LSRMODE of ud_7 : label is "EDGE";
+ attribute AIL of ud_6 : label is "OFF";
+ attribute LSRMODE of ud_6 : label is "EDGE";
+ attribute AIL of ud_5 : label is "OFF";
+ attribute LSRMODE of ud_5 : label is "EDGE";
+ attribute AIL of ud_4 : label is "OFF";
+ attribute LSRMODE of ud_4 : label is "EDGE";
+ attribute AIL of ud_3 : label is "OFF";
+ attribute LSRMODE of ud_3 : label is "EDGE";
+ attribute AIL of ud_2 : label is "OFF";
+ attribute LSRMODE of ud_2 : label is "EDGE";
+ attribute AIL of ud_1 : label is "OFF";
+ attribute LSRMODE of ud_1 : label is "EDGE";
+ attribute AIL of ud_0 : label is "OFF";
+ attribute LSRMODE of ud_0 : label is "EDGE";
+ attribute DIV of ucdiv : label is "2";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ ud_15: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data15, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(15), QB0=>Q(31),
+ QA1=>Q(47), QB1=>Q(63), UPDATE=>Update(15), LOCK=>open);
+
+ ud_14: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data14, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(14), QB0=>Q(30),
+ QA1=>Q(46), QB1=>Q(62), UPDATE=>Update(14), LOCK=>open);
+
+ ud_13: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data13, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(13), QB0=>Q(29),
+ QA1=>Q(45), QB1=>Q(61), UPDATE=>Update(13), LOCK=>open);
+
+ ud_12: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data12, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(12), QB0=>Q(28),
+ QA1=>Q(44), QB1=>Q(60), UPDATE=>Update(12), LOCK=>open);
+
+ ud_11: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data11, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(11), QB0=>Q(27),
+ QA1=>Q(43), QB1=>Q(59), UPDATE=>Update(11), LOCK=>open);
+
+ ud_10: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data10, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(10), QB0=>Q(26),
+ QA1=>Q(42), QB1=>Q(58), UPDATE=>Update(10), LOCK=>open);
+
+ ud_9: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data9, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(9), QB0=>Q(25),
+ QA1=>Q(41), QB1=>Q(57), UPDATE=>Update(9), LOCK=>open);
+
+ ud_8: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data8, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(8), QB0=>Q(24),
+ QA1=>Q(40), QB1=>Q(56), UPDATE=>Update(8), LOCK=>open);
+
+ ud_7: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data7, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(7), QB0=>Q(23),
+ QA1=>Q(39), QB1=>Q(55), UPDATE=>Update(7), LOCK=>open);
+
+ ud_6: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data6, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(6), QB0=>Q(22),
+ QA1=>Q(38), QB1=>Q(54), UPDATE=>Update(6), LOCK=>open);
+
+ ud_5: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data5, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(5), QB0=>Q(21),
+ QA1=>Q(37), QB1=>Q(53), UPDATE=>Update(5), LOCK=>open);
+
+ ud_4: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data4, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(4), QB0=>Q(20),
+ QA1=>Q(36), QB1=>Q(52), UPDATE=>Update(4), LOCK=>open);
+
+ ud_3: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data3, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(3), QB0=>Q(19),
+ QA1=>Q(35), QB1=>Q(51), UPDATE=>Update(3), LOCK=>open);
+
+ ud_2: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data2, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(2), QB0=>Q(18),
+ QA1=>Q(34), QB1=>Q(50), UPDATE=>Update(2), LOCK=>open);
+
+ ud_1: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data1, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(1), QB0=>Q(17),
+ QA1=>Q(33), QB1=>Q(49), UPDATE=>Update(1), LOCK=>open);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ ud_0: IDDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (D=>buf_Data0, ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ RSTAIL=>scuba_vlo, RUNAIL=>scuba_vlo, QA0=>Q(0), QB0=>Q(16),
+ QA1=>Q(32), QB1=>Q(48), UPDATE=>Update(0), LOCK=>open);
+
+ ucdiv: CLKDIV
+ -- synopsys translate_off
+ generic map (DIV=> 2)
+ -- synopsys translate_on
+ port map (CLKI=>EClk, LSR=>Rst, CLKO=>SClk_t, ELSR=>ERst);
+
+ buf_Data15_in_inst: IB
+ port map (I=>Data(15), O=>buf_Data15);
+
+ buf_Data14_in_inst: IB
+ port map (I=>Data(14), O=>buf_Data14);
+
+ buf_Data13_in_inst: IB
+ port map (I=>Data(13), O=>buf_Data13);
+
+ buf_Data12_in_inst: IB
+ port map (I=>Data(12), O=>buf_Data12);
+
+ buf_Data11_in_inst: IB
+ port map (I=>Data(11), O=>buf_Data11);
+
+ buf_Data10_in_inst: IB
+ port map (I=>Data(10), O=>buf_Data10);
+
+ buf_Data9_in_inst: IB
+ port map (I=>Data(9), O=>buf_Data9);
+
+ buf_Data8_in_inst: IB
+ port map (I=>Data(8), O=>buf_Data8);
+
+ buf_Data7_in_inst: IB
+ port map (I=>Data(7), O=>buf_Data7);
+
+ buf_Data6_in_inst: IB
+ port map (I=>Data(6), O=>buf_Data6);
+
+ buf_Data5_in_inst: IB
+ port map (I=>Data(5), O=>buf_Data5);
+
+ buf_Data4_in_inst: IB
+ port map (I=>Data(4), O=>buf_Data4);
+
+ buf_Data3_in_inst: IB
+ port map (I=>Data(3), O=>buf_Data3);
+
+ buf_Data2_in_inst: IB
+ port map (I=>Data(2), O=>buf_Data2);
+
+ buf_Data1_in_inst: IB
+ port map (I=>Data(1), O=>buf_Data1);
+
+ buf_Data0_in_inst: IB
+ port map (I=>Data(0), O=>buf_Data0);
+
+ SClk <= SClk_t;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of ddr2_16inputs is
+ for Structure
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:IB use entity SCM.IB(V); end for;
+ for all:IDDRX2A use entity SCM.IDDRX2A(V); end for;
+ for all:CLKDIV use entity SCM.CLKDIV(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module Version: 5.2
+--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n ddr2_3out_clkdiv -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type iol -mode out -width 3 -reg ddr -gear 2 -cdiv -cmode 0 -e
+
+-- Wed Nov 9 17:25:26 2011
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity ddr2_3out_clkdiv is
+ port (
+ Data: in std_logic_vector(11 downto 0);
+ EClk: in std_logic;
+ Rst: in std_logic;
+ SClk: out std_logic;
+ Q: out std_logic_vector(2 downto 0);
+ Update: out std_logic_vector(2 downto 0));
+ attribute dont_touch : boolean;
+ attribute dont_touch of ddr2_3out_clkdiv : entity is true;
+end ddr2_3out_clkdiv;
+
+architecture Structure of ddr2_3out_clkdiv is
+
+ -- internal signal declarations
+ signal ERst: std_logic;
+ signal SClk_t: std_logic;
+ signal buf_Q2: std_logic;
+ signal buf_Q1: std_logic;
+ signal buf_Q0: std_logic;
+
+ -- local component declarations
+ component OB
+ port (I: in std_logic; O: out std_logic);
+ end component;
+ component ODDRX2A
+ -- synopsys translate_off
+ generic (LSRMODE : in String);
+ -- synopsys translate_on
+ port (DA0: in std_logic; DB0: in std_logic; DA1: in std_logic;
+ DB1: in std_logic; ECLK: in std_logic; SCLK: in std_logic;
+ RST: in std_logic; Q: out std_logic;
+ UPDATE: out std_logic);
+ end component;
+ component CLKDIV
+ -- synopsys translate_off
+ generic (DIV : in Integer);
+ -- synopsys translate_on
+ port (CLKI: in std_logic; LSR: in std_logic;
+ CLKO: out std_logic; ELSR: out std_logic);
+ end component;
+ attribute LSRMODE : string;
+ attribute DIV : string;
+ attribute LSRMODE of ud_2 : label is "EDGE";
+ attribute LSRMODE of ud_1 : label is "EDGE";
+ attribute LSRMODE of ud_0 : label is "EDGE";
+ attribute DIV of ucdiv : label is "2";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ ud_2: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(2), DB0=>Data(5), DA1=>Data(8),
+ DB1=>Data(11), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q2, UPDATE=>Update(2));
+
+ ud_1: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(1), DB0=>Data(4), DA1=>Data(7),
+ DB1=>Data(10), ECLK=>EClk, SCLK=>SClk_t, RST=>ERst,
+ Q=>buf_Q1, UPDATE=>Update(1));
+
+ ud_0: ODDRX2A
+ -- synopsys translate_off
+ generic map (LSRMODE=> "EDGE")
+ -- synopsys translate_on
+ port map (DA0=>Data(0), DB0=>Data(3), DA1=>Data(6), DB1=>Data(9),
+ ECLK=>EClk, SCLK=>SClk_t, RST=>ERst, Q=>buf_Q0,
+ UPDATE=>Update(0));
+
+ ucdiv: CLKDIV
+ -- synopsys translate_off
+ generic map (DIV=> 2)
+ -- synopsys translate_on
+ port map (CLKI=>EClk, LSR=>Rst, CLKO=>SClk_t, ELSR=>ERst);
+
+ buf_Q2_out_inst: OB
+ port map (I=>buf_Q2, O=>Q(2));
+
+ buf_Q1_out_inst: OB
+ port map (I=>buf_Q1, O=>Q(1));
+
+ buf_Q0_out_inst: OB
+ port map (I=>buf_Q0, O=>Q(0));
+
+ SClk <= SClk_t;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of ddr2_3out_clkdiv is
+ for Structure
+ for all:OB use entity SCM.OB(V); end for;
+ for all:ODDRX2A use entity SCM.ODDRX2A(V); end for;
+ for all:CLKDIV use entity SCM.CLKDIV(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use ieee.std_logic_arith.all;
+
+entity ddr2_busses is
+ generic (
+ TRIGGER_INPUTS_NUMBER : natural);
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ EDGE_CLK : in std_logic;
+ TRIG_IN : in std_logic_vector(63 downto 0);
+ TRIG_OUT : out std_logic_vector(TRIGGER_INPUTS_NUMBER*4-1 downto 0);
+ FAST_LVDS_TIMING_IN : in std_logic_vector(3 downto 0);
+ FAST_PECL_TIMING_IN : in std_logic_vector(3 downto 0);
+ FAST_MDCA_TIMING_IN : in std_logic_vector(3 downto 0);
+ FAST_MDCB_TIMING_IN : in std_logic_vector(3 downto 0);
+ MULTIPLEXER_IN : in std_logic_vector(7 downto 0);
+ LVDS_TIMING_OUT : out std_logic_vector(11 downto 0);
+ PECL_TIMING_OUT : out std_logic_vector(2 downto 0);
+ START_VETO_STRUCTURE_OUT : out std_logic_vector(23 downto 0);
+ TRIG_CNTRL_IN : in std_logic_vector(7 downto 0)
+ );
+end ddr2_busses;
+
+architecture ddr2_busses of ddr2_busses is
+ component ddr2_4inputs
+ port (
+ Data : in std_logic_vector(3 downto 0);
+ EClk : in std_logic;
+ Rst : in std_logic;
+ SClk : out std_logic;
+ Q : out std_logic_vector(15 downto 0);
+ Update : out std_logic_vector(3 downto 0));
+ end component;
+
+ component ddr2_8inputs
+ port (
+ Data : in std_logic_vector(7 downto 0);
+ EClk : in std_logic;
+ Rst : in std_logic;
+ SClk : out std_logic;
+ Q : out std_logic_vector(31 downto 0);
+ Update : out std_logic_vector(7 downto 0));
+ end component;
+
+ component ddr2_16inputs
+ port (
+ Data : in std_logic_vector(15 downto 0);
+ EClk : in std_logic;
+ Rst : in std_logic;
+ SClk : out std_logic;
+ Q : out std_logic_vector(63 downto 0);
+ Update : out std_logic_vector(15 downto 0));
+ end component;
+
+ component ddr2_32inputs
+ port (
+ Data : in std_logic_vector(31 downto 0);
+ EClk : in std_logic;
+ Rst : in std_logic;
+ SClk : out std_logic;
+ Q : out std_logic_vector(127 downto 0);
+ Update : out std_logic_vector(31 downto 0));
+ end component;
+
+ component fifo16bit_synch
+ port (
+ Data : in std_logic_vector(15 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(15 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+ component dll_edge
+ port (
+ clk : in std_logic;
+ aluhold : in std_logic;
+ clkop : out std_logic;
+ clkos : out std_logic;
+ lock : out std_logic);
+ end component;
+
+ component ddr2_12out_clkdiv
+ port (
+ Data : in std_logic_vector(47 downto 0);
+ EClk : in std_logic;
+ Rst : in std_logic;
+ SClk : out std_logic;
+ Q : out std_logic_vector(11 downto 0);
+ Update : out std_logic_vector(11 downto 0));
+ end component;
+
+ component ddr2_3out_clkdiv
+ port (
+ Data : in std_logic_vector(11 downto 0);
+ EClk : in std_logic;
+ Rst : in std_logic;
+ SClk : out std_logic;
+ Q : out std_logic_vector(2 downto 0);
+ Update : out std_logic_vector(2 downto 0));
+ end component;
+
+ component DCS
+-- synthesis translate_off
+ generic (
+ DCSMODE : string := " POS");
+-- synthesis translate_on
+ PORT (
+ CLK0 : IN std_logic;
+ CLK1 : IN std_logic;
+ SEL : IN std_logic;
+ DCSOUT : OUT std_logic);
+ end component;
+ attribute DCSMODE:string;
+ attribute DCSMODE of DCS_A: label is "POS" ; --no_sim--
+ attribute DCSMODE of DCS_B: label is "POS" ; --no_sim--
+
+ --ddr in
+ signal ddr_outvector : std_logic_vector(64*4-1 downto 0);
+ signal ddr_div_clk : std_logic_vector(15 downto 0);
+ signal ddr_div_clk_op : std_logic_vector(15 downto 0);
+ signal ddr_edge_clk : std_logic_vector(15 downto 0);
+ signal output_from_fifo_sunch_a : std_logic_vector(64*4-1 downto 0);
+ --ddr out
+ signal ddr_in_vector_a : std_logic_vector(16*3-1 downto 0);
+ signal ddr_out_vector_a : std_logic_vector(16*3-1 downto 0);
+
+
+ signal ddr_in_vector_b : std_logic_vector(15 downto 0);
+ signal ddr_out_vector_b : std_logic_vector(15 downto 0);
+
+ signal ddr_div_out_clk : std_logic_vector(1 downto 0);
+ signal fast_trigger_tmp : std_logic_vector(47 downto 0);
+ signal pecl_trigger_tmp : std_logic_vector(11 downto 0);
+
+ signal start_veto_beam_struct_signals : std_logic_vector(63 downto 0);
+
+begin
+
+-- DDR2_32INPUTS_INST_FIRST: ddr2_32inputs --bank 2 and 3 of the FPGA
+-- port map (
+-- Data => TRIG_IN(31 downto 0),
+-- EClk => EDGE_CLK,
+-- Rst => RESET,
+-- SClk => ddr_div_clk(0),
+-- Q => ddr_outvector(32*4-1 downto 0),
+-- Update => open);
+
+ -----------------------------------------------------------------------------
+ -- in DDR
+ -----------------------------------------------------------------------------
+
+ MAKE_DDR_CONNECTIONS: for i in 0 to 3 generate
+ DLL_EDGE_INJECTION_COMPENSATE: dll_edge
+ port map (
+ clk => EDGE_CLK,
+ aluhold => '0',
+ clkop => ddr_div_clk_op(i),
+ clkos => ddr_edge_clk(i),
+ lock => open);
+
+ DDR2_16INPUTS_INST: ddr2_16inputs
+ port map (
+ Data => TRIG_IN((i+1)*16-1 downto i*16),
+ EClk => ddr_edge_clk(i),
+ Rst => RESET,
+ SClk => ddr_div_clk(i),
+ Q => ddr_outvector((i+1)*16*4-1 downto i*16*4),
+ Update => open);
+ end generate MAKE_DDR_CONNECTIONS;
+
+ DDR_SYNCH: for i in 0 to 15 generate
+ FIFO16BIT_SYNCH_A: fifo16bit_synch
+ port map (
+ Data => ddr_outvector((16*(i+1))-1 downto i*16),
+ WrClock => ddr_div_clk(i/4),
+ RdClock => CLK,
+ WrEn => '1',
+ RdEn => '1',
+ Reset => RESET,
+ RPReset => RESET,
+ Q => output_from_fifo_sunch_a((16*(i+1))-1 downto i*16),
+ Empty => open,
+ Full => open,
+ AlmostEmpty => open,
+ AlmostFull => open);
+
+ end generate DDR_SYNCH;
+ --TRIG_OUT arrangment
+ -- 7:0 START
+ -- 15:8 Veto
+ -- 21:16 TOF
+ -- 27:22 RPC
+ -- 36:28 TOF Multiplicicty
+ -- 44:37 Physical triggers
+
+
+ --start in 16 out 3 x 8 (beam shifting by 4 due to the start detector damage) for triggering
+ SELECT_START_SIGNALS_FOR_TRIGGER : process (CLK, RESET) --connector 1 and 2
+ begin
+ if rising_edge(CLK) then
+ case TRIG_CNTRL_IN(7 downto 6) is
+ when b"00" =>
+ TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(8*4-1 downto 0);
+ when b"01" =>
+ TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(12*4-1 downto 4*4);
+ when b"10" =>
+ TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(16*4-1 downto 8*4);
+ when others =>
+ TRIG_OUT(8*4-1 downto 0) <= output_from_fifo_sunch_a(8*4-1 downto 0);
+ end case;
+ end if;
+ end process SELECT_START_SIGNALS_FOR_TRIGGER;
+ --first 32 inputs are used for the START - first 16 for trggering and
+ --histograming next 16 for histograming only
+
+ TRIG_OUT(16*4-1 downto 8*4) <= output_from_fifo_sunch_a(40*4-1 downto 32*4); --veto
+ TRIG_OUT(22*4-1 downto 16*4) <= output_from_fifo_sunch_a(54*4-1 downto 48*4); --TOF
+ TRIG_OUT(26*4-1 downto 22*4) <= output_from_fifo_sunch_a(60*4-1 downto 56*4); --RPC
+ TRIG_OUT(28*4-1 downto 26*4) <= output_from_fifo_sunch_a(63*4-1 downto 61*4); --RPC
+ TRIG_OUT(36*4-1 downto 28*4) <= output_from_fifo_sunch_a(48*4-1 downto 40*4); --PT
+ --veto and PT connector number 3
+ --TOF and RPC connector number 4
+
+ -----------------------------------------------------------------------------
+ -- beam structure (pulses on rising edge made in the beam structure component)
+ -----------------------------------------------------------------------------
+ SET_START_VETO_STRUCT_SIGNALS: for i in 0 to 63 generate
+ SET_HISTOGRAM_SIGNALS_PROC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ start_veto_beam_struct_signals(i) <= '0';
+ elsif output_from_fifo_sunch_a((i+1)*4-1 downto i*4) > 0 then
+ start_veto_beam_struct_signals(i) <= '1';
+ else
+ start_veto_beam_struct_signals(i) <= '0';
+ end if;
+ end if;
+ end process SET_HISTOGRAM_SIGNALS_PROC;
+ end generate SET_START_VETO_STRUCT_SIGNALS;
+
+ SELECT_START_SIGNALS_A : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ case TRIG_CNTRL_IN(1 downto 0) is
+ when b"00" =>
+ START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(7 downto 0);
+ when b"01" =>
+ START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(11 downto 4);
+ when b"10" =>
+ START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(15 downto 8);
+ when others =>
+ START_VETO_STRUCTURE_OUT(7 downto 0) <= start_veto_beam_struct_signals(7 downto 0);
+ end case;
+ end if;
+ end process SELECT_START_SIGNALS_A;
+
+ --this part is for histograming only - perpendicular stripes of the Start
+ --detector. first 16 used for triggering and histograming next only histograming
+ SELECT_START_SIGNALS_B : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ case TRIG_CNTRL_IN(3 downto 2) is
+ when b"00" =>
+ START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(23 downto 16);
+ when b"01" =>
+ START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(27 downto 20);
+ when b"10" =>
+ START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(31 downto 24);
+ when others =>
+ START_VETO_STRUCTURE_OUT(15 downto 8) <= start_veto_beam_struct_signals(23 downto 16);
+ end case;
+ end if;
+ end process SELECT_START_SIGNALS_B;
+
+ START_VETO_STRUCTURE_OUT(23 downto 16) <= start_veto_beam_struct_signals(39 downto 32);
+ --veto histograming
+
+ -----------------------------------------------------------------------------
+ -- out DDR
+ -----------------------------------------------------------------------------
+
+ ddr_in_vector_a <=
+ FAST_LVDS_TIMING_IN & FAST_LVDS_TIMING_IN &
+ MULTIPLEXER_IN &
+ FAST_MDCB_TIMING_IN & FAST_MDCB_TIMING_IN &
+ FAST_MDCA_TIMING_IN & FAST_MDCA_TIMING_IN & FAST_MDCA_TIMING_IN &
+ FAST_LVDS_TIMING_IN & FAST_LVDS_TIMING_IN & FAST_LVDS_TIMING_IN;
+
+-- DLL_EDGE_INJECTION_COMPENSATE_LVDS: dll_edge
+-- port map (
+-- clk => EDGE_CLK,
+-- aluhold => '0',
+-- clkop => open,
+-- clkos => ddr_edge_clk(4),
+-- lock => open);
+ DCS_A: DCS --no_sim--
+-- synthesis translate_off --no_sim--
+ generic map ( --no_sim--
+ DCSMODE => "POS") --no_sim--
+-- synthesis translate_on --no_sim--
+ port map ( --no_sim--
+ SEL => '0', --no_sim--
+ CLK0 => EDGE_CLK, --no_sim--
+ CLK1 => '0', --no_sim--
+ DCSOUT => ddr_edge_clk(4) ); --no_sim--
+
+
+--sim-- ddr_edge_clk(4) <= EDGE_CLK;
+ REWRITE_DDR_DATA_OUT: for i in 0 to 2 generate
+ FIFO16BIT_SYNCH_OUT_A: fifo16bit_synch
+ port map (
+ Data => ddr_in_vector_a((i+1)*16-1 downto i*16),
+ WrClock => CLK,
+ RdClock => ddr_div_out_clk(0),
+ WrEn => '1',
+ RdEn => '1',
+ Reset => RESET,
+ RPReset => RESET,
+ Q => ddr_out_vector_a((i+1)*16-1 downto i*16),
+ Empty => open,
+ Full => open,
+ AlmostEmpty => open,
+ AlmostFull => open);
+ end generate REWRITE_DDR_DATA_OUT;
+
+ DDR2_12OUT_CLKDIV_INST: ddr2_12out_clkdiv
+ port map (
+ Data => ddr_out_vector_a,
+ EClk => ddr_edge_clk(4),
+ Rst => RESET,
+ SClk => ddr_div_out_clk(0),
+ Q => LVDS_TIMING_OUT,
+ Update => open);
+
+-- DLL_EDGE_INJECTION_COMPENSATE_PECL: dll_edge
+-- port map (
+-- clk => EDGE_CLK,
+-- aluhold => '0',
+-- clkop => open,
+-- clkos => ddr_edge_clk(5),
+-- lock => open);
+ DCS_B : DCS --no_sim--
+-- synthesis translate_off --no_sim--
+ generic map ( --no_sim--
+ DCSMODE => "POS") --no_sim--
+-- synthesis translate_on --no_sim--
+ port map ( --no_sim--
+ SEL => '0', --no_sim--
+ CLK0 => EDGE_CLK, --no_sim--
+ CLK1 => '0', --no_sim--
+ DCSOUT => ddr_edge_clk(5) ); --no_sim--
+
+--sim-- ddr_edge_clk(5) <= EDGE_CLK;
+
+ ddr_in_vector_b <= x"0" & FAST_PECL_TIMING_IN & FAST_PECL_TIMING_IN & FAST_PECL_TIMING_IN; --pecl out bank 2
+
+ FIFO16BIT_SYNCH_OUT_B: fifo16bit_synch
+ port map (
+ Data => ddr_in_vector_b,
+ WrClock => CLK,
+ RdClock => ddr_div_clk(0),
+ WrEn => '1',
+ RdEn => '1',
+ Reset => RESET,
+ RPReset => RESET,
+ Q => ddr_out_vector_b,
+ Empty => open,
+ Full => open,
+ AlmostEmpty => open,
+ AlmostFull => open);
+
+ DDR2_3OUT_CLKDIV_INST: ddr2_3out_clkdiv
+ port map (
+ Data => ddr_out_vector_b(11 downto 0),
+ EClk => ddr_edge_clk(0),
+ Rst => RESET,
+ SClk => ddr_div_out_clk(1),
+ Q => PECL_TIMING_OUT,
+ Update => open);
+
+
+end ddr2_busses;
+
+
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use work.version.all;
+use ieee.std_logic_arith.all;
+
+entity ddr_lvl1_trigger is
+ generic (
+ VECTOR_WIDTH : natural
+ );
+ port (
+ RESET : in std_logic;
+ CLK_100 : in std_logic;
+ CLK : in std_logic;
+ CLK_400MHz : in std_logic;
+ CLK_40MHz_OUT : out std_logic;
+ TRIGGER_VECTOR_IN : in std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ FAST_TRIGGER_OUT_LVDS : out std_logic_vector(3 downto 0);
+ FAST_TRIGGER_OUT_PECL : out std_logic_vector(3 downto 0);
+ MDCA_TRIGGER_OUT : out std_logic_vector(3 downto 0);
+ MDCB_TRIGGER_OUT : out std_logic_vector(3 downto 0);
+
+ LVL1_LOGICAL_TRIGG_OUT : out std_logic;
+
+ TRIGGER_IN : in std_logic;
+ CAL_MARKER_IN : in std_logic;
+ TRIGGER_WIDTH_IN : in std_logic_vector(3 downto 0);
+ FAST_TRIGGER_DELAY_IN : in std_logic_vector(3 downto 0);
+ MDCA_TRIGGER_DELAY_IN : in std_logic_vector(4 downto 0);
+ MDCB_TRIGGER_DELAY_IN : in std_logic_vector(4 downto 0);
+
+ LVL1_LOCAL_BUSY_IN : in std_logic;
+ LVL1_TRBNET_BUSY_IN : in std_logic;
+ LVL1_BUSY_OUT : out std_logic;
+ LVL1_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL1_RND_NUMBER_OUT : out std_logic_vector(7 downto 0);
+
+ LVL2_TRBNET_BUSY_IN : in std_logic;
+ LVL2_LOCAL_BUSY_IN : in std_logic;
+ LVL2_TRIGGER_OUT : out std_logic;
+ LVL2_TRIGGER_CODE_OUT : out std_logic_vector(3 downto 0);
+ LVL2_TRIGGER_TAG_OUT : out std_logic_vector(15 downto 0);
+ LVL2_RND_NUMBER_OUT : out std_logic_vector(7 downto 0);
+
+ DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_0 : out std_logic_vector(31 downto 0);
+ DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_1 : out std_logic_vector(31 downto 0);
+ DDR_LVL1_TRIGGER_BUFFER_CTRL_IN_0 : in std_logic_vector(11 downto 0)
+ );
+end ddr_lvl1_trigger;
+
+architecture ddr_lvl1_trigger of ddr_lvl1_trigger is
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+ component trigger_buffer_fifo_1kW
+ port (
+ Data : in std_logic_vector(33 downto 0);
+ Clock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ Q : out std_logic_vector(33 downto 0);
+ WCNT : out std_logic_vector(10 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic);
+ end component;
+
+ component ddr_out
+ port (
+ Data : in std_logic_vector(7 downto 0);
+ EClk : in std_logic;
+ SClk : in std_logic;
+ Rst : in std_logic;
+ Q : out std_logic_vector(0 downto 0);
+ Update : out std_logic_vector(0 downto 0));
+ end component;
+
+ component ddr_out200MHz
+ port (
+ Data : in std_logic_vector(3 downto 0);
+ EClk : in std_logic;
+ SClk : in std_logic;
+ Rst : in std_logic;
+ Q : out std_logic_vector(0 downto 0);
+ Update : out std_logic_vector(0 downto 0));
+ end component;
+
+ component pll_in200_out100
+ port (
+ clk : in std_logic;
+ clkop : out std_logic;
+ clkos : out std_logic;
+ lock : out std_logic);
+ end component;
+
+ component ddr2_11out
+ port (
+ Data : in std_logic_vector(43 downto 0);
+ EClk : in std_logic;
+ SClk : in std_logic;
+ Rst : in std_logic;
+ Q : out std_logic_vector(10 downto 0);
+ Update : out std_logic_vector(10 downto 0));
+ end component;
+
+ component ddr2_3out
+ port (
+ Data : in std_logic_vector(11 downto 0);
+ EClk : in std_logic;
+ SClk : in std_logic;
+ Rst : in std_logic;
+ Q : out std_logic_vector(2 downto 0);
+ Update : out std_logic_vector(2 downto 0));
+ end component;
+
+ component dll_in400_out200
+ port (
+ clk : in std_logic;
+ aluhold : in std_logic;
+ clkop : out std_logic;
+ clkos : out std_logic;
+ lock : out std_logic);
+ end component;
+
+ component fifo16bit_synch
+ port (
+ Data : in std_logic_vector(15 downto 0);
+ WrClock : in std_logic;
+ RdClock : in std_logic;
+ WrEn : in std_logic;
+ RdEn : in std_logic;
+ Reset : in std_logic;
+ RPReset : in std_logic;
+ Q : out std_logic_vector(15 downto 0);
+ Empty : out std_logic;
+ Full : out std_logic;
+ AlmostEmpty : out std_logic;
+ AlmostFull : out std_logic);
+ end component;
+
+
+ --signal edges
+ signal saved_vector_in,leading_edge,trailing_edge : std_logic_vector(VECTOR_WIDTH -1 downto 0);
+
+ --fast trigger
+ signal fast_trigger_fsm,fast_trigger : std_logic_vector(VECTOR_WIDTH -1 downto 0);
+ type fast_trigger_array is array (0 to 7) of std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ signal fast_trigger_sync : fast_trigger_array;
+ type LVL1_FAST_TRIGGER_PULSER is (IDLE, LVL1_FAST_TRIGGER_DELAY, LVL1_FAST_TRIGGER_LEADING, LVL1_FAST_TRIGGER, LVL1_FAST_TRIGGER_TRAILING);
+ signal LVL1_FAST_TRIGGER_PULSER_CURRENT, LVL1_FAST_TRIGGER_PULSER_NEXT : LVL1_FAST_TRIGGER_PULSER;
+ signal delay_for_fast_rst, delay_for_fast_rst_fsm, delay_for_fast_up, delay_for_fast_up_fsm : std_logic;
+ signal delay_for_fast_cntr : std_logic_vector(7 downto 0);
+ signal width_for_fast_rst, width_for_fast_rst_fsm, width_for_fast_up, width_for_fast_up_fsm : std_logic;
+ signal width_for_fast_cntr : std_logic_vector(7 downto 0);
+ signal fast_trigger_tmp : std_logic_vector(11*4-1 downto 0);
+ signal fast_trigger_tmp_b : std_logic_vector(11 downto 0);
+ signal mdc_and_fast_trigger_out : std_logic_vector(10 downto 0);
+ --mdca trigger
+ type mdc_trigger_array is array (0 to 2) of std_logic_vector(VECTOR_WIDTH - 1 downto 0);
+ signal mdca_trigger_sync : mdc_trigger_array;
+ signal mdca_trigger_fsm,mdca_trigger : std_logic_vector(VECTOR_WIDTH-1 downto 0);
+ type LVL1_MDCA_TRIGGER_PULSER is (IDLE, LVL1_MDCA_TRIGGER_DELAY, LVL1_MDCA_TRIGGER_LEADING, LVL1_MDCA_TRIGGER, LVL1_MDCA_TRIGGER_TRAILING);
+ signal LVL1_MDCA_TRIGGER_PULSER_CURRENT, LVL1_MDCA_TRIGGER_PULSER_NEXT : LVL1_MDCA_TRIGGER_PULSER;
+ signal delay_for_mdca_rst, delay_for_mdca_rst_fsm, delay_for_mdca_up, delay_for_mdca_up_fsm : std_logic;
+ signal delay_for_mdca_cntr : std_logic_vector(7 downto 0);
+ signal width_for_mdca_rst, width_for_mdca_rst_fsm, width_for_mdca_up, width_for_mdca_up_fsm : std_logic;
+ signal width_for_mdca_cntr : std_logic_vector(7 downto 0);
+
+ --mdcb trigger
+ signal mdcb_trigger_sync : mdc_trigger_array;
+ signal mdcb_trigger_fsm,mdcb_trigger : std_logic_vector(VECTOR_WIDTH -1 downto 0);
+ type LVL1_MDCB_TRIGGER_PULSER is (IDLE, LVL1_MDCB_TRIGGER_DELAY, LVL1_MDCB_TRIGGER_LEADING, LVL1_MDCB_TRIGGER, LVL1_MDCB_TRIGGER_TRAILING);
+ signal LVL1_MDCB_TRIGGER_PULSER_CURRENT, LVL1_MDCB_TRIGGER_PULSER_NEXT : LVL1_MDCB_TRIGGER_PULSER;
+ signal delay_for_mdcb_rst, delay_for_mdcb_rst_fsm, delay_for_mdcb_up, delay_for_mdcb_up_fsm : std_logic;
+ signal delay_for_mdcb_cntr : std_logic_vector(7 downto 0);
+ signal width_for_mdcb_rst, width_for_mdcb_rst_fsm, width_for_mdcb_up, width_for_mdcb_up_fsm : std_logic;
+ signal width_for_mdcb_cntr : std_logic_vector(7 downto 0);
+
+ --rich trigger
+ signal apv_double_pulse_busy : std_logic := '0';
+
+ --lvl1 busy
+ signal lvl1_busy_source_finished, lvl1_busy_source_finished_pulse,lvl1_busy_marker : std_logic_vector(3 downto 0);
+ signal lvl1_busy_marker_all_and : std_logic;
+ signal not_all_lvl1_busy_or, not_all_lvl1_busy_or_pulse, lvl1_fifo_busy, lvl1_trigger_buffer_busy : std_logic;
+
+ --lvl1 rnd trigger nr
+ signal rnd_counter : std_logic_vector(11 downto 0);
+ signal phys_trigger_in_pulse : std_logic;
+ signal lvl1_trigger_rnd_code_i : std_logic_vector(7 downto 0);
+
+ --counters
+ signal lvl1_trigger_pulse,lvl1_trigger_pulse_sync : std_logic;
+ signal trigg_send_nr, trigg_end_nr : std_logic_vector(7 downto 0);
+
+ --lvl1 tag
+ signal lvl1_trigger_tag : std_logic_vector(15 downto 0);
+
+ --trigger rate
+ signal one_second_reset, event_end_pulse : std_logic;
+ signal one_second_cntr : std_logic_vector(27 downto 0);
+ signal saved_event_rate,event_rate_cntr : std_logic_vector(19 downto 0);
+
+ --lvl2
+ signal lvl2_local_trigger_pulse,not_all_lvl2_busy_or,not_all_lvl2_busy_or_pulse,lvl2_trigger,downscale,lvl2_trigger_buffer_busy,lvl2_trigger_out_i,lvl2_trigger_out_pulse,lvl2_trigger_out_pulse_synch : std_logic;
+ signal lvl2_trigger_code : std_logic_vector(3 downto 0);
+ signal lvl2_trigger_tag : std_logic_vector(15 downto 0);
+ signal downscale_cntr, lvl1_lvl2_diff_cntr: std_logic_vector(7 downto 0);
+ signal trigger_buffer_fifo_data_cntr_a : std_logic_vector(10 downto 0);
+ signal trigger_buffer_fifo_empty_a, trigger_buffer_fifo_full_a : std_logic;
+ signal lvl2_trigger_code_and_tag,lvl2_trigger_code_and_tag_out : std_logic_vector(33 downto 0);
+ constant HOW_MANY_MAX_EVENTS : integer := 254;
+ signal lvl2_trigger_out_pulse_slow,lvl2_trigger_out_pulse_slow_sync_a,lvl2_trigger_out_pulse_slow_sync_b : std_logic;
+
+ --pll for output reference times
+ signal pll_locked : std_logic;
+ signal clk_400_ref_a : std_logic;
+ signal clk_400_ref_b : std_logic;
+begin
+
+-- THE_PLL_FOR_OUT_REF : pll_in200_out100
+-- port map(
+-- CLK => CLK,
+-- CLKOP => open,
+-- CLKOS => clk_400_ref,
+-- LOCK => pll_locked
+-- );
+
+-- DLL_IN400_OUT200_INST_A: dll_in400_out200
+-- port map (
+-- clk => CLK_400MHz,
+-- aluhold => '0',
+-- clkop => clk_400_ref_a,
+-- clkos => open,
+-- lock => open);
+
+-- DLL_IN400_OUT200_INST_B: dll_in400_out200
+-- port map (
+-- clk => CLK_400MHz,
+-- aluhold => '0',
+-- clkop => clk_400_ref_b,
+-- clkos => open,
+-- lock => open);
+
+-- clk_400_ref <= CLK_400MHz;
+
+ VECTOR_IN_WIDTH8: if VECTOR_WIDTH = 8 generate
+ CREATE_EDGES : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ case TRIGGER_VECTOR_IN(7 downto 0) is
+ when x"01" =>
+ leading_edge <= x"ff";
+ trailing_edge <= x"00";
+ when x"02" =>
+ leading_edge <= x"fe";
+ trailing_edge <= x"01";
+ when x"04" =>
+ leading_edge <= x"fc";
+ trailing_edge <= x"03";
+ when x"08" =>
+ leading_edge <= x"f8";
+ trailing_edge <= x"07";
+ when x"10" =>
+ leading_edge <= x"f0";
+ trailing_edge <= x"0f";
+ when x"20" =>
+ leading_edge <= x"e0";
+ trailing_edge <= x"1f";
+ when x"40" =>
+ leading_edge <= x"c0";
+ trailing_edge <= x"3f";
+ when x"80" =>
+ leading_edge <= x"80";
+ trailing_edge <= x"7f";
+ when others =>
+ leading_edge <= x"ff";
+ trailing_edge <= x"00";
+ end case;
+ end if;
+ end process CREATE_EDGES;
+ end generate VECTOR_IN_WIDTH8;
+
+ VECTOR_IN_WIDTH4: if VECTOR_WIDTH = 4 generate
+ CREATE_EDGES : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ case TRIGGER_VECTOR_IN(3 downto 0) is
+ --first bit
+ when x"1" =>
+ leading_edge <= x"f";
+ trailing_edge <= x"0";
+ when x"3" =>
+ leading_edge <= x"f";
+ trailing_edge <= x"0";
+ when x"5" =>
+ leading_edge <= x"f";
+ trailing_edge <= x"0";
+ when x"7" =>
+ leading_edge <= x"f";
+ trailing_edge <= x"0";
+ when x"9" =>
+ leading_edge <= x"f";
+ trailing_edge <= x"0";
+ when x"B" =>
+ leading_edge <= x"f";
+ trailing_edge <= x"0";
+ when x"D" =>
+ leading_edge <= x"f";
+ trailing_edge <= x"0";
+ when x"F" =>
+ leading_edge <= x"f";
+ trailing_edge <= x"0";
+ --2nd bit
+ when x"2" =>
+ leading_edge <= x"e";
+ trailing_edge <= x"1";
+ when x"6" =>
+ leading_edge <= x"e";
+ trailing_edge <= x"1";
+ when x"a" =>
+ leading_edge <= x"e";
+ trailing_edge <= x"1";
+ when x"e" =>
+ leading_edge <= x"e";
+ trailing_edge <= x"1";
+ --3rd bit
+ when x"4" =>
+ leading_edge <= x"c";
+ trailing_edge <= x"3";
+ when x"c" =>
+ leading_edge <= x"c";
+ trailing_edge <= x"3";
+ --4th bit
+ when x"8" =>
+ leading_edge <= x"8";
+ trailing_edge <= x"7";
+
+ when others =>
+ leading_edge <= x"f";
+ trailing_edge <= x"0";
+ end case;
+ end if;
+ end process CREATE_EDGES;
+ end generate VECTOR_IN_WIDTH4;
+
+
+-------------------------------------------------------------------------------
+-- FAST TRIGGER
+-------------------------------------------------------------------------------
+ LVL1_FAST_TRIGGER_PULSER_CLOCK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL1_FAST_TRIGGER_PULSER_CURRENT <= IDLE;
+ fast_trigger <= (others => '0');
+ delay_for_fast_rst <= '1';
+ delay_for_fast_up <= '0';
+ width_for_fast_rst <= '1';
+ width_for_fast_up <= '0';
+ else
+ LVL1_FAST_TRIGGER_PULSER_CURRENT <= LVL1_FAST_TRIGGER_PULSER_NEXT;
+ fast_trigger <= fast_trigger_fsm;
+ delay_for_fast_rst <= delay_for_fast_rst_fsm;
+ delay_for_fast_up <= delay_for_fast_up_fsm;
+ width_for_fast_rst <= width_for_fast_rst_fsm;
+ width_for_fast_up <= width_for_fast_up_fsm;
+ end if;
+ end if;
+ end process LVL1_FAST_TRIGGER_PULSER_CLOCK;
+
+ LVL1_FAST_TRIGGER_PULSER_PROC : process (CLK)
+ begin
+ fast_trigger_fsm <= (others => '0');
+ delay_for_fast_rst_fsm <= '1';
+ delay_for_fast_up_fsm <= '0';
+ width_for_fast_rst_fsm <= '1';
+ width_for_fast_up_fsm <= '0';
+ case (LVL1_FAST_TRIGGER_PULSER_CURRENT) is
+
+ when IDLE =>
+ if TRIGGER_IN = '1' and CAL_MARKER_IN = '0' then
+ LVL1_FAST_TRIGGER_PULSER_NEXT <= LVL1_FAST_TRIGGER_DELAY;
+ else
+ LVL1_FAST_TRIGGER_PULSER_NEXT <= IDLE;
+ end if;
+
+ when LVL1_FAST_TRIGGER_DELAY =>
+ delay_for_fast_rst_fsm <= '0';
+ delay_for_fast_up_fsm <= '1';
+ if delay_for_fast_cntr(4 downto 1) = FAST_TRIGGER_DELAY_IN then
+ LVL1_FAST_TRIGGER_PULSER_NEXT <= LVL1_FAST_TRIGGER_LEADING;
+ else
+ LVL1_FAST_TRIGGER_PULSER_NEXT <= LVL1_FAST_TRIGGER_DELAY;
+ end if;
+
+ when LVL1_FAST_TRIGGER_LEADING =>
+ fast_trigger_fsm <= leading_edge;
+ LVL1_FAST_TRIGGER_PULSER_NEXT <= LVL1_FAST_TRIGGER;
+
+ when LVL1_FAST_TRIGGER =>
+ width_for_fast_rst_fsm <= '0';
+ width_for_fast_up_fsm <= '1';
+ fast_trigger_fsm <= (others => '1');
+ if ((width_for_fast_cntr(4 downto 1) = (TRIGGER_WIDTH_IN + 9)) and (TRIGGER_WIDTH_IN < 7)) or ((width_for_fast_cntr = (TRIGGER_WIDTH_IN)) and (TRIGGER_WIDTH_IN > 6)) then
+ LVL1_FAST_TRIGGER_PULSER_NEXT <= LVL1_FAST_TRIGGER_TRAILING;
+ else
+ LVL1_FAST_TRIGGER_PULSER_NEXT <= LVL1_FAST_TRIGGER;
+ end if;
+
+ when LVL1_FAST_TRIGGER_TRAILING =>
+ fast_trigger_fsm <= trailing_edge;
+ LVL1_FAST_TRIGGER_PULSER_NEXT <= IDLE;
+
+ when others =>
+ LVL1_FAST_TRIGGER_PULSER_NEXT <= IDLE;
+ end case;
+ end process LVL1_FAST_TRIGGER_PULSER_PROC;
+
+ MAKE_INDIVIDUAL_FAST_TRIGGERS: for i in 0 to 7 generate
+ SYNC_FAST_TRIGGER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ fast_trigger_sync(i) <= x"0";
+ else
+ fast_trigger_sync(i) <= fast_trigger;
+ end if;
+ end if;
+ end process SYNC_FAST_TRIGGER;
+ end generate MAKE_INDIVIDUAL_FAST_TRIGGERS;
+
+
+ DELAY_CNTR_FOR_FAST: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => delay_for_fast_rst,
+ COUNT_OUT => delay_for_fast_cntr,
+ UP_IN => delay_for_fast_up,
+ DOWN_IN => '0');
+
+ WIDTH_CNTR_FOR_FAST: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => width_for_fast_rst,
+ COUNT_OUT => width_for_fast_cntr,
+ UP_IN => width_for_fast_up,
+ DOWN_IN => '0');
+
+-- OUT_WIDTH8_FAST : if VECTOR_WIDTH = 8 generate
+-- FAST_TRIGG_OUT_GEN_A: for i in 0 to 9 generate
+-- FAST_DDR_OUT : ddr_out
+-- port map (
+-- Data => fast_trigger,
+-- EClk => clk_400_ref,--CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => FAST_TRIGGER_OUT(i downto i),
+-- Update => open);
+-- end generate FAST_TRIGG_OUT_GEN_A;
+-- end generate OUT_WIDTH8_FAST;
+
+-- OUT_WIDTH4_FAST : if VECTOR_WIDTH = 4 generate
+-- FAST_TRIGG_OUT_GEN_B: for i in 0 to 7 generate
+-- FAST_DDR_OUT : ddr_out200MHz
+-- port map (
+-- Data => fast_trigger_sync(i),
+-- EClk => clk_400_ref,--CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => FAST_TRIGGER_OUT(i downto i),
+-- Update => open);
+-- end generate FAST_TRIGG_OUT_GEN_B;
+-- end generate OUT_WIDTH4_FAST;
+-- fifo16bit_synch_1: fifo16bit_synch
+-- port map (
+-- Data => Data,
+-- WrClock => WrClock,
+-- RdClock => RdClock,
+-- WrEn => WrEn,
+-- RdEn => RdEn,
+-- Reset => Reset,
+-- RPReset => RPReset,
+-- Q => Q,
+-- Empty => Empty,
+-- Full => Full,
+-- AlmostEmpty => AlmostEmpty,
+-- AlmostFull => AlmostFull);
+
+
+-- ddr2_11out_1: ddr2_11out
+-- port map (
+-- Data => fast_trigger_tmp,
+-- EClk => clk_400_ref_a,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => mdc_and_fast_trigger_out,
+-- Update => open);
+
+-- fast_trigger_tmp_b <= fast_trigger_sync(3) & fast_trigger_sync(2) & fast_trigger_sync(1);
+-- ddr2_3out_1: ddr2_3out
+-- port map (
+-- Data => fast_trigger_tmp_b,
+-- EClk => clk_400_ref_b,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => FAST_TRIGGER_OUT(2 downto 0),
+-- Update => open);
+
+-- DDR_OUT_CONNECTION: for i in 0 to 10 generate
+-- START_SIGNALS: if i<5 generate
+-- fast_trigger_tmp((i+1)*4-1 downto i*4) <= fast_trigger_sync(0);
+-- end generate START_SIGNALS;
+-- MDCA_CONN: if i>4 and i<8 generate
+-- fast_trigger_tmp((i+1)*4-1 downto i*4) <= mdca_trigger;
+-- end generate MDCA_CONN;
+
+-- MDCA_CONN: if i>7 and i<10 generate
+-- fast_trigger_tmp((i+1)*4-1 downto i*4) <= mdcb_trigger;
+-- end generate MDCA_CONN;
+
+-- MDCB_CONN: if i=10 generate
+-- fast_trigger_tmp((i+1)*4-1 downto i*4) <= fast_trigger_sync(0);
+-- end generate MDCB_CONN;
+-- end generate DDR_OUT_CONNECTION;
+
+
+ FAST_TRIGGER_OUT_LVDS <= fast_trigger_sync(0);
+ FAST_TRIGGER_OUT_PECL <= fast_trigger_sync(1);
+ MDCA_TRIGGER_OUT <= mdca_trigger;
+ MDCB_TRIGGER_OUT <= mdcb_trigger;
+
+
+ LVL_LOGICAL_TRIG_SYNC : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_trigger_pulse_sync <= '0';
+ else
+ lvl1_trigger_pulse_sync <= lvl1_trigger_pulse;
+ end if;
+ end if;
+ end process LVL_LOGICAL_TRIG_SYNC;
+ LVL1_LOGICAL_TRIGG_OUT <= lvl1_trigger_pulse_sync; --or of physical trigger and cal
+-------------------------------------------------------------------------------
+-- MDCA TRIGGER
+-------------------------------------------------------------------------------
+ LVL1_MDCA_TRIGGER_PULSER_CLOCK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL1_MDCA_TRIGGER_PULSER_CURRENT <= IDLE;
+ mdca_trigger <= (others => '0');
+ delay_for_mdca_rst <= '1';
+ delay_for_mdca_up <= '0';
+ width_for_mdca_rst <= '1';
+ width_for_mdca_up <= '0';
+ else
+ LVL1_MDCA_TRIGGER_PULSER_CURRENT <= LVL1_MDCA_TRIGGER_PULSER_NEXT;
+ mdca_trigger <= mdca_trigger_fsm;
+ delay_for_mdca_rst <= delay_for_mdca_rst_fsm;
+ delay_for_mdca_up <= delay_for_mdca_up_fsm;
+ width_for_mdca_rst <= width_for_mdca_rst_fsm;
+ width_for_mdca_up <= width_for_mdca_up_fsm;
+ end if;
+ end if;
+ end process LVL1_MDCA_TRIGGER_PULSER_CLOCK;
+
+ LVL1_MDCA_TRIGGER_PULSER_PROC : process (CLK)
+ begin
+ mdca_trigger_fsm <= (others => '0');
+ delay_for_mdca_rst_fsm <= '1';
+ delay_for_mdca_up_fsm <= '0';
+ width_for_mdca_rst_fsm <= '1';
+ width_for_mdca_up_fsm <= '0';
+ case (LVL1_MDCA_TRIGGER_PULSER_CURRENT) is
+
+ when IDLE =>
+ if TRIGGER_IN = '1' and CAL_MARKER_IN = '0' then
+ LVL1_MDCA_TRIGGER_PULSER_NEXT <= LVL1_MDCA_TRIGGER_DELAY;
+ else
+ LVL1_MDCA_TRIGGER_PULSER_NEXT <= IDLE;
+ end if;
+
+ when LVL1_MDCA_TRIGGER_DELAY =>
+ delay_for_mdca_rst_fsm <= '0';
+ delay_for_mdca_up_fsm <= '1';
+ if delay_for_mdca_cntr(6 downto 2) = MDCA_TRIGGER_DELAY_IN then
+ LVL1_MDCA_TRIGGER_PULSER_NEXT <= LVL1_MDCA_TRIGGER_LEADING;
+ else
+ LVL1_MDCA_TRIGGER_PULSER_NEXT <= LVL1_MDCA_TRIGGER_DELAY;
+ end if;
+
+ when LVL1_MDCA_TRIGGER_LEADING =>
+ mdca_trigger_fsm <= leading_edge;
+ LVL1_MDCA_TRIGGER_PULSER_NEXT <= LVL1_MDCA_TRIGGER;
+
+ when LVL1_MDCA_TRIGGER =>
+ width_for_mdca_rst_fsm <= '0';
+ width_for_mdca_up_fsm <= '1';
+ mdca_trigger_fsm <= (others => '1');
+ if ((width_for_mdca_cntr(4 downto 1) = (TRIGGER_WIDTH_IN + 9)) and (TRIGGER_WIDTH_IN < 7)) or ((width_for_mdca_cntr = (TRIGGER_WIDTH_IN)) and (TRIGGER_WIDTH_IN > 6)) then
+ LVL1_MDCA_TRIGGER_PULSER_NEXT <= LVL1_MDCA_TRIGGER_TRAILING;
+ else
+ LVL1_MDCA_TRIGGER_PULSER_NEXT <= LVL1_MDCA_TRIGGER;
+ end if;
+
+ when LVL1_MDCA_TRIGGER_TRAILING =>
+ mdca_trigger_fsm <= trailing_edge;
+ LVL1_MDCA_TRIGGER_PULSER_NEXT <= IDLE;
+
+ when others =>
+ LVL1_MDCA_TRIGGER_PULSER_NEXT <= IDLE;
+ end case;
+ end process LVL1_MDCA_TRIGGER_PULSER_PROC;
+
+ DELAY_CNTR_FOR_MDCA: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => delay_for_mdca_rst,
+ COUNT_OUT => delay_for_mdca_cntr,
+ UP_IN => delay_for_mdca_up,
+ DOWN_IN => '0');
+
+ WIDTH_CNTR_FOR_MDCA: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => width_for_mdca_rst,
+ COUNT_OUT => width_for_mdca_cntr,
+ UP_IN => width_for_mdca_up,
+ DOWN_IN => '0');
+
+ MAKE_INDIVIDUAL_MDCA_TRIGGERS: for i in 0 to 2 generate
+ SYNC_MDCA_TRIGGER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ mdca_trigger_sync(i) <= x"0";
+ else
+ mdca_trigger_sync(i) <= mdca_trigger;
+ end if;
+ end if;
+ end process SYNC_MDCA_TRIGGER;
+ end generate MAKE_INDIVIDUAL_MDCA_TRIGGERS;
+
+-- OUT_WIDTH8_MDCA: if VECTOR_WIDTH = 8 generate
+-- MDCA_DDR_OUT_A: for i in 0 to 2 generate
+-- MDCA_DDR_OUT: ddr_out
+-- port map (
+-- Data => mdca_trigger,
+-- EClk => clk_400_ref,--CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => MDCA_TRIGGER_OUT(i downto i),
+-- Update => open);
+-- end generate MDCA_DDR_OUT_A;
+-- end generate OUT_WIDTH8_MDCA;
+
+
+-- OUT_WIDTH4_MDCA: if VECTOR_WIDTH = 4 generate
+-- MDCA_DDR_OUT_B: for i in 0 to 2 generate
+-- MDCA_DDR_OUT: ddr_out200MHz
+-- port map (
+-- Data => mdca_trigger_sync(i),
+-- EClk => clk_400_ref,--CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => MDCA_TRIGGER_OUT(i downto i),
+-- Update => open);
+-- end generate MDCA_DDR_OUT_B;
+-- end generate OUT_WIDTH4_MDCA;
+
+-------------------------------------------------------------------------------
+-- MDCB TRIGGER
+-------------------------------------------------------------------------------
+ LVL1_MDCB_TRIGGER_PULSER_CLOCK : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ LVL1_MDCB_TRIGGER_PULSER_CURRENT <= IDLE;
+ mdcb_trigger <= (others => '0');
+ delay_for_mdcb_rst <= '1';
+ delay_for_mdcb_up <= '0';
+ width_for_mdcb_rst <= '1';
+ width_for_mdcb_up <= '0';
+ else
+ LVL1_MDCB_TRIGGER_PULSER_CURRENT <= LVL1_MDCB_TRIGGER_PULSER_NEXT;
+ mdcb_trigger <= mdcb_trigger_fsm;
+ delay_for_mdcb_rst <= delay_for_mdcb_rst_fsm;
+ delay_for_mdcb_up <= delay_for_mdcb_up_fsm;
+ width_for_mdcb_rst <= width_for_mdcb_rst_fsm;
+ width_for_mdcb_up <= width_for_mdcb_up_fsm;
+ end if;
+ end if;
+ end process LVL1_MDCB_TRIGGER_PULSER_CLOCK;
+
+ LVL1_MDCB_TRIGGER_PULSER_PROC : process (CLK)
+ begin
+ mdcb_trigger_fsm <= (others => '0');
+ delay_for_mdcb_rst_fsm <= '1';
+ delay_for_mdcb_up_fsm <= '0';
+ width_for_mdcb_rst_fsm <= '1';
+ width_for_mdcb_up_fsm <= '0';
+ case (LVL1_MDCB_TRIGGER_PULSER_CURRENT) is
+
+ when IDLE =>
+ if TRIGGER_IN = '1' and CAL_MARKER_IN = '0' then
+ LVL1_MDCB_TRIGGER_PULSER_NEXT <= LVL1_MDCB_TRIGGER_DELAY;
+ else
+ LVL1_MDCB_TRIGGER_PULSER_NEXT <= IDLE;
+ end if;
+
+ when LVL1_MDCB_TRIGGER_DELAY =>
+ delay_for_mdcb_rst_fsm <= '0';
+ delay_for_mdcb_up_fsm <= '1';
+ if delay_for_mdcb_cntr(6 downto 2) = MDCB_TRIGGER_DELAY_IN then
+ LVL1_MDCB_TRIGGER_PULSER_NEXT <= LVL1_MDCB_TRIGGER_LEADING;
+ else
+ LVL1_MDCB_TRIGGER_PULSER_NEXT <= LVL1_MDCB_TRIGGER_DELAY;
+ end if;
+
+ when LVL1_MDCB_TRIGGER_LEADING =>
+ mdcb_trigger_fsm <= leading_edge;
+ LVL1_MDCB_TRIGGER_PULSER_NEXT <= LVL1_MDCB_TRIGGER;
+
+ when LVL1_MDCB_TRIGGER =>
+ width_for_mdcb_rst_fsm <= '0';
+ width_for_mdcb_up_fsm <= '1';
+ mdcb_trigger_fsm <= (others => '1');
+ if ((width_for_mdcb_cntr(4 downto 1) = (TRIGGER_WIDTH_IN + 9)) and (TRIGGER_WIDTH_IN < 7)) or ((width_for_mdcb_cntr = (TRIGGER_WIDTH_IN)) and (TRIGGER_WIDTH_IN > 6)) then
+ LVL1_MDCB_TRIGGER_PULSER_NEXT <= LVL1_MDCB_TRIGGER_TRAILING;
+ else
+ LVL1_MDCB_TRIGGER_PULSER_NEXT <= LVL1_MDCB_TRIGGER;
+ end if;
+
+ when LVL1_MDCB_TRIGGER_TRAILING =>
+ mdcb_trigger_fsm <= trailing_edge;
+ LVL1_MDCB_TRIGGER_PULSER_NEXT <= IDLE;
+
+ when others =>
+ LVL1_MDCB_TRIGGER_PULSER_NEXT <= IDLE;
+ end case;
+ end process LVL1_MDCB_TRIGGER_PULSER_PROC;
+
+ DELAY_CNTR_FOR_MDCB: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => delay_for_mdcb_rst,
+ COUNT_OUT => delay_for_mdcb_cntr,
+ UP_IN => delay_for_mdcb_up,
+ DOWN_IN => '0');
+
+ WIDTH_CNTR_FOR_MDCB: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => width_for_mdcb_rst,
+ COUNT_OUT => width_for_mdcb_cntr,
+ UP_IN => width_for_mdcb_up,
+ DOWN_IN => '0');
+
+ MAKE_INDIVIDUAL_MDCB_TRIGGERS: for i in 0 to 2 generate
+ SYNC_MDCB_TRIGGER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ mdcb_trigger_sync(i) <= x"0";
+ else
+ mdcb_trigger_sync(i) <= mdcb_trigger;
+ end if;
+ end if;
+ end process SYNC_MDCB_TRIGGER;
+ end generate MAKE_INDIVIDUAL_MDCB_TRIGGERS;
+
+-- OUT_WIDTH8_MDCB: if VECTOR_WIDTH = 8 generate
+-- MDCB_DDR_OUT_A: for i in 0 to 1 generate
+-- MDCB_DDR_OUT: ddr_out
+-- port map (
+-- Data => mdcb_trigger,
+-- EClk => clk_400_ref,--CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => MDCB_TRIGGER_OUT(i downto i),
+-- Update => open);
+-- end generate MDCB_DDR_OUT_A;
+-- end generate OUT_WIDTH8_MDCB;
+
+
+-- OUT_WIDTH4_MDCB: if VECTOR_WIDTH = 4 generate
+-- MDCB_DDR_OUT_B: for i in 0 to 1 generate
+-- MDCB_DDR_OUT: ddr_out200MHz
+-- port map (
+-- Data => mdcb_trigger_sync(i),
+-- EClk => clk_400_ref,--CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => MDCB_TRIGGER_OUT(i downto i),
+-- Update => open);
+-- end generate MDCB_DDR_OUT_B;
+-- end generate OUT_WIDTH4_MDCB;
+
+
+-------------------------------------------------------------------------------
+-- RICH TRIGGER ask MB about details
+-------------------------------------------------------------------------------
+-- THE_TRIGGER_EDGE_TO_PULSE_FOR_APV: edge_to_pulse
+-- port map (
+-- clock => CLK40_IN,
+-- en_clk => '1',
+-- signal_in => lvl1_timing_trigger,
+-- pulse => lvl1_timing_trigger_pulse
+-- );
+
+-- THE_DOUBLE_EDGE_TO_PULSE_FOR_APV: edge_to_pulse
+-- port map (
+-- clock => CLK40_IN,
+-- en_clk => '1',
+-- signal_in => TRIGGER_BUFFER_CTRL_IN_0(31),
+-- pulse => double_apv_pulse_source
+-- );
+
+-- APV_PULSE_FSM_CLOCK : process (CLK40_IN, RESET)
+-- begin
+-- if rising_edge(CLK40_IN) then
+-- if RESET = '1' then
+-- APV_PULSE_FSM_CURRENT <= IDLE;
+-- apv_double_pulse <= '0';
+-- apv_double_pulse_busy <= '0';
+-- else
+-- APV_PULSE_FSM_CURRENT <= APV_PULSE_FSM_NEXT;
+-- apv_double_pulse <= apv_double_pulse_fsm;
+-- apv_double_pulse_busy <= apv_double_pulse_busy_fsm;
+-- end if;
+-- end if;
+-- end process APV_PULSE_FSM_CLOCK;
+
+-- APV_PULSE_FSM_PROC : process (CLK40_IN)
+-- begin
+-- apv_double_pulse_fsm <= '0';
+-- apv_double_pulse_busy_fsm <= '1';
+-- case (APV_PULSE_FSM_CURRENT) is
+-- when IDLE =>
+-- apv_double_pulse_busy_fsm <= '0';
+-- if double_apv_pulse_source = '1' then
+-- APV_PULSE_FSM_NEXT <= APV_PULSE_FSM_A;
+-- else
+-- APV_PULSE_FSM_NEXT <= IDLE;
+-- end if;
+-- when APV_PULSE_FSM_A =>
+-- if lvl1_timing_trigger = '0' and lvl1_trigger = '0' then
+-- APV_PULSE_FSM_NEXT <= APV_PULSE_FSM_B;
+-- else
+-- APV_PULSE_FSM_NEXT <= APV_PULSE_FSM_A;
+-- end if;
+-- when APV_PULSE_FSM_B =>
+-- apv_double_pulse_fsm <= '1';
+-- APV_PULSE_FSM_NEXT <= APV_PULSE_FSM_C;
+-- when APV_PULSE_FSM_C =>
+-- APV_PULSE_FSM_NEXT <= APV_PULSE_FSM_D;
+-- when APV_PULSE_FSM_D =>
+-- apv_double_pulse_fsm <= '1';
+-- APV_PULSE_FSM_NEXT <= IDLE;
+-- when others =>
+-- APV_PULSE_FSM_NEXT <= IDLE;
+-- end case;
+-- end process APV_PULSE_FSM_PROC;
+
+-- SEND_APV_PULSE : process (CLK40_IN, RESET)
+-- begin
+-- if rising_edge(CLK40_IN) then
+-- if RESET = '1' then
+-- LVL1_APV_TRIGGER_OUT <= '0';
+-- else
+-- LVL1_APV_TRIGGER_OUT <= lvl1_timing_trigger_pulse or apv_double_pulse_fsm;
+-- end if;
+-- end if;
+-- end process SEND_APV_PULSE;
+-- RICH_DDR_OUT_WIDTH8: if VECTOR_WIDTH = 8 generate
+-- RICH_DDR_OUT_A: ddr_out
+-- port map (
+-- Data => fast_trigger,
+-- EClk => clk_400_ref,--CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => RICH_APV_TRIGGER_OUT,
+-- Update => open);
+-- end generate RICH_DDR_OUT_WIDTH8;
+
+-- RICH_DDR_OUT_WIDTH4: if VECTOR_WIDTH = 4 generate
+-- RICH_DDR_OUT_B: ddr_out200MHz
+-- port map (
+-- Data => fast_trigger,
+-- EClk => clk_400_ref,--CLK_400MHz,
+-- SClk => CLK,
+-- Rst => RESET,
+-- Q => RICH_APV_TRIGGER_OUT,
+-- Update => open);
+-- end generate RICH_DDR_OUT_WIDTH4;
+
+-----------------------------------------------------------------------------
+-- LVL1 BUSY
+-----------------------------------------------------------------------------
+ lvl1_busy_source_finished(0) <= not LVL1_TRBNET_BUSY_IN;
+-- lvl1_busy_source_finished(1) <= not lvl1_fifo_busy or ;
+ lvl1_busy_source_finished(1) <= not LVL1_LOCAL_BUSY_IN;
+-- lvl1_busy_source_finished(3) <= not lvl1_fifo_busy;
+-- lvl1_busy_source_finished(1) <= not lvl1_trigger_buffer_busy ;
+
+ BUSY_FINISHED_MARKERS: for i in 0 to 1 generate
+
+ LVL1_BUSY_END: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => lvl1_busy_source_finished(i),
+ pulse => lvl1_busy_source_finished_pulse(i)
+ );
+
+ BUSY_END_MARKER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or lvl1_busy_marker_all_and = '1' then
+ lvl1_busy_marker(i) <= '0';
+ elsif lvl1_busy_source_finished_pulse(i) = '1' then
+ lvl1_busy_marker(i) <= '1';
+ else
+ lvl1_busy_marker(i) <= lvl1_busy_marker(i);
+ end if;
+ end if;
+ end process BUSY_END_MARKER;
+
+ end generate BUSY_FINISHED_MARKERS;
+
+ lvl1_busy_marker_all_and <= lvl1_busy_marker(0) and lvl1_busy_marker(1);-- and lvl1_busy_marker(2);
+
+ BUSY_OR : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ not_all_lvl1_busy_or <= '0';
+ else
+ not_all_lvl1_busy_or <= lvl1_busy_marker_all_and;--
+ --and lvl1_busy_marker(3);
+ end if;
+ end if;
+ end process BUSY_OR;
+
+ END_BUSY_PULSER: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_all_lvl1_busy_or,
+ pulse => not_all_lvl1_busy_or_pulse
+ );
+
+ SET_FIFO_BUSY : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_fifo_busy <= '0';
+ elsif lvl1_lvl2_diff_cntr > HOW_MANY_MAX_EVENTS then
+ lvl1_fifo_busy <= '1';
+ else
+ lvl1_fifo_busy <= '0';
+ end if;
+ end if;
+ end process SET_FIFO_BUSY;
+
+ SET_TRIGGER_BUFFER_BUSY : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or not_all_lvl1_busy_or_pulse = '1' then
+ lvl1_trigger_buffer_busy <= '0';
+ elsif TRIGGER_IN = '1' then --and lvl1_lvl2_diff_cntr < HOW_MANY_MAX_EVENTS then
+ lvl1_trigger_buffer_busy <= '1';
+ else
+ lvl1_trigger_buffer_busy <= lvl1_trigger_buffer_busy;
+ end if;
+ end if;
+ end process SET_TRIGGER_BUFFER_BUSY;
+ LVL1_BUSY_OUT <= lvl1_trigger_buffer_busy or LVL2_TRBNET_BUSY_IN;
+
+
+-------------------------------------------------------------------------------
+-- LVL1 TRIGGER RND NUMBER
+-------------------------------------------------------------------------------
+ RANDOM_NUMBER_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 12)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ COUNT_OUT => rnd_counter,
+ UP_IN => '1',
+ DOWN_IN => '0');
+
+ PHYS_TRIGG_PULSE: edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => TRIGGER_IN,
+ pulse => phys_trigger_in_pulse
+ );
+
+ SET_RND_LVL1_TRIGGER : process (CLK,lvl1_lvl2_diff_cntr)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ lvl1_trigger_rnd_code_i <= (others => '0');
+ elsif phys_trigger_in_pulse = '1' then
+ lvl1_trigger_rnd_code_i <= rnd_counter(4) & rnd_counter(9) & rnd_counter(1) & rnd_counter(6) & rnd_counter(11) & rnd_counter(5) & rnd_counter(2) & rnd_counter(7);
+ else
+ lvl1_trigger_rnd_code_i <= lvl1_trigger_rnd_code_i;
+ end if;
+ end if;
+ end process SET_RND_LVL1_TRIGGER;
+ LVL1_RND_NUMBER_OUT <= lvl1_trigger_rnd_code_i;
+
+-------------------------------------------------------------------------------
+-- COUNTERS
+-------------------------------------------------------------------------------
+ lvl1_trigger_pulse <= phys_trigger_in_pulse;
+ COUNT_START_TRIGG: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ COUNT_OUT => trigg_send_nr, --started
+ UP_IN => lvl1_trigger_pulse,
+ DOWN_IN => '0');
+
+ COUNT_END_TRIGG: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 8)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ COUNT_OUT => trigg_end_nr, --ended
+ UP_IN => not_all_lvl1_busy_or_pulse,
+ DOWN_IN => '0');
+
+ ------------------------------------------------------------------------------
+ -- LVL1 TAG
+ ------------------------------------------------------------------------------
+
+ LVL1_TAG_CNTR: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 16)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ COUNT_OUT => lvl1_trigger_tag,
+ UP_IN => not_all_lvl1_busy_or_pulse,
+ DOWN_IN => '0');
+
+ LVL1_TRIGGER_TAG_OUT <= lvl1_trigger_tag;
+--a0100001
+ DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_0 <= lvl1_trigger_rnd_code_i & apv_double_pulse_busy & LVL1_LOCAL_BUSY_IN & LVL1_TRBNET_BUSY_IN & lvl1_trigger_buffer_busy & event_rate_cntr(15) & event_rate_cntr(13) & trigger_buffer_fifo_empty_a & trigger_buffer_fifo_full_a & lvl1_trigger_tag;--trigg_send_nr trigg_end_nr & ;--lvl1_trigger_tag;
+
+
+-------------------------------------------------------------------------------
+-- TRIGGER RATE
+-------------------------------------------------------------------------------
+ THE_ONE_SECOND_COUNTER: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 28)
+ port map (
+ CLK => CLK,
+ RESET => one_second_reset,
+ COUNT_OUT => one_second_cntr,
+ UP_IN => '1',
+ DOWN_IN => '0');
+
+ SET_RESET_EACH_ONE_SECOND : process (CLK, RESET) --and save event rate
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ one_second_reset <= '1';
+ saved_event_rate <= (others => '0');
+ elsif one_second_cntr = x"BEBC200" then
+ one_second_reset <= '1';
+ saved_event_rate <= event_rate_cntr;
+ else
+ one_second_reset <= '0';
+ saved_event_rate <= saved_event_rate;
+ end if;
+ end if;
+ end process SET_RESET_EACH_ONE_SECOND;
+
+ LOCAL_CLK_EVENT_END_PULSE : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => not_all_lvl1_busy_or_pulse, --busy finished
+ pulse => event_end_pulse);
+
+ TRIGGER_COUNTER_RATE: up_down_counter
+ generic map (
+ NUMBER_OF_BITS => 20)
+ port map (
+ CLK => CLK,
+ RESET => one_second_reset,
+ COUNT_OUT => event_rate_cntr,
+ UP_IN => event_end_pulse,
+ DOWN_IN => '0');
+
+ DDR_LVL1_TRIGGER_BUFFER_STASUS_0UT_1 <= lvl1_lvl2_diff_cntr & '0' & LVL2_LOCAL_BUSY_IN & LVL2_TRBNET_BUSY_IN & lvl2_trigger_buffer_busy & saved_event_rate;
+
+
+end ddr_lvl1_trigger;
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 4.7
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n delay_fifo -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -sync_mode -depth 128 -width 32 -regout -no_enable -pe -1 -pf -1 -fill -e
+
+-- Fri Sep 3 11:15:46 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity delay_fifo is
+ port (
+ Data: in std_logic_vector(31 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ WCNT: out std_logic_vector(7 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end delay_fifo;
+
+architecture Structure of delay_fifo is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal rden_i_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co3: std_logic;
+ signal cnt_con: std_logic;
+ signal co2: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal co2_1: std_logic;
+ signal scuba_vlo: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal co2_2: std_logic;
+ signal wren_i: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co3_1: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co3_2: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+
+ -- local component declarations
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CO: out std_logic; NC1: out std_logic; NC0: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC1: in std_logic; PC0: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC1: out std_logic;
+ NC0: out std_logic);
+ end component;
+ component AGEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A1: in std_logic; A0: in std_logic; B1: in std_logic;
+ B0: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "delay_fifo.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t3: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ AND2_t1: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t0: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_1: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ pdp_ram_0_0_0: PDP16KA
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>scuba_vhi, ADW1=>scuba_vhi, ADW2=>scuba_vhi,
+ ADW3=>scuba_vhi, ADW4=>scuba_vlo, ADW5=>wcount_0,
+ ADW6=>wcount_1, ADW7=>wcount_2, ADW8=>wcount_3,
+ ADW9=>wcount_4, ADW10=>wcount_5, ADW11=>wcount_6,
+ ADW12=>scuba_vlo, ADW13=>scuba_vlo, CEW=>wren_i, CLKW=>Clock,
+ WE=>scuba_vhi, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
+ ADR5=>rcount_0, ADR6=>rcount_1, ADR7=>rcount_2,
+ ADR8=>rcount_3, ADR9=>rcount_4, ADR10=>rcount_5,
+ ADR11=>rcount_6, ADR12=>scuba_vlo, ADR13=>scuba_vlo,
+ CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i, CSR1=>scuba_vlo,
+ CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
+ DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
+ DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
+ DO12=>Q(30), DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open,
+ DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
+ DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
+ DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
+ DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
+ DO35=>Q(17));
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_21: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_20: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_17: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>cnt_con, PC1=>fcount_1, PC0=>fcount_0,
+ CON=>cnt_con, CO=>co0, NC1=>ifcount_1, NC0=>ifcount_0);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC1=>fcount_3, PC0=>fcount_2, CON=>cnt_con,
+ CO=>co1, NC1=>ifcount_3, NC0=>ifcount_2);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC1=>fcount_5, PC0=>fcount_4, CON=>cnt_con,
+ CO=>co2, NC1=>ifcount_5, NC0=>ifcount_4);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC1=>fcount_7, PC0=>fcount_6, CON=>cnt_con,
+ CO=>co3, NC1=>ifcount_7, NC0=>ifcount_6);
+
+ e_cmp_0: ALEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>scuba_vlo, B0=>rden_i,
+ CI=>scuba_vhi, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ e_cmp_3: ALEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>scuba_vlo,
+ B0=>scuba_vlo, CI=>co2_1, LE=>cmp_le_1);
+
+ g_cmp_0: AGEB2
+ port map (A1=>fcount_1, A0=>fcount_0, B1=>wren_i, B0=>wren_i,
+ CI=>scuba_vhi, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A1=>fcount_3, A0=>fcount_2, B1=>wren_i, B0=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A1=>fcount_5, A0=>fcount_4, B1=>wren_i, B0=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A1=>fcount_7, A0=>fcount_6, B1=>wren_i_inv, B0=>wren_i,
+ CI=>co2_2, GE=>cmp_ge_d1);
+
+ w_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>wcount_1, PC0=>wcount_0, CO=>co0_3,
+ NC1=>iwcount_1, NC0=>iwcount_0);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC1=>wcount_3, PC0=>wcount_2, CO=>co1_3,
+ NC1=>iwcount_3, NC0=>iwcount_2);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC1=>wcount_5, PC0=>wcount_4, CO=>co2_3,
+ NC1=>iwcount_5, NC0=>iwcount_4);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC1=>wcount_7, PC0=>wcount_6, CO=>co3_1,
+ NC1=>iwcount_7, NC0=>iwcount_6);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_0: CU2
+ port map (CI=>scuba_vhi, PC1=>rcount_1, PC0=>rcount_0, CO=>co0_4,
+ NC1=>ircount_1, NC0=>ircount_0);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC1=>rcount_3, PC0=>rcount_2, CO=>co1_4,
+ NC1=>ircount_3, NC0=>ircount_2);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC1=>rcount_5, PC0=>rcount_4, CO=>co2_4,
+ NC1=>ircount_5, NC0=>ircount_4);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC1=>rcount_7, PC0=>rcount_6, CO=>co3_2,
+ NC1=>ircount_7, NC0=>ircount_6);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of delay_fifo is
+ for Structure
+ for all:ROM16X1 use entity SCM.ROM16X1(V); end for;
+ for all:AND2 use entity SCM.AND2(V); end for;
+ for all:XOR2 use entity SCM.XOR2(V); end for;
+ for all:INV use entity SCM.INV(V); end for;
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:CU2 use entity SCM.CU2(V); end for;
+ for all:CB2 use entity SCM.CB2(V); end for;
+ for all:AGEB2 use entity SCM.AGEB2(V); end for;
+ for all:ALEB2 use entity SCM.ALEB2(V); end for;
+ for all:FD1P3DX use entity SCM.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity SCM.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity SCM.FD1S3DX(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module Version: 3.5
+--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n dll_edge -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type dll -dll_type cid -fin 400 -clkos_div 1 -fb_mode 0 -e
+
+-- Tue Nov 8 09:51:24 2011
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity dll_edge is
+ generic (
+ SMI_OFFSET : in String := "0x410"
+ );
+ port (
+ clk: in std_logic;
+ aluhold: in std_logic;
+ clkop: out std_logic;
+ clkos: out std_logic;
+ lock: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of dll_edge : entity is true;
+end dll_edge;
+
+architecture Structure of dll_edge is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal clkos_t: std_logic;
+ signal scuba_vhi: std_logic;
+ signal clkop_t: std_logic;
+ signal clk_t: std_logic;
+
+ attribute module_type : string;
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component CIDDLLA
+ generic (SMI_OFFSET : in String
+ -- synopsys translate_off
+ ; CLKOS_DIV : in Integer; CLKOS_FPHASE : in Integer
+ -- synopsys translate_on
+ );
+ port (CLKI: in std_logic; CLKFB: in std_logic;
+ RSTN: in std_logic; ALUHOLD: in std_logic;
+ SMIADDR9: in std_logic; SMIADDR8: in std_logic;
+ SMIADDR7: in std_logic; SMIADDR6: in std_logic;
+ SMIADDR5: in std_logic; SMIADDR4: in std_logic;
+ SMIADDR3: in std_logic; SMIADDR2: in std_logic;
+ SMIADDR1: in std_logic; SMIADDR0: in std_logic;
+ SMIRD: in std_logic; SMIWR: in std_logic;
+ SMICLK: in std_logic; SMIWDATA: in std_logic;
+ SMIRSTN: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; LOCK: out std_logic;
+ SMIRDATA: out std_logic);
+ end component;
+ attribute module_type of CIDDLLA : component is "CIDDLLA";
+ attribute ip_type : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute GSR : string;
+ attribute CLKFB_PDEL : string;
+ attribute CLKI_PDEL : string;
+ attribute ALU_INIT_CNTVAL : string;
+ attribute ALU_UNLOCK_CNT : string;
+ attribute ALU_LOCK_CNT : string;
+ attribute CLKI_DIV : string;
+ attribute CLKOS_DIV : string;
+ attribute CLKOS_FPHASE : string;
+ attribute CLKOS_PHASE : string;
+ attribute CLKOP_PHASE : string;
+ attribute ip_type of dll_edge_0_0 : label is "CIDDLLA";
+ attribute FREQUENCY_PIN_CLKOS of dll_edge_0_0 : label is "400.000000";
+ attribute FREQUENCY_PIN_CLKOP of dll_edge_0_0 : label is "400.000000";
+ attribute FREQUENCY_PIN_CLKI of dll_edge_0_0 : label is "400.000000";
+ attribute GSR of dll_edge_0_0 : label is "DISABLED";
+ attribute CLKFB_PDEL of dll_edge_0_0 : label is "DEL0";
+ attribute CLKI_PDEL of dll_edge_0_0 : label is "DEL0";
+ attribute ALU_INIT_CNTVAL of dll_edge_0_0 : label is "0";
+ attribute ALU_UNLOCK_CNT of dll_edge_0_0 : label is "3";
+ attribute ALU_LOCK_CNT of dll_edge_0_0 : label is "3";
+ attribute CLKI_DIV of dll_edge_0_0 : label is "1";
+ attribute CLKOS_DIV of dll_edge_0_0 : label is "1";
+ attribute CLKOS_FPHASE of dll_edge_0_0 : label is "0";
+ attribute CLKOS_PHASE of dll_edge_0_0 : label is "90";
+ attribute CLKOP_PHASE of dll_edge_0_0 : label is "90";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ dll_edge_0_0: CIDDLLA
+ generic map (SMI_OFFSET=> SMI_OFFSET
+ -- synopsys translate_off
+ , CLKOS_DIV=> 1, CLKOS_FPHASE=> 0
+ -- synopsys translate_on
+ )
+ port map (CLKI=>clk_t, CLKFB=>clkop_t, RSTN=>scuba_vhi,
+ ALUHOLD=>aluhold, SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo,
+ SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo,
+ SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo,
+ SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo,
+ SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo,
+ SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo,
+ SMIRSTN=>scuba_vlo, CLKOP=>clkop_t, CLKOS=>clkos_t,
+ LOCK=>lock, SMIRDATA=>open);
+
+ clkos <= clkos_t;
+ clkop <= clkop_t;
+ clk_t <= clk;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of dll_edge is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:CIDDLLA use entity SCM.CIDDLLA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 3.5
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n dll_in400_out200 -lang vhdl -synth synplify -bus_exp 7 -bb -arch slayer -type dll -dll_type cid -fin 400 -clkos_div 2 -fb_mode 0 -e
+
+-- Tue Nov 1 11:30:03 2011
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SC;
+use SC.COMPONENTS.all;
+-- synopsys translate_on
+
+entity dll_in400_out200 is
+ generic (
+ SMI_OFFSET : in String := "0x410"
+ );
+ port (
+ clk: in std_logic;
+ aluhold: in std_logic;
+ clkop: out std_logic;
+ clkos: out std_logic;
+ lock: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of dll_in400_out200 : entity is true;
+end dll_in400_out200;
+
+architecture Structure of dll_in400_out200 is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal clkos_t: std_logic;
+ signal scuba_vhi: std_logic;
+ signal clkop_t: std_logic;
+ signal clk_t: std_logic;
+
+ attribute module_type : string;
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component CIDDLLA
+ generic (SMI_OFFSET : in String
+ -- synopsys translate_off
+ ; CLKOS_DIV : in Integer; CLKOS_FPHASE : in Integer
+ -- synopsys translate_on
+ );
+ port (CLKI: in std_logic; CLKFB: in std_logic;
+ RSTN: in std_logic; ALUHOLD: in std_logic;
+ SMIADDR9: in std_logic; SMIADDR8: in std_logic;
+ SMIADDR7: in std_logic; SMIADDR6: in std_logic;
+ SMIADDR5: in std_logic; SMIADDR4: in std_logic;
+ SMIADDR3: in std_logic; SMIADDR2: in std_logic;
+ SMIADDR1: in std_logic; SMIADDR0: in std_logic;
+ SMIRD: in std_logic; SMIWR: in std_logic;
+ SMICLK: in std_logic; SMIWDATA: in std_logic;
+ SMIRSTN: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; LOCK: out std_logic;
+ SMIRDATA: out std_logic);
+ end component;
+ attribute module_type of CIDDLLA : component is "CIDDLLA";
+ attribute ip_type : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute GSR : string;
+ attribute CLKFB_PDEL : string;
+ attribute CLKI_PDEL : string;
+ attribute ALU_INIT_CNTVAL : string;
+ attribute ALU_UNLOCK_CNT : string;
+ attribute ALU_LOCK_CNT : string;
+ attribute CLKI_DIV : string;
+ attribute CLKOS_DIV : string;
+ attribute CLKOS_FPHASE : string;
+ attribute CLKOS_PHASE : string;
+ attribute CLKOP_PHASE : string;
+ attribute ip_type of dll_in400_out200_0_0 : label is "CIDDLLA";
+ attribute FREQUENCY_PIN_CLKOS of dll_in400_out200_0_0 : label is "200.000000";
+ attribute FREQUENCY_PIN_CLKOP of dll_in400_out200_0_0 : label is "400.000000";
+ attribute FREQUENCY_PIN_CLKI of dll_in400_out200_0_0 : label is "400.000000";
+ attribute GSR of dll_in400_out200_0_0 : label is "DISABLED";
+ attribute CLKFB_PDEL of dll_in400_out200_0_0 : label is "DEL0";
+ attribute CLKI_PDEL of dll_in400_out200_0_0 : label is "DEL0";
+ attribute ALU_INIT_CNTVAL of dll_in400_out200_0_0 : label is "0";
+ attribute ALU_UNLOCK_CNT of dll_in400_out200_0_0 : label is "3";
+ attribute ALU_LOCK_CNT of dll_in400_out200_0_0 : label is "3";
+ attribute CLKI_DIV of dll_in400_out200_0_0 : label is "1";
+ attribute CLKOS_DIV of dll_in400_out200_0_0 : label is "2";
+ attribute CLKOS_FPHASE of dll_in400_out200_0_0 : label is "0";
+ attribute CLKOS_PHASE of dll_in400_out200_0_0 : label is "90";
+ attribute CLKOP_PHASE of dll_in400_out200_0_0 : label is "90";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ dll_in400_out200_0_0: CIDDLLA
+ generic map (SMI_OFFSET=> SMI_OFFSET
+ -- synopsys translate_off
+ , CLKOS_DIV=> 2, CLKOS_FPHASE=> 0
+ -- synopsys translate_on
+ )
+ port map (CLKI=>clk_t, CLKFB=>clkop_t, RSTN=>scuba_vhi,
+ ALUHOLD=>aluhold, SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo,
+ SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo,
+ SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo,
+ SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo,
+ SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo,
+ SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo,
+ SMIRSTN=>scuba_vlo, CLKOP=>clkop_t, CLKOS=>clkos_t,
+ LOCK=>lock, SMIRDATA=>open);
+
+ clkos <= clkos_t;
+ clkop <= clkop_t;
+ clk_t <= clk;
+end Structure;
+
+-- synopsys translate_off
+library SC;
+configuration Structure_CON of dll_in400_out200 is
+ for Structure
+ for all:VHI use entity SC.VHI(V); end for;
+ for all:VLO use entity SC.VLO(V); end for;
+ for all:CIDDLLA use entity SC.CIDDLLA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]
+Family=latticeecp2m
+PartType=LFE2M100E
+PartName=LFE2M100E-5F900C
+SpeedGrade=-5
+Package=FPBGA900
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO
+CoreRevision=4.7
+ModuleName=ecp2m_lvl2_trigger_buffer_fifo_1kW
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=10/19/2010
+Time=11:55:39
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=512
+Width=34
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=1
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 4.7
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 512 -width 34 -depth 512 -regout -no_enable -pe -1 -pf -1 -fill -e
+
+-- Tue Oct 19 11:55:39 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity ecp2m_lvl2_trigger_buffer_fifo_1kW is
+ port (
+ Data: in std_logic_vector(33 downto 0);
+ Clock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ Q: out std_logic_vector(33 downto 0);
+ WCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end ecp2m_lvl2_trigger_buffer_fifo_1kW;
+
+architecture Structure of ecp2m_lvl2_trigger_buffer_fifo_1kW is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal rden_i_inv: std_logic;
+ signal fcnt_en: std_logic;
+ signal empty_i: std_logic;
+ signal empty_d: std_logic;
+ signal full_i: std_logic;
+ signal full_d: std_logic;
+ signal ifcount_0: std_logic;
+ signal ifcount_1: std_logic;
+ signal bdcnt_bctr_ci: std_logic;
+ signal ifcount_2: std_logic;
+ signal ifcount_3: std_logic;
+ signal co0: std_logic;
+ signal ifcount_4: std_logic;
+ signal ifcount_5: std_logic;
+ signal co1: std_logic;
+ signal ifcount_6: std_logic;
+ signal ifcount_7: std_logic;
+ signal co2: std_logic;
+ signal ifcount_8: std_logic;
+ signal ifcount_9: std_logic;
+ signal co4: std_logic;
+ signal cnt_con: std_logic;
+ signal co3: std_logic;
+ signal cmp_ci: std_logic;
+ signal rden_i: std_logic;
+ signal co0_1: std_logic;
+ signal co1_1: std_logic;
+ signal co2_1: std_logic;
+ signal co3_1: std_logic;
+ signal cmp_le_1: std_logic;
+ signal cmp_le_1_c: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal fcount_0: std_logic;
+ signal fcount_1: std_logic;
+ signal co0_2: std_logic;
+ signal fcount_2: std_logic;
+ signal fcount_3: std_logic;
+ signal co1_2: std_logic;
+ signal fcount_4: std_logic;
+ signal fcount_5: std_logic;
+ signal co2_2: std_logic;
+ signal fcount_6: std_logic;
+ signal fcount_7: std_logic;
+ signal co3_2: std_logic;
+ signal wren_i: std_logic;
+ signal wren_i_inv: std_logic;
+ signal fcount_8: std_logic;
+ signal fcount_9: std_logic;
+ signal cmp_ge_d1: std_logic;
+ signal cmp_ge_d1_c: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal w_ctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co0_3: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co1_3: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co2_3: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co4_1: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co3_3: std_logic;
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal r_ctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co0_4: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co1_4: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co2_4: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_2: std_logic;
+ signal rcount_8: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_4: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component ALEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; LE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component CB2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CON: in std_logic; CO: out std_logic; NC0: out std_logic;
+ NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component PDPW16KB
+ -- synopsys translate_off
+ generic (CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ GSR : in String; RESETMODE : in String;
+ REGMODE : in String; DATA_WIDTH_R : in Integer;
+ DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
+ BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
+ CLKW: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; CSW2: in std_logic;
+ ADR0: in std_logic; ADR1: in std_logic;
+ ADR2: in std_logic; ADR3: in std_logic;
+ ADR4: in std_logic; ADR5: in std_logic;
+ ADR6: in std_logic; ADR7: in std_logic;
+ ADR8: in std_logic; ADR9: in std_logic;
+ ADR10: in std_logic; ADR11: in std_logic;
+ ADR12: in std_logic; ADR13: in std_logic;
+ CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute GSR : string;
+ attribute initval of LUT4_1 : label is "0x3232";
+ attribute initval of LUT4_0 : label is "0x3232";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "ecp2m_lvl2_trigger_buffer_fifo_1kW.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_R of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_W of pdp_ram_0_0_0 : label is "0b001";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_W of pdp_ram_0_0_0 : label is "36";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t3: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_3: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t2: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_2: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ AND2_t1: AND2
+ port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con);
+
+ XOR2_t0: XOR2
+ port map (A=>wren_i, B=>rden_i, Z=>fcnt_en);
+
+ INV_1: INV
+ port map (A=>rden_i, Z=>rden_i_inv);
+
+ INV_0: INV
+ port map (A=>wren_i, Z=>wren_i_inv);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i,
+ AD0=>empty_i, DO0=>empty_d);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x3232")
+ -- synopsys translate_on
+ port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i,
+ AD0=>full_i, DO0=>full_d);
+
+ pdp_ram_0_0_0: PDPW16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_R=> "001", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>Data(32),
+ DI33=>Data(33), DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>wcount_0, ADW1=>wcount_1, ADW2=>wcount_2,
+ ADW3=>wcount_3, ADW4=>wcount_4, ADW5=>wcount_5,
+ ADW6=>wcount_6, ADW7=>wcount_7, ADW8=>wcount_8,
+ BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
+ BE3=>scuba_vhi, CEW=>wren_i, CLKW=>Clock, CSW0=>scuba_vhi,
+ CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
+ ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
+ ADR4=>scuba_vlo, ADR5=>rcount_0, ADR6=>rcount_1,
+ ADR7=>rcount_2, ADR8=>rcount_3, ADR9=>rcount_4,
+ ADR10=>rcount_5, ADR11=>rcount_6, ADR12=>rcount_7,
+ ADR13=>rcount_8, CER=>scuba_vhi, CLKR=>Clock, CSR0=>rden_i,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18),
+ DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23),
+ DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28),
+ DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>Q(32),
+ DO15=>Q(33), DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1),
+ DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6),
+ DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
+ DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
+ DO34=>Q(16), DO35=>Q(17));
+
+ FF_31: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_0);
+
+ FF_30: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_1);
+
+ FF_29: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_2);
+
+ FF_28: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_3);
+
+ FF_27: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_4);
+
+ FF_26: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_5);
+
+ FF_25: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_6);
+
+ FF_24: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_7);
+
+ FF_23: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_8);
+
+ FF_22: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset,
+ Q=>fcount_9);
+
+ FF_21: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i);
+
+ FF_19: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_0);
+
+ FF_18: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_17: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_16: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_15: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_14: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_13: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_12: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_11: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_10: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_9: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_0);
+
+ FF_8: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_1);
+
+ FF_7: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_2);
+
+ FF_6: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_3);
+
+ FF_5: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_4);
+
+ FF_4: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_5);
+
+ FF_3: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_6);
+
+ FF_2: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_7);
+
+ FF_1: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_8);
+
+ FF_0: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset,
+ Q=>rcount_9);
+
+ bdcnt_bctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con,
+ CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open);
+
+ bdcnt_bctr_0: CB2
+ port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1,
+ CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1);
+
+ bdcnt_bctr_1: CB2
+ port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con,
+ CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3);
+
+ bdcnt_bctr_2: CB2
+ port map (CI=>co1, PC0=>fcount_4, PC1=>fcount_5, CON=>cnt_con,
+ CO=>co2, NC0=>ifcount_4, NC1=>ifcount_5);
+
+ bdcnt_bctr_3: CB2
+ port map (CI=>co2, PC0=>fcount_6, PC1=>fcount_7, CON=>cnt_con,
+ CO=>co3, NC0=>ifcount_6, NC1=>ifcount_7);
+
+ bdcnt_bctr_4: CB2
+ port map (CI=>co3, PC0=>fcount_8, PC1=>fcount_9, CON=>cnt_con,
+ CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9);
+
+ e_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open,
+ S1=>open);
+
+ e_cmp_0: ALEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo,
+ CI=>cmp_ci, LE=>co0_1);
+
+ e_cmp_1: ALEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_1, LE=>co1_1);
+
+ e_cmp_2: ALEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co1_1, LE=>co2_1);
+
+ e_cmp_3: ALEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co2_1, LE=>co3_1);
+
+ e_cmp_4: ALEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co3_1, LE=>cmp_le_1_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1,
+ S1=>open);
+
+ g_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open,
+ S1=>open);
+
+ g_cmp_0: AGEB2
+ port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i,
+ CI=>cmp_ci_1, GE=>co0_2);
+
+ g_cmp_1: AGEB2
+ port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i,
+ CI=>co0_2, GE=>co1_2);
+
+ g_cmp_2: AGEB2
+ port map (A0=>fcount_4, A1=>fcount_5, B0=>wren_i, B1=>wren_i,
+ CI=>co1_2, GE=>co2_2);
+
+ g_cmp_3: AGEB2
+ port map (A0=>fcount_6, A1=>fcount_7, B0=>wren_i, B1=>wren_i,
+ CI=>co2_2, GE=>co3_2);
+
+ g_cmp_4: AGEB2
+ port map (A0=>fcount_8, A1=>fcount_9, B0=>wren_i, B1=>wren_i_inv,
+ CI=>co3_2, GE=>cmp_ge_d1_c);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1,
+ S1=>open);
+
+ w_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open,
+ S1=>open);
+
+ w_ctr_0: CU2
+ port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_ctr_1: CU2
+ port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_ctr_2: CU2
+ port map (CI=>co1_3, PC0=>wcount_4, PC1=>wcount_5, CO=>co2_3,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_ctr_3: CU2
+ port map (CI=>co2_3, PC0=>wcount_6, PC1=>wcount_7, CO=>co3_3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_ctr_4: CU2
+ port map (CI=>co3_3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4_1,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ r_ctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open,
+ S1=>open);
+
+ r_ctr_0: CU2
+ port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_ctr_1: CU2
+ port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_ctr_2: CU2
+ port map (CI=>co1_4, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_4,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_ctr_3: CU2
+ port map (CI=>co2_4, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_4,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_ctr_4: CU2
+ port map (CI=>co3_4, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_2,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ WCNT(0) <= fcount_0;
+ WCNT(1) <= fcount_1;
+ WCNT(2) <= fcount_2;
+ WCNT(3) <= fcount_3;
+ WCNT(4) <= fcount_4;
+ WCNT(5) <= fcount_5;
+ WCNT(6) <= fcount_6;
+ WCNT(7) <= fcount_7;
+ WCNT(8) <= fcount_8;
+ WCNT(9) <= fcount_9;
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of ecp2m_lvl2_trigger_buffer_fifo_1kW is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:ALEB2 use entity ecp2m.ALEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:CB2 use entity ecp2m.CB2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:PDPW16KB use entity ecp2m.PDPW16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA40EP1
+PartName=LFSCM3GA40EP1-7FC1152C
+SpeedGrade=-7
+Package=FCBGA1152
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.1
+ModuleName=edge_clk
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=07/30/2010
+Time=15:58:49
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+Clki_freq=200
+U_OFrq=800
+OP_Tol=0.0
+ClkOP_Freq= 800.000000
+U_SFrq=200
+OS_Tol=0.0
+ClkOS_Freq= 200.000000
+Phase=0
+FineDelay=0
+FeedbackClk=Internal
+Frequency=200
+enSpectrum=0
+smiport=0
+enRSTN=0
+Clki_boosting=DEL0
+Clkfb_boosting=DEL0
+Clki_fine=0
+Clkfb_fine=0
+enSpread=0
+modulation=1
+Desired=30
+Actual=30
+lock=Frequency
+enGSR=0
+VcoRate= 800.000000
+Bandwidth= 6.620846
+enHighBand=0
+enBypassP=0
+enBypassS=0
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+--use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.NUMERIC_STD.all;
+use STD.TEXTIO.all;
+use IEEE.STD_LOGIC_TEXTIO.all;
+--library UNISIM;
+--use UNISIM.VCOMPONENTS.all;
+
+entity etrax_reg_mem is
+ generic (
+ RW_REGISTERS_NUMBER : natural;
+ R_REGISTERS_NUMBER : natural;
+ SCALERS_NUMBER : natural;
+ ENABLE_ETRAX_RW_INTERFACE : natural
+ );
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ ETRAX_DATA_BUS_E : inout std_logic_vector(9 downto 8);
+ RW_REGISTER_OUT : out std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0);
+ R_REGISTER_IN : in std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+ R_REGISTER_IN_SAVE_1S_IN : in std_logic;
+ R_REGISTER_OUT : out std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0);
+ SAVED_SCALERS_OUT : out std_logic_vector(SCALERS_NUMBER*32-1 downto 0);
+ REGIO_ADDR_IN : in std_logic_vector(15 downto 0);
+ REGIO_READ_ENABLE_IN : in std_logic;
+ REGIO_WRITE_ENABLE_IN : in std_logic;
+ REGIO_DATA_IN : in std_logic_vector(31 downto 0);
+ REGIO_DATA_OUT : out std_logic_vector(31 downto 0);
+ REGIO_DATAREADY_OUT : out std_logic;
+ REGIO_NO_MORE_DATA_OUT : out std_logic;
+ REGIO_WRITE_ACK_OUT : out std_logic;
+ REGIO_UNKNOWN_ADDR_OUT : out std_logic;
+ DEBUG_REGISTER_OO : out std_logic_vector(31 downto 0)
+ );
+end etrax_reg_mem;
+
+architecture etrax_reg_mem of etrax_reg_mem is
+
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+
+ component up_down_counter
+ generic (
+ NUMBER_OF_BITS : positive);
+ port (
+ CLK : in std_logic;
+ RESET : in std_logic;
+ COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
+ UP_IN : in std_logic;
+ DOWN_IN : in std_logic);
+ end component;
+
+ component ram_register
+ port (
+ WrAddress : in std_logic_vector(0 downto 0);
+ RdAddress : in std_logic_vector(0 downto 0);
+ Data : in std_logic_vector(31 downto 0);
+ WE : in std_logic;
+ RdClock : in std_logic;
+ RdClockEn : in std_logic;
+ Reset : in std_logic;
+ WrClock : in std_logic;
+ WrClockEn : in std_logic;
+ Q : out std_logic_vector(31 downto 0));
+ end component;
+
+ signal rw_operation_finished_pulse : std_logic;
+ signal saved_rw_mode : std_logic_vector(15 downto 0):= (others => '0');
+ signal saved_address : std_logic_vector (31 downto 0):= (others => '0');
+ signal saved_data : std_logic_vector(31 downto 0):= (others => '0');
+ signal saved_data_fpga : std_logic_vector(31 downto 0):= (others => '0');
+ signal r_register_i : std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0) := (others => '0');
+ signal rw_register_i : std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0) := (others => '0');
+ signal r_register_i_sync : std_logic_vector(R_REGISTERS_NUMBER*32-1 downto 0) := (others => '0');
+ signal rw_register_i_sync : std_logic_vector(RW_REGISTERS_NUMBER*32-1 downto 0) := (others => '0');
+
+
+
+ signal etrax_is_ready_to_read_i : std_logic;
+ signal lvl2_not_valid_pulse : std_logic;
+ signal counter_for_pulses : std_logic_vector(2 downto 0);
+ signal internal_reset_i : std_logic := '0';
+
+ signal data_from_etrax : std_logic_vector(80 downto 0):= (others => '0');
+ signal etrax_std_data_counter : std_logic_vector(7 downto 0):=x"00";
+ signal enable_transmition : std_logic :='1';
+ signal etrax_strobe : std_logic;
+ signal data_to_etrax : std_logic_vector(31 downto 0);
+
+
+ signal not_etrax_busy : std_logic;
+
+
+ signal data_bus_reg : std_logic_vector(31 downto 0);
+
+
+ signal readout_lvl2_fifo :std_logic;
+
+ signal data_valid_start_pulse : std_logic;
+ signal data_valid_end_pulse : std_logic;
+ signal data_valid_not : std_logic;
+ signal etrax_busy_end : std_logic;
+ signal write_to_dma_synch : std_logic;
+ signal word16_counter : std_logic_vector(7 downto 0);
+ signal write_to_dma_synch_synch : std_logic;
+ signal reg_address : integer range 0 to 256 :=1;
+ signal data_valid_synch : std_logic;
+ signal how_many_data_was_sent : std_logic_vector(4 downto 0);
+ signal time_out_cntr : std_logic_vector(31 downto 0);
+ signal time_out_pulse : std_logic;
+ signal etrax_or_regio_reg_access : std_logic;
+
+--reg io signals
+ signal regio_address_saved : std_logic_vector(15 downto 0);
+ signal regio_data_saved : std_logic_vector(31 downto 0);
+ signal regio_mode_save : std_logic;
+ signal ack_out_synch_a : std_logic:='0';
+ signal ack_out_synch_b : std_logic:='0';
+ signal ack_out_synch_c : std_logic:='0';
+ signal ack_out_synch_d : std_logic:='0';
+ signal ack_out_synch_e : std_logic:='0';
+ signal unknown_address_set, unknown_address_pulse : std_logic;
+ signal ipu_data_valid_a, ipu_data_valid_b: std_logic;
+ signal test_regio : std_logic_vector(3 downto 0);
+ constant max_rw_range : integer := RW_REGISTERS_NUMBER+191; --x"c0" - 192
+ constant min_rw_range : integer := 191; -- bigger than
+ constant max_r_range : integer := R_REGISTERS_NUMBER; --x"80" - 128
+ constant min_r_range : integer := 0;
+ constant endpoint_base_addr : std_logic_vector(7 downto 0) := x"A0";
+ signal rw_access : std_logic_vector(RW_REGISTERS_NUMBER-1 downto 0);
+ signal rw_access_not : std_logic_vector(RW_REGISTERS_NUMBER-1 downto 0);
+ signal rw_access_pulse : std_logic_vector(RW_REGISTERS_NUMBER-1 downto 0);
+ signal rw_access_not_pulse : std_logic_vector(RW_REGISTERS_NUMBER-1 downto 0);
+ signal r_access : std_logic_vector(R_REGISTERS_NUMBER-1 downto 0);
+ signal r_access_read : std_logic;
+begin
+
+ R_REGISTER_OUT <= r_register_i;
+
+
+
+ ETRAX_DATA_BUS_E(9) <= 'Z';
+
+
+ STROBE_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => ETRAX_DATA_BUS_E(9),--
+ pulse => etrax_strobe);
+
+ SAVE_ETRAX_DATA : process (CLK, RESET)
+ variable etrax_data_counter : integer := 0;
+ begin
+ if rising_edge(CLK)then
+ if RESET = '1' or (etrax_std_data_counter = 81 and saved_rw_mode(15) = '0') or (etrax_std_data_counter = 114 and saved_rw_mode(15) = '1') or (ENABLE_ETRAX_RW_INTERFACE = 0) then
+ etrax_data_counter := 0;
+ data_from_etrax <= data_from_etrax;
+ ETRAX_DATA_BUS_E(8) <= 'Z';
+ enable_transmition <= '1';
+ etrax_std_data_counter <= x"00";
+ elsif etrax_strobe = '1' and etrax_std_data_counter < 81 then -- and etrax_data_counter < 81 and etrax_data_counter > 0 then
+ data_from_etrax(etrax_data_counter) <= ETRAX_DATA_BUS_E(8);
+ etrax_data_counter := etrax_data_counter + 1;
+ ETRAX_DATA_BUS_E(8) <= 'Z';
+ enable_transmition <= '0';
+ etrax_std_data_counter <= etrax_std_data_counter + 1;
+-- elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' and saved_rw_mode(7 downto 0) = x"00" then
+ elsif etrax_std_data_counter = 81 and saved_rw_mode(15) = '1' then
+ data_from_etrax <= data_from_etrax;
+ ETRAX_DATA_BUS_E(8) <= data_to_etrax(0);
+ etrax_data_counter := etrax_data_counter + 1;
+ etrax_std_data_counter <= etrax_std_data_counter + 1;
+ enable_transmition <= '0';
+ elsif etrax_strobe = '1' and etrax_std_data_counter > 81 and saved_rw_mode(15) = '1' then
+ data_from_etrax <= data_from_etrax;
+ ETRAX_DATA_BUS_E(8) <= data_to_etrax((etrax_data_counter-81) mod 32);--+reg_address*32
+ etrax_data_counter := etrax_data_counter + 1;
+ etrax_std_data_counter <= etrax_std_data_counter + 1;
+ enable_transmition <= '0';
+ end if;
+ end if;
+ end process SAVE_ETRAX_DATA;
+
+ CHANGE_MODE_ETRAX_OR_REGIO : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ etrax_or_regio_reg_access <= '0';
+ elsif etrax_std_data_counter > 0 then
+ etrax_or_regio_reg_access <= '1';
+ elsif REGIO_WRITE_ENABLE_IN = '1' or REGIO_READ_ENABLE_IN = '1' then
+ etrax_or_regio_reg_access <= '0';
+ else
+ etrax_or_regio_reg_access <= etrax_or_regio_reg_access;
+ end if;
+ end if;
+ end process CHANGE_MODE_ETRAX_OR_REGIO;
+
+ SYNC_DATA_TO_ETRAX : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ data_to_etrax <= (others => '0');
+ else
+ data_to_etrax <= saved_data_fpga;
+ end if;
+ end if;
+ end process SYNC_DATA_TO_ETRAX;
+
+ TIME_OUT : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ time_out_cntr <= x"00000000";
+ elsif etrax_std_data_counter = 81 then
+ time_out_cntr <= time_out_cntr + 1;
+ else
+ time_out_cntr <= x"00000000";
+ end if;
+ end if;
+ end process TIME_OUT;
+
+ TIME_OUT_PULSER : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => time_out_cntr(26),
+ pulse => time_out_pulse);
+
+ SAVE_REG_IO_ADD_DATA : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ regio_address_saved <= (others => '0');
+ regio_data_saved <= (others => '0');
+ elsif REGIO_WRITE_ENABLE_IN = '1' or REGIO_READ_ENABLE_IN = '1' then
+ regio_address_saved <= REGIO_ADDR_IN;
+ regio_data_saved <= REGIO_DATA_IN;
+ else
+ regio_address_saved <= regio_address_saved;
+ regio_data_saved <= regio_data_saved;
+ end if;
+ end if;
+ end process SAVE_REG_IO_ADD_DATA;
+
+ SET_UNKNOWN_ADDRESS : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or ack_out_synch_e = '1' then
+ unknown_address_set <= '0';
+ elsif (ack_out_synch_b = '1') and
+ (((saved_address(15 downto 8) /= endpoint_base_addr) or
+ (reg_address > max_rw_range and reg_address < min_rw_range and saved_rw_mode(15) = '0') or
+ (reg_address > max_r_range and reg_address < min_r_range and saved_rw_mode(15) = '1'))) then
+ unknown_address_set <= '1';
+ end if;
+ end if;
+ end process SET_UNKNOWN_ADDRESS;
+ REGIO_UNKNOWN_ADDR_OUT <= unknown_address_set;
+
+ SET_ACK_OUT : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ ack_out_synch_a <= '0';
+ ack_out_synch_b <= '0';
+ ack_out_synch_c <= '0';
+ ack_out_synch_d <= '0';
+ ack_out_synch_e <= '0';
+ else
+ ack_out_synch_e <= ack_out_synch_d;
+ ack_out_synch_d <= ack_out_synch_c;
+ ack_out_synch_c <= ack_out_synch_b;
+ ack_out_synch_b <= ack_out_synch_a;
+ ack_out_synch_a <= REGIO_WRITE_ENABLE_IN or REGIO_READ_ENABLE_IN;
+ end if;
+ end if;
+ end process SET_ACK_OUT;
+
+ REGIO_NO_MORE_DATA_OUT <= ack_out_synch_e and (not unknown_address_set);
+ REGIO_DATAREADY_OUT <= ack_out_synch_d and regio_mode_save and (not unknown_address_set);
+ REGIO_WRITE_ACK_OUT <= ack_out_synch_d and (not (regio_mode_save)) and (not unknown_address_set);
+
+
+ SEND_DATA_OUT : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ REGIO_DATA_OUT <= x"00000000";
+ else
+ REGIO_DATA_OUT <= saved_data_fpga;
+ end if;
+ end if;
+ end process SEND_DATA_OUT;
+
+ REGIO_SAVE_MODE : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ regio_mode_save <= '0';
+ elsif REGIO_WRITE_ENABLE_IN = '1' then
+ regio_mode_save <= '0';
+ elsif REGIO_READ_ENABLE_IN = '1' then
+ regio_mode_save <= '1';
+ else
+ regio_mode_save <= regio_mode_save;
+ end if;
+ end if;
+ end process REGIO_SAVE_MODE;
+
+ CLOCK_SAVED_DATA: process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ saved_rw_mode <= (others => '0');
+ saved_address <= (others => '0');
+ saved_data <= (others => '0');
+ reg_address <= 1;
+ elsif etrax_or_regio_reg_access = '1' then
+ saved_rw_mode <= data_from_etrax(15 downto 0);
+ saved_address <= data_from_etrax(47 downto 16);
+ -- reg_address <= reg_address* (conv_integer(data_from_etrax(47 downto 16)));
+-- reg_address <= conv_integer(data_from_etrax(31 downto 16));
+ reg_address <= conv_integer(data_from_etrax(23 downto 16));
+ --only 16 lowest bits - the 8 highest is not taken into address for
+ --internal registers
+ saved_data <= data_from_etrax(79 downto 48);
+ else
+ saved_rw_mode <= regio_mode_save & "000" & x"000";
+ saved_address <= x"0000" & regio_address_saved(15 downto 0);
+ saved_data <= regio_data_saved;
+ reg_address <= conv_integer(regio_address_saved(7 downto 0));
+ end if;
+ end if;
+ end process CLOCK_SAVED_DATA;
+
+ DEBUG_REGISTER_OO(25 downto 0) <= unknown_address_set & saved_rw_mode(15) & saved_address(7 downto 0) & saved_data(15 downto 0);
+
+
+ DEBUG_REGISTER_OO(31 downto 28) <= test_regio;
+
+ RW_REGISTER_MANAGER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ rw_access<= (others => '1');
+ elsif ((saved_rw_mode(15) = '0' and etrax_std_data_counter = 80) or (saved_rw_mode(15) = '0' and ack_out_synch_b = '1' and saved_address(15 downto 8) = x"A0")) and (reg_address >191 and reg_address < 192+RW_REGISTERS_NUMBER-1) then
+ rw_access(reg_address-192) <= '1';
+ else
+ rw_access<= (others => '0');
+ end if;
+ end if;
+ end process RW_REGISTER_MANAGER;
+
+
+
+ RW_REGISTERS: for i in 0 to RW_REGISTERS_NUMBER - 1 generate
+
+ rw_access_not(i) <= not rw_access(i);
+
+ WRITE_RW : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => rw_access_not(i),
+ pulse => rw_access_not_pulse(i));
+
+ READ_R : edge_to_pulse
+ port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => rw_access(i),
+ pulse => rw_access_pulse(i));
+
+ RW_RAM_REGISTER: ram_register
+
+ port map (
+ WrAddress => (others => '0'),
+ RdAddress => (others => '0'),
+ Data => saved_data,
+ WE => rw_access(i),
+ RdClock => CLK,
+ RdClockEn => rw_access_not(i),
+ Reset => RESET,
+ WrClock => CLK,
+ WrClockEn => rw_access(i),
+ Q => rw_register_i((i+1)*32-1 downto i*32));
+
+ end generate RW_REGISTERS;
+
+
+ SYNC_RW_REGISTER : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ RW_REGISTER_OUT <= rw_register_i;
+ end if;
+ end process SYNC_RW_REGISTER;
+
+
+
+
+ r_access_read <= not R_REGISTER_IN_SAVE_1S_IN;
+
+ R_REGISTERS: for i in 0 to R_REGISTERS_NUMBER - 1 generate
+
+ DEBUG_REGISTERS: if i < 8 generate
+ r_register_i((i+1)*32-1 downto i*32) <= R_REGISTER_IN((i+1)*32-1 downto i*32);
+ end generate DEBUG_REGISTERS;
+
+ SCALERS: if i > 7 generate
+ R_RAM_REGISTER: ram_register
+
+ port map (
+ WrAddress => (others => '0'),
+ RdAddress => (others => '0'),
+ Data => R_REGISTER_IN((i+1)*32-1 downto i*32),
+ WE => R_REGISTER_IN_SAVE_1S_IN,
+ RdClock => CLK,
+ RdClockEn => r_access_read,
+ Reset => RESET,
+ WrClock => CLK,
+ WrClockEn => R_REGISTER_IN_SAVE_1S_IN,
+ Q => r_register_i((i+1)*32-1 downto i*32));
+
+ end generate SCALERS;
+ end generate R_REGISTERS;
+
+
+
+ -- SAVED_SCALERS_OUT(SCALERS_NUMBER*32-1 downto 0) <= r_register_i((SCALERS_NUMBER+8)*32-1 downto 8*32);
+
+ DATA_OUT_SOURCE_SELECT : process (CLK,RESET,saved_rw_mode,saved_address)
+ begin
+ if rising_edge(CLK) then
+ case saved_rw_mode(7 downto 0) is
+ when x"00" =>
+ --etrax
+ if saved_rw_mode(15) = '1' and etrax_std_data_counter = 80 and reg_address < 192 then
+ saved_data_fpga <= r_register_i((reg_address+1)*32-1 downto ((reg_address)*32));
+ elsif saved_rw_mode(15) = '1' and etrax_std_data_counter = 80 and reg_address >191 and reg_address < 256 then
+ saved_data_fpga <= rw_register_i((reg_address+1-192)*32-1 downto (reg_address-192)*32);
+ --trbnet
+ elsif saved_rw_mode(15) = '1' and ack_out_synch_b = '1' and reg_address < 192 and saved_address(15 downto 8) = x"A0" then
+ saved_data_fpga <= r_register_i((reg_address+1)*32-1 downto ((reg_address)*32));
+ test_regio <= x"1";
+ elsif saved_rw_mode(15) = '1' and ack_out_synch_b = '1' and reg_address >191 and reg_address < 256 and saved_address(15 downto 8) = x"A0" then
+ saved_data_fpga <= rw_register_i((reg_address+1-192)*32-1 downto (reg_address-192)*32);
+ test_regio <= x"2";
+ --rest
+ else
+ saved_data_fpga <= saved_data_fpga;
+ test_regio <= x"0";
+ end if;
+ when others =>
+ saved_data_fpga <= x"deadface";
+ end case;
+
+ end if;
+ end process DATA_OUT_SOURCE_SELECT;
+
+end etrax_reg_mem;
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module Version: 5.4
+--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n fifo16bit_synch -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 32 -width 16 -rwidth 16 -regout -no_enable -pe 2 -pf 6 -e
+
+-- Fri Nov 4 16:22:02 2011
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity fifo16bit_synch is
+ port (
+ Data: in std_logic_vector(15 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(15 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end fifo16bit_synch;
+
+architecture Structure of fifo16bit_synch is
+
+ -- internal signal declarations
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of fifo16bit_synch_0_0 : label is "0b000001111000001";
+ attribute FULLPOINTER of fifo16bit_synch_0_0 : label is "0b000001111100001";
+ attribute AFPOINTER1 of fifo16bit_synch_0_0 : label is "0b000000010000001";
+ attribute AFPOINTER of fifo16bit_synch_0_0 : label is "0b000000010100001";
+ attribute AEPOINTER1 of fifo16bit_synch_0_0 : label is "0b000000001111111";
+ attribute AEPOINTER of fifo16bit_synch_0_0 : label is "0b000000001011111";
+ attribute RESETMODE of fifo16bit_synch_0_0 : label is "ASYNC";
+ attribute REGMODE of fifo16bit_synch_0_0 : label is "OUTREG";
+ attribute CSDECODE_R of fifo16bit_synch_0_0 : label is "0b11";
+ attribute CSDECODE_W of fifo16bit_synch_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of fifo16bit_synch_0_0 : label is "36";
+ attribute DATA_WIDTH_W of fifo16bit_synch_0_0 : label is "36";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ fifo16bit_synch_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "000001111000001", FULLPOINTER=> "000001111100001",
+ AFPOINTER1=> "000000010000001", AFPOINTER=> "000000010100001",
+ AEPOINTER1=> "000000001111111", AEPOINTER=> "000000001011111",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>scuba_vlo, DI17=>scuba_vlo,
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
+ EMPTYI=>Empty_int, CSR0=>RdEn, CSR1=>scuba_vhi, WE=>WrEn,
+ RE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset,
+ RPRST=>RPReset, DO0=>open, DO1=>open, DO2=>open, DO3=>open,
+ DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open,
+ DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open,
+ DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0),
+ DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
+ DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
+ DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
+ DO33=>Q(15), DO34=>open, DO35=>open, EF=>Empty_int,
+ AEF=>AlmostEmpty, AFF=>AlmostFull, FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of fifo16bit_synch is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]
+Family=latticeecp2m
+PartType=LFE2M100E
+PartName=LFE2M100E-5F900C
+SpeedGrade=-5
+Package=FPBGA900
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.3
+ModuleName=fifo_16bit_to_32bit
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/09/2010
+Time=11:07:52
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=1024
+Width=16
+RDepth=512
+RWidth=32
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=1
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.3
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 1024 -width 16 -depth 1024 -rdata_width 32 -regout -no_enable -pe -1 -pf -1 -rfill -e
+
+-- Mon Aug 9 11:07:52 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_16bit_to_32bit is
+ port (
+ Data: in std_logic_vector(15 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ RCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_16bit_to_32bit;
+
+architecture Structure of fifo_16bit_to_32bit is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_2: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
+ signal r_g2b_xor_cluster_1: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
+ signal w_gdata_8: std_logic;
+ signal w_gdata_9: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal r_gdata_6: std_logic;
+ signal r_gdata_7: std_logic;
+ signal r_gdata_8: std_logic;
+ signal rptr_9: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
+ signal w_gcount_9: std_logic;
+ signal w_gcount_10: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal r_gcount_7: std_logic;
+ signal r_gcount_8: std_logic;
+ signal r_gcount_9: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
+ signal w_gcount_r29: std_logic;
+ signal w_gcount_r9: std_logic;
+ signal w_gcount_r210: std_logic;
+ signal w_gcount_r10: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal r_gcount_w27: std_logic;
+ signal r_gcount_w7: std_logic;
+ signal r_gcount_w28: std_logic;
+ signal r_gcount_w8: std_logic;
+ signal r_gcount_w29: std_logic;
+ signal r_gcount_w9: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3: std_logic;
+ signal iwcount_10: std_logic;
+ signal co5: std_logic;
+ signal wcount_10: std_logic;
+ signal co4: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_1: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_1: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_1: std_logic;
+ signal rfill_sub_0: std_logic;
+ signal rptr_0: std_logic;
+ signal scuba_vhi: std_logic;
+ signal rfill_sub_1: std_logic;
+ signal rfill_sub_2: std_logic;
+ signal co0_2: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rfill_sub_3: std_logic;
+ signal rfill_sub_4: std_logic;
+ signal co1_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rfill_sub_5: std_logic;
+ signal rfill_sub_6: std_logic;
+ signal co2_2: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rfill_sub_7: std_logic;
+ signal rfill_sub_8: std_logic;
+ signal co3_2: std_logic;
+ signal rptr_7: std_logic;
+ signal rptr_8: std_logic;
+ signal rfill_sub_9: std_logic;
+ signal co4_2: std_logic;
+ signal rfill_sub_msb: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r1: std_logic;
+ signal wcount_r2: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_r3: std_logic;
+ signal wcount_r4: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_r5: std_logic;
+ signal wcount_r6: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_3: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal wcount_r8: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_r9: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal rcount_8: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal rcount_w0: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_w1: std_logic;
+ signal rcount_w2: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_w3: std_logic;
+ signal rcount_w4: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_w5: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_w7: std_logic;
+ signal rcount_w8: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co4_3: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
+ attribute initval of LUT4_25 : label is "0x6996";
+ attribute initval of LUT4_24 : label is "0x6996";
+ attribute initval of LUT4_23 : label is "0x6996";
+ attribute initval of LUT4_22 : label is "0x6996";
+ attribute initval of LUT4_21 : label is "0x6996";
+ attribute initval of LUT4_20 : label is "0x6996";
+ attribute initval of LUT4_19 : label is "0x6996";
+ attribute initval of LUT4_18 : label is "0x6996";
+ attribute initval of LUT4_17 : label is "0x6996";
+ attribute initval of LUT4_16 : label is "0x6996";
+ attribute initval of LUT4_15 : label is "0x6996";
+ attribute initval of LUT4_14 : label is "0x6996";
+ attribute initval of LUT4_13 : label is "0x6996";
+ attribute initval of LUT4_12 : label is "0x6996";
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x6996";
+ attribute initval of LUT4_6 : label is "0x6996";
+ attribute initval of LUT4_5 : label is "0x6996";
+ attribute initval of LUT4_4 : label is "0x6996";
+ attribute initval of LUT4_3 : label is "0x0410";
+ attribute initval of LUT4_2 : label is "0x1004";
+ attribute initval of LUT4_1 : label is "0x0140";
+ attribute initval of LUT4_0 : label is "0x4001";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_16bit_to_32bit.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute REGMODE_A of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "18";
+ attribute GSR of FF_116 : label is "ENABLED";
+ attribute GSR of FF_115 : label is "ENABLED";
+ attribute GSR of FF_114 : label is "ENABLED";
+ attribute GSR of FF_113 : label is "ENABLED";
+ attribute GSR of FF_112 : label is "ENABLED";
+ attribute GSR of FF_111 : label is "ENABLED";
+ attribute GSR of FF_110 : label is "ENABLED";
+ attribute GSR of FF_109 : label is "ENABLED";
+ attribute GSR of FF_108 : label is "ENABLED";
+ attribute GSR of FF_107 : label is "ENABLED";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t22: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t21: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t20: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t19: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t18: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t17: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t16: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t15: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t14: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t13: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t12: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t11: XOR2
+ port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+ XOR2_t10: XOR2
+ port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+ XOR2_t9: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t8: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t7: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t6: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+ LUT4_25: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
+ AD1=>w_gcount_r29, AD0=>w_gcount_r210,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_24: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
+ AD1=>w_gcount_r25, AD0=>w_gcount_r26,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_23: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r9);
+
+ LUT4_22: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
+ AD1=>w_gcount_r210, AD0=>scuba_vlo, DO0=>wcount_r8);
+
+ LUT4_21: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
+ AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
+
+ LUT4_20: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
+ AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
+
+ LUT4_19: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
+ AD1=>w_gcount_r26, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r4);
+
+ LUT4_18: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r3);
+
+ LUT4_17: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+ LUT4_16: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r21, AD0=>w_gcount_r22, DO0=>wcount_r1);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_2);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
+ AD1=>r_gcount_w28, AD0=>r_gcount_w29,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>r_gcount_w25,
+ DO0=>r_g2b_xor_cluster_1);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w8);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
+ AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
+ AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+ XOR2_t0: XOR2
+ port map (A=>w_gcount_r210, B=>rptr_9, Z=>rfill_sub_msb);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r210,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r210,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_10, AD2=>wcount_10, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ pdp_ram_0_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 36,
+ DATA_WIDTH_A=> 18)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10),
+ DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13),
+ DIA14=>Data(14), DIA15=>Data(15), DIA16=>scuba_vlo,
+ DIA17=>scuba_vlo, ADA0=>scuba_vhi, ADA1=>scuba_vhi,
+ ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1,
+ ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5,
+ ADA10=>wptr_6, ADA11=>wptr_7, ADA12=>wptr_8, ADA13=>wptr_9,
+ CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, CSA0=>scuba_vlo,
+ CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset,
+ DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo,
+ DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo,
+ DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo,
+ DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo,
+ DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo,
+ DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo,
+ ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo,
+ ADB3=>scuba_vlo, ADB4=>scuba_vlo, ADB5=>rptr_0, ADB6=>rptr_1,
+ ADB7=>rptr_2, ADB8=>rptr_3, ADB9=>rptr_4, ADB10=>rptr_5,
+ ADB11=>rptr_6, ADB12=>rptr_7, ADB13=>rptr_8, CEB=>scuba_vhi,
+ CLKB=>RdClock, WEB=>scuba_vlo, CSB0=>rden_i, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>Q(0), DOA1=>Q(1),
+ DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6),
+ DOA7=>Q(7), DOA8=>Q(8), DOA9=>Q(9), DOA10=>Q(10),
+ DOA11=>Q(11), DOA12=>Q(12), DOA13=>Q(13), DOA14=>Q(14),
+ DOA15=>Q(15), DOA16=>open, DOA17=>open, DOB0=>Q(16),
+ DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>Q(20),
+ DOB5=>Q(21), DOB6=>Q(22), DOB7=>Q(23), DOB8=>Q(24),
+ DOB9=>Q(25), DOB10=>Q(26), DOB11=>Q(27), DOB12=>Q(28),
+ DOB13=>Q(29), DOB14=>Q(30), DOB15=>Q(31), DOB16=>open,
+ DOB17=>open);
+
+ FF_116: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_115: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_114: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_113: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_112: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_111: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_110: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_109: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_108: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_107: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_106: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_105: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_104: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_103: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_102: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_101: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_100: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_99: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_98: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_97: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_96: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_9);
+
+ FF_95: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_10);
+
+ FF_94: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_93: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_92: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_91: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_90: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_89: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_88: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_87: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_83: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_7);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_8);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_9);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_7);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_8);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_9);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_7);
+
+ FF_55: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_8);
+
+ FF_54: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_9);
+
+ FF_53: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_52: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_51: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_50: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_49: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_48: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_47: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_46: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_45: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_44: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+ FF_43: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r10);
+
+ FF_42: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_41: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_40: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_39: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_38: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_37: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_36: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_35: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+ FF_34: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+ FF_33: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+ FF_32: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_31: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_30: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_29: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_28: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_27: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_26: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r29);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r210);
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_gctr_5: CU2
+ port map (CI=>co4, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5,
+ NC0=>iwcount_10, NC1=>open);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_gctr_4: CU2
+ port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ rfill_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>wcount_r1, B0=>scuba_vlo,
+ B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
+ S1=>rfill_sub_0);
+
+ rfill_1: FSUB2B
+ port map (A0=>wcount_r2, A1=>wcount_r3, B0=>rptr_1, B1=>rptr_2,
+ BI=>co0_2, BOUT=>co1_2, S0=>rfill_sub_1, S1=>rfill_sub_2);
+
+ rfill_2: FSUB2B
+ port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_3, B1=>rptr_4,
+ BI=>co1_2, BOUT=>co2_2, S0=>rfill_sub_3, S1=>rfill_sub_4);
+
+ rfill_3: FSUB2B
+ port map (A0=>wcount_r6, A1=>w_g2b_xor_cluster_0, B0=>rptr_5,
+ B1=>rptr_6, BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5,
+ S1=>rfill_sub_6);
+
+ rfill_4: FSUB2B
+ port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_7, B1=>rptr_8,
+ BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7, S1=>rfill_sub_8);
+
+ rfill_5: FSUB2B
+ port map (A0=>rfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co4_2, BOUT=>open, S0=>rfill_sub_9,
+ S1=>open);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r1,
+ B1=>wcount_r2, CI=>cmp_ci, GE=>co0_3);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r3,
+ B1=>wcount_r4, CI=>co0_3, GE=>co1_3);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r5,
+ B1=>wcount_r6, CI=>co1_3, GE=>co2_3);
+
+ empty_cmp_3: AGEB2
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
+ B1=>wcount_r8, CI=>co2_3, GE=>co3_3);
+
+ empty_cmp_4: AGEB2
+ port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r9,
+ B1=>empty_cmp_clr, CI=>co3_3, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>rcount_w0, CI=>cmp_ci_1, GE=>co0_4);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w1,
+ B1=>rcount_w2, CI=>co0_4, GE=>co1_4);
+
+ full_cmp_2: AGEB2
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w3,
+ B1=>rcount_w4, CI=>co1_4, GE=>co2_4);
+
+ full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w5,
+ B1=>r_g2b_xor_cluster_0, CI=>co2_4, GE=>co3_4);
+
+ full_cmp_4: AGEB2
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w7,
+ B1=>rcount_w8, CI=>co3_4, GE=>co4_3);
+
+ full_cmp_5: AGEB2
+ port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
+ B1=>scuba_vlo, CI=>co4_3, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_16bit_to_32bit is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp2m.FSUB2B(V); end for;
+ for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:OR2 use entity ecp2m.OR2(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]
+Family=latticeecp2m
+PartType=LFE2M100E
+PartName=LFE2M100E-5F900C
+SpeedGrade=-5
+Package=FPBGA900
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.3
+ModuleName=fifo_1bit_to_32bit
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/09/2010
+Time=10:58:34
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=16384
+Width=1
+RDepth=512
+RWidth=32
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=1
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.3
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 16384 -width 1 -depth 16384 -rdata_width 32 -regout -no_enable -pe -1 -pf -1 -rfill -e
+
+-- Mon Aug 9 10:58:35 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_1bit_to_32bit is
+ port (
+ Data: in std_logic_vector(0 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ RCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_1bit_to_32bit;
+
+architecture Structure of fifo_1bit_to_32bit is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal wcount_r4: std_logic;
+ signal w_g2b_xor_cluster_2_1: std_logic;
+ signal wcount_r3: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r1: std_logic;
+ signal w_g2b_xor_cluster_3: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_3_1: std_logic;
+ signal w_g2b_xor_cluster_2: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
+ signal r_g2b_xor_cluster_1: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
+ signal w_gdata_8: std_logic;
+ signal w_gdata_9: std_logic;
+ signal w_gdata_10: std_logic;
+ signal w_gdata_11: std_logic;
+ signal w_gdata_12: std_logic;
+ signal w_gdata_13: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal wptr_12: std_logic;
+ signal wptr_13: std_logic;
+ signal wptr_14: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal r_gdata_6: std_logic;
+ signal r_gdata_7: std_logic;
+ signal r_gdata_8: std_logic;
+ signal rptr_9: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
+ signal w_gcount_9: std_logic;
+ signal w_gcount_10: std_logic;
+ signal w_gcount_11: std_logic;
+ signal w_gcount_12: std_logic;
+ signal w_gcount_13: std_logic;
+ signal w_gcount_14: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal r_gcount_7: std_logic;
+ signal r_gcount_8: std_logic;
+ signal r_gcount_9: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
+ signal w_gcount_r29: std_logic;
+ signal w_gcount_r9: std_logic;
+ signal w_gcount_r210: std_logic;
+ signal w_gcount_r10: std_logic;
+ signal w_gcount_r211: std_logic;
+ signal w_gcount_r11: std_logic;
+ signal w_gcount_r212: std_logic;
+ signal w_gcount_r12: std_logic;
+ signal w_gcount_r213: std_logic;
+ signal w_gcount_r13: std_logic;
+ signal w_gcount_r214: std_logic;
+ signal w_gcount_r14: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal r_gcount_w27: std_logic;
+ signal r_gcount_w7: std_logic;
+ signal r_gcount_w28: std_logic;
+ signal r_gcount_w8: std_logic;
+ signal r_gcount_w29: std_logic;
+ signal r_gcount_w9: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4: std_logic;
+ signal iwcount_12: std_logic;
+ signal iwcount_13: std_logic;
+ signal co5: std_logic;
+ signal iwcount_14: std_logic;
+ signal co7: std_logic;
+ signal wcount_14: std_logic;
+ signal co6: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_1: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_1: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_1: std_logic;
+ signal rfill_sub_0: std_logic;
+ signal rptr_0: std_logic;
+ signal scuba_vhi: std_logic;
+ signal rfill_sub_1: std_logic;
+ signal rfill_sub_2: std_logic;
+ signal co0_2: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rfill_sub_3: std_logic;
+ signal rfill_sub_4: std_logic;
+ signal co1_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rfill_sub_5: std_logic;
+ signal rfill_sub_6: std_logic;
+ signal co2_2: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rfill_sub_7: std_logic;
+ signal rfill_sub_8: std_logic;
+ signal co3_2: std_logic;
+ signal rptr_7: std_logic;
+ signal rptr_8: std_logic;
+ signal rfill_sub_9: std_logic;
+ signal co4_2: std_logic;
+ signal rfill_sub_msb: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r5: std_logic;
+ signal wcount_r6: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_r7: std_logic;
+ signal wcount_r8: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_r9: std_logic;
+ signal wcount_r10: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_3: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal wcount_r12: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_r13: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal rcount_8: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_4: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_w0: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_w1: std_logic;
+ signal rcount_w2: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_w3: std_logic;
+ signal rcount_w4: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co4_3: std_logic;
+ signal rcount_w5: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal co5_1: std_logic;
+ signal rcount_w7: std_logic;
+ signal rcount_w8: std_logic;
+ signal wcount_12: std_logic;
+ signal wcount_13: std_logic;
+ signal co6_1: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
+ attribute initval of LUT4_32 : label is "0x6996";
+ attribute initval of LUT4_31 : label is "0x6996";
+ attribute initval of LUT4_30 : label is "0x6996";
+ attribute initval of LUT4_29 : label is "0x6996";
+ attribute initval of LUT4_28 : label is "0x6996";
+ attribute initval of LUT4_27 : label is "0x6996";
+ attribute initval of LUT4_26 : label is "0x6996";
+ attribute initval of LUT4_25 : label is "0x6996";
+ attribute initval of LUT4_24 : label is "0x6996";
+ attribute initval of LUT4_23 : label is "0x6996";
+ attribute initval of LUT4_22 : label is "0x6996";
+ attribute initval of LUT4_21 : label is "0x6996";
+ attribute initval of LUT4_20 : label is "0x6996";
+ attribute initval of LUT4_19 : label is "0x6996";
+ attribute initval of LUT4_18 : label is "0x6996";
+ attribute initval of LUT4_17 : label is "0x6996";
+ attribute initval of LUT4_16 : label is "0x6996";
+ attribute initval of LUT4_15 : label is "0x6996";
+ attribute initval of LUT4_14 : label is "0x6996";
+ attribute initval of LUT4_13 : label is "0x6996";
+ attribute initval of LUT4_12 : label is "0x6996";
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x6996";
+ attribute initval of LUT4_6 : label is "0x6996";
+ attribute initval of LUT4_5 : label is "0x6996";
+ attribute initval of LUT4_4 : label is "0x6996";
+ attribute initval of LUT4_3 : label is "0x0410";
+ attribute initval of LUT4_2 : label is "0x1004";
+ attribute initval of LUT4_1 : label is "0x0140";
+ attribute initval of LUT4_0 : label is "0x4001";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_1bit_to_32bit.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute REGMODE_A of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "1";
+ attribute GSR of FF_136 : label is "ENABLED";
+ attribute GSR of FF_135 : label is "ENABLED";
+ attribute GSR of FF_134 : label is "ENABLED";
+ attribute GSR of FF_133 : label is "ENABLED";
+ attribute GSR of FF_132 : label is "ENABLED";
+ attribute GSR of FF_131 : label is "ENABLED";
+ attribute GSR of FF_130 : label is "ENABLED";
+ attribute GSR of FF_129 : label is "ENABLED";
+ attribute GSR of FF_128 : label is "ENABLED";
+ attribute GSR of FF_127 : label is "ENABLED";
+ attribute GSR of FF_126 : label is "ENABLED";
+ attribute GSR of FF_125 : label is "ENABLED";
+ attribute GSR of FF_124 : label is "ENABLED";
+ attribute GSR of FF_123 : label is "ENABLED";
+ attribute GSR of FF_122 : label is "ENABLED";
+ attribute GSR of FF_121 : label is "ENABLED";
+ attribute GSR of FF_120 : label is "ENABLED";
+ attribute GSR of FF_119 : label is "ENABLED";
+ attribute GSR of FF_118 : label is "ENABLED";
+ attribute GSR of FF_117 : label is "ENABLED";
+ attribute GSR of FF_116 : label is "ENABLED";
+ attribute GSR of FF_115 : label is "ENABLED";
+ attribute GSR of FF_114 : label is "ENABLED";
+ attribute GSR of FF_113 : label is "ENABLED";
+ attribute GSR of FF_112 : label is "ENABLED";
+ attribute GSR of FF_111 : label is "ENABLED";
+ attribute GSR of FF_110 : label is "ENABLED";
+ attribute GSR of FF_109 : label is "ENABLED";
+ attribute GSR of FF_108 : label is "ENABLED";
+ attribute GSR of FF_107 : label is "ENABLED";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t26: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t25: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t24: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t23: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t22: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t21: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t20: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t19: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t18: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t17: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t16: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t15: XOR2
+ port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+ XOR2_t14: XOR2
+ port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+ XOR2_t13: XOR2
+ port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
+
+ XOR2_t12: XOR2
+ port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
+
+ XOR2_t11: XOR2
+ port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
+
+ XOR2_t10: XOR2
+ port map (A=>wcount_13, B=>wcount_14, Z=>w_gdata_13);
+
+ XOR2_t9: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t8: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t7: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t6: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+ LUT4_32: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
+ AD1=>w_gcount_r213, AD0=>w_gcount_r214,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_31: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
+ AD1=>w_gcount_r29, AD0=>w_gcount_r210,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_30: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
+ AD1=>w_gcount_r25, AD0=>w_gcount_r26,
+ DO0=>w_g2b_xor_cluster_2);
+
+ LUT4_29: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r213, AD2=>w_gcount_r214, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r13);
+
+ LUT4_28: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213,
+ AD1=>w_gcount_r214, AD0=>scuba_vlo, DO0=>wcount_r12);
+
+ LUT4_27: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
+ AD1=>w_gcount_r212, AD0=>wcount_r13, DO0=>wcount_r10);
+
+ LUT4_26: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
+ AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9);
+
+ LUT4_25: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
+ AD1=>w_gcount_r210, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r8);
+
+ LUT4_24: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r7);
+
+ LUT4_23: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r6);
+
+ LUT4_22: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r25, AD0=>w_gcount_r26, DO0=>wcount_r5);
+
+ LUT4_21: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
+ AD1=>w_gcount_r26, AD0=>scuba_vlo,
+ DO0=>w_g2b_xor_cluster_2_1);
+
+ LUT4_20: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r4);
+
+ LUT4_19: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r3);
+
+ LUT4_18: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r22, DO0=>wcount_r2);
+
+ LUT4_17: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3);
+
+ LUT4_16: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
+ DO0=>wcount_r1);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>scuba_vlo,
+ DO0=>w_g2b_xor_cluster_3_1);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3_1,
+ DO0=>wcount_r0);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
+ AD1=>r_gcount_w28, AD0=>r_gcount_w29,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>r_gcount_w25,
+ DO0=>r_g2b_xor_cluster_1);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w8);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
+ AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
+ AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+ XOR2_t0: XOR2
+ port map (A=>w_gcount_r214, B=>rptr_9, Z=>rfill_sub_msb);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r214,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r214,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_14, AD2=>wcount_14, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ pdp_ram_0_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 36,
+ DATA_WIDTH_A=> 1)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>wptr_0, ADA1=>wptr_1, ADA2=>wptr_2, ADA3=>wptr_3,
+ ADA4=>wptr_4, ADA5=>wptr_5, ADA6=>wptr_6, ADA7=>wptr_7,
+ ADA8=>wptr_8, ADA9=>wptr_9, ADA10=>wptr_10, ADA11=>wptr_11,
+ ADA12=>wptr_12, ADA13=>wptr_13, CEA=>wren_i, CLKA=>WrClock,
+ WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo,
+ ADB4=>scuba_vlo, ADB5=>rptr_0, ADB6=>rptr_1, ADB7=>rptr_2,
+ ADB8=>rptr_3, ADB9=>rptr_4, ADB10=>rptr_5, ADB11=>rptr_6,
+ ADB12=>rptr_7, ADB13=>rptr_8, CEB=>scuba_vhi, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>rden_i, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>Q(0), DOA1=>Q(1),
+ DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6),
+ DOA7=>Q(7), DOA8=>open, DOA9=>Q(8), DOA10=>Q(9),
+ DOA11=>Q(10), DOA12=>Q(11), DOA13=>Q(12), DOA14=>Q(13),
+ DOA15=>Q(14), DOA16=>Q(15), DOA17=>open, DOB0=>Q(16),
+ DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>Q(20),
+ DOB5=>Q(21), DOB6=>Q(22), DOB7=>Q(23), DOB8=>open,
+ DOB9=>Q(24), DOB10=>Q(25), DOB11=>Q(26), DOB12=>Q(27),
+ DOB13=>Q(28), DOB14=>Q(29), DOB15=>Q(30), DOB16=>Q(31),
+ DOB17=>open);
+
+ FF_136: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_135: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_134: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_133: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_132: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_131: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_130: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_129: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_128: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_127: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_126: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_125: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_124: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_123: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_13);
+
+ FF_122: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_14);
+
+ FF_121: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_120: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_119: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_118: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_117: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_116: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_115: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_114: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_113: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_112: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_9);
+
+ FF_111: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_10);
+
+ FF_110: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_11);
+
+ FF_109: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_12);
+
+ FF_108: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_13);
+
+ FF_107: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_14);
+
+ FF_106: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_105: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_104: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_103: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_102: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_101: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_100: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_99: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_98: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_97: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_96: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_95: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_94: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_12);
+
+ FF_93: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_13);
+
+ FF_92: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_14, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_14);
+
+ FF_91: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_90: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_89: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_88: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_87: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_7);
+
+ FF_83: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_8);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_9);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_7);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_8);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_9);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_7);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_8);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_9);
+
+ FF_61: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_60: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_59: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_58: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_57: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_56: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_55: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_54: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_53: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_52: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+ FF_51: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r10);
+
+ FF_50: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r11);
+
+ FF_49: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r12);
+
+ FF_48: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r13);
+
+ FF_47: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_14, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r14);
+
+ FF_46: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_45: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_44: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_43: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_42: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_41: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_40: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_39: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+ FF_38: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+ FF_37: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+ FF_36: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_35: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_34: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_33: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_32: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_31: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_30: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_29: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_28: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_27: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r29);
+
+ FF_26: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r210);
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r211);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r212);
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r213);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r14, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r214);
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_gctr_5: CU2
+ port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
+ NC0=>iwcount_10, NC1=>iwcount_11);
+
+ w_gctr_6: CU2
+ port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
+ NC0=>iwcount_12, NC1=>iwcount_13);
+
+ w_gctr_7: CU2
+ port map (CI=>co6, PC0=>wcount_14, PC1=>scuba_vlo, CO=>co7,
+ NC0=>iwcount_14, NC1=>open);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_gctr_4: CU2
+ port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ rfill_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>wcount_r5, B0=>scuba_vlo,
+ B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
+ S1=>rfill_sub_0);
+
+ rfill_1: FSUB2B
+ port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_1, B1=>rptr_2,
+ BI=>co0_2, BOUT=>co1_2, S0=>rfill_sub_1, S1=>rfill_sub_2);
+
+ rfill_2: FSUB2B
+ port map (A0=>wcount_r8, A1=>wcount_r9, B0=>rptr_3, B1=>rptr_4,
+ BI=>co1_2, BOUT=>co2_2, S0=>rfill_sub_3, S1=>rfill_sub_4);
+
+ rfill_3: FSUB2B
+ port map (A0=>wcount_r10, A1=>w_g2b_xor_cluster_0, B0=>rptr_5,
+ B1=>rptr_6, BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5,
+ S1=>rfill_sub_6);
+
+ rfill_4: FSUB2B
+ port map (A0=>wcount_r12, A1=>wcount_r13, B0=>rptr_7, B1=>rptr_8,
+ BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7, S1=>rfill_sub_8);
+
+ rfill_5: FSUB2B
+ port map (A0=>rfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co4_2, BOUT=>open, S0=>rfill_sub_9,
+ S1=>open);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r5,
+ B1=>wcount_r6, CI=>cmp_ci, GE=>co0_3);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r7,
+ B1=>wcount_r8, CI=>co0_3, GE=>co1_3);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r9,
+ B1=>wcount_r10, CI=>co1_3, GE=>co2_3);
+
+ empty_cmp_3: AGEB2
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
+ B1=>wcount_r12, CI=>co2_3, GE=>co3_3);
+
+ empty_cmp_4: AGEB2
+ port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r13,
+ B1=>empty_cmp_clr, CI=>co3_3, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_4, GE=>co1_4);
+
+ full_cmp_2: AGEB2
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>scuba_vlo,
+ B1=>rcount_w0, CI=>co1_4, GE=>co2_4);
+
+ full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w1,
+ B1=>rcount_w2, CI=>co2_4, GE=>co3_4);
+
+ full_cmp_4: AGEB2
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w3,
+ B1=>rcount_w4, CI=>co3_4, GE=>co4_3);
+
+ full_cmp_5: AGEB2
+ port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w5,
+ B1=>r_g2b_xor_cluster_0, CI=>co4_3, GE=>co5_1);
+
+ full_cmp_6: AGEB2
+ port map (A0=>wcount_12, A1=>wcount_13, B0=>rcount_w7,
+ B1=>rcount_w8, CI=>co5_1, GE=>co6_1);
+
+ full_cmp_7: AGEB2
+ port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
+ B1=>scuba_vlo, CI=>co6_1, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_1bit_to_32bit is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp2m.FSUB2B(V); end for;
+ for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:OR2 use entity ecp2m.OR2(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]
+Family=latticeecp2m
+PartType=LFE2M100E
+PartName=LFE2M100E-5F900C
+SpeedGrade=-5
+Package=FPBGA900
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.3
+ModuleName=fifo_2bit_to_32bit
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/09/2010
+Time=10:51:07
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=8192
+Width=2
+RDepth=512
+RWidth=32
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=1
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.3
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 8192 -width 2 -depth 8192 -rdata_width 32 -regout -no_enable -pe -1 -pf -1 -rfill -e
+
+-- Mon Aug 9 10:51:08 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_2bit_to_32bit is
+ port (
+ Data: in std_logic_vector(1 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ RCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_2bit_to_32bit;
+
+architecture Structure of fifo_2bit_to_32bit is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal wcount_r3: std_logic;
+ signal w_g2b_xor_cluster_2_1: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r1: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_3: std_logic;
+ signal w_g2b_xor_cluster_2: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
+ signal r_g2b_xor_cluster_1: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
+ signal w_gdata_8: std_logic;
+ signal w_gdata_9: std_logic;
+ signal w_gdata_10: std_logic;
+ signal w_gdata_11: std_logic;
+ signal w_gdata_12: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal wptr_12: std_logic;
+ signal wptr_13: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal r_gdata_6: std_logic;
+ signal r_gdata_7: std_logic;
+ signal r_gdata_8: std_logic;
+ signal rptr_9: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
+ signal w_gcount_9: std_logic;
+ signal w_gcount_10: std_logic;
+ signal w_gcount_11: std_logic;
+ signal w_gcount_12: std_logic;
+ signal w_gcount_13: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal r_gcount_7: std_logic;
+ signal r_gcount_8: std_logic;
+ signal r_gcount_9: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
+ signal w_gcount_r29: std_logic;
+ signal w_gcount_r9: std_logic;
+ signal w_gcount_r210: std_logic;
+ signal w_gcount_r10: std_logic;
+ signal w_gcount_r211: std_logic;
+ signal w_gcount_r11: std_logic;
+ signal w_gcount_r212: std_logic;
+ signal w_gcount_r12: std_logic;
+ signal w_gcount_r213: std_logic;
+ signal w_gcount_r13: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal r_gcount_w27: std_logic;
+ signal r_gcount_w7: std_logic;
+ signal r_gcount_w28: std_logic;
+ signal r_gcount_w8: std_logic;
+ signal r_gcount_w29: std_logic;
+ signal r_gcount_w9: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4: std_logic;
+ signal iwcount_12: std_logic;
+ signal iwcount_13: std_logic;
+ signal co6: std_logic;
+ signal wcount_13: std_logic;
+ signal co5: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_1: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_1: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_1: std_logic;
+ signal rfill_sub_0: std_logic;
+ signal rptr_0: std_logic;
+ signal scuba_vhi: std_logic;
+ signal rfill_sub_1: std_logic;
+ signal rfill_sub_2: std_logic;
+ signal co0_2: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rfill_sub_3: std_logic;
+ signal rfill_sub_4: std_logic;
+ signal co1_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rfill_sub_5: std_logic;
+ signal rfill_sub_6: std_logic;
+ signal co2_2: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rfill_sub_7: std_logic;
+ signal rfill_sub_8: std_logic;
+ signal co3_2: std_logic;
+ signal rptr_7: std_logic;
+ signal rptr_8: std_logic;
+ signal rfill_sub_9: std_logic;
+ signal co4_2: std_logic;
+ signal rfill_sub_msb: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r4: std_logic;
+ signal wcount_r5: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_r6: std_logic;
+ signal wcount_r7: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_r8: std_logic;
+ signal wcount_r9: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_3: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal wcount_r11: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_r12: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal rcount_8: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_4: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_w4: std_logic;
+ signal rcount_w5: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co4_3: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal rcount_w7: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal co5_1: std_logic;
+ signal rcount_w8: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal wcount_12: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
+ attribute initval of LUT4_30 : label is "0x6996";
+ attribute initval of LUT4_29 : label is "0x6996";
+ attribute initval of LUT4_28 : label is "0x6996";
+ attribute initval of LUT4_27 : label is "0x6996";
+ attribute initval of LUT4_26 : label is "0x6996";
+ attribute initval of LUT4_25 : label is "0x6996";
+ attribute initval of LUT4_24 : label is "0x6996";
+ attribute initval of LUT4_23 : label is "0x6996";
+ attribute initval of LUT4_22 : label is "0x6996";
+ attribute initval of LUT4_21 : label is "0x6996";
+ attribute initval of LUT4_20 : label is "0x6996";
+ attribute initval of LUT4_19 : label is "0x6996";
+ attribute initval of LUT4_18 : label is "0x6996";
+ attribute initval of LUT4_17 : label is "0x6996";
+ attribute initval of LUT4_16 : label is "0x6996";
+ attribute initval of LUT4_15 : label is "0x6996";
+ attribute initval of LUT4_14 : label is "0x6996";
+ attribute initval of LUT4_13 : label is "0x6996";
+ attribute initval of LUT4_12 : label is "0x6996";
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x6996";
+ attribute initval of LUT4_6 : label is "0x6996";
+ attribute initval of LUT4_5 : label is "0x6996";
+ attribute initval of LUT4_4 : label is "0x6996";
+ attribute initval of LUT4_3 : label is "0x0410";
+ attribute initval of LUT4_2 : label is "0x1004";
+ attribute initval of LUT4_1 : label is "0x0140";
+ attribute initval of LUT4_0 : label is "0x4001";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_2bit_to_32bit.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute REGMODE_A of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "2";
+ attribute GSR of FF_131 : label is "ENABLED";
+ attribute GSR of FF_130 : label is "ENABLED";
+ attribute GSR of FF_129 : label is "ENABLED";
+ attribute GSR of FF_128 : label is "ENABLED";
+ attribute GSR of FF_127 : label is "ENABLED";
+ attribute GSR of FF_126 : label is "ENABLED";
+ attribute GSR of FF_125 : label is "ENABLED";
+ attribute GSR of FF_124 : label is "ENABLED";
+ attribute GSR of FF_123 : label is "ENABLED";
+ attribute GSR of FF_122 : label is "ENABLED";
+ attribute GSR of FF_121 : label is "ENABLED";
+ attribute GSR of FF_120 : label is "ENABLED";
+ attribute GSR of FF_119 : label is "ENABLED";
+ attribute GSR of FF_118 : label is "ENABLED";
+ attribute GSR of FF_117 : label is "ENABLED";
+ attribute GSR of FF_116 : label is "ENABLED";
+ attribute GSR of FF_115 : label is "ENABLED";
+ attribute GSR of FF_114 : label is "ENABLED";
+ attribute GSR of FF_113 : label is "ENABLED";
+ attribute GSR of FF_112 : label is "ENABLED";
+ attribute GSR of FF_111 : label is "ENABLED";
+ attribute GSR of FF_110 : label is "ENABLED";
+ attribute GSR of FF_109 : label is "ENABLED";
+ attribute GSR of FF_108 : label is "ENABLED";
+ attribute GSR of FF_107 : label is "ENABLED";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t25: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t24: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t23: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t22: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t21: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t20: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t19: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t18: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t17: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t16: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t15: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t14: XOR2
+ port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+ XOR2_t13: XOR2
+ port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+ XOR2_t12: XOR2
+ port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
+
+ XOR2_t11: XOR2
+ port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
+
+ XOR2_t10: XOR2
+ port map (A=>wcount_12, B=>wcount_13, Z=>w_gdata_12);
+
+ XOR2_t9: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t8: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t7: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t6: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+ LUT4_30: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
+ AD1=>w_gcount_r212, AD0=>w_gcount_r213,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_29: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
+ AD1=>w_gcount_r28, AD0=>w_gcount_r29,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_28: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>w_gcount_r25,
+ DO0=>w_g2b_xor_cluster_2);
+
+ LUT4_27: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r212, AD2=>w_gcount_r213, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r12);
+
+ LUT4_26: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212,
+ AD1=>w_gcount_r213, AD0=>scuba_vlo, DO0=>wcount_r11);
+
+ LUT4_25: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
+ AD1=>w_gcount_r211, AD0=>wcount_r12, DO0=>wcount_r9);
+
+ LUT4_24: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
+ AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);
+
+ LUT4_23: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
+ AD1=>w_gcount_r29, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r7);
+
+ LUT4_22: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r6);
+
+ LUT4_21: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r25, AD0=>scuba_vlo, DO0=>wcount_r5);
+
+ LUT4_20: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r24, AD0=>w_gcount_r25, DO0=>wcount_r4);
+
+ LUT4_19: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
+ AD1=>w_gcount_r25, AD0=>scuba_vlo,
+ DO0=>w_g2b_xor_cluster_2_1);
+
+ LUT4_18: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r3);
+
+ LUT4_17: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+ LUT4_16: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r21, DO0=>wcount_r1);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>w_g2b_xor_cluster_3);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_g2b_xor_cluster_3,
+ DO0=>wcount_r0);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
+ AD1=>r_gcount_w28, AD0=>r_gcount_w29,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>r_gcount_w25,
+ DO0=>r_g2b_xor_cluster_1);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w8);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
+ AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
+ AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+ XOR2_t0: XOR2
+ port map (A=>w_gcount_r213, B=>rptr_9, Z=>rfill_sub_msb);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r213,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r213,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_13, AD2=>wcount_13, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_13, AD2=>wcount_13, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ pdp_ram_0_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 36,
+ DATA_WIDTH_A=> 2)
+ -- synopsys translate_on
+ port map (DIA0=>scuba_vlo, DIA1=>Data(1), DIA2=>scuba_vlo,
+ DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>Data(0),
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>wptr_0, ADA2=>wptr_1, ADA3=>wptr_2,
+ ADA4=>wptr_3, ADA5=>wptr_4, ADA6=>wptr_5, ADA7=>wptr_6,
+ ADA8=>wptr_7, ADA9=>wptr_8, ADA10=>wptr_9, ADA11=>wptr_10,
+ ADA12=>wptr_11, ADA13=>wptr_12, CEA=>wren_i, CLKA=>WrClock,
+ WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo,
+ ADB4=>scuba_vlo, ADB5=>rptr_0, ADB6=>rptr_1, ADB7=>rptr_2,
+ ADB8=>rptr_3, ADB9=>rptr_4, ADB10=>rptr_5, ADB11=>rptr_6,
+ ADB12=>rptr_7, ADB13=>rptr_8, CEB=>scuba_vhi, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>rden_i, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>Q(0), DOA1=>Q(1),
+ DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6),
+ DOA7=>Q(7), DOA8=>open, DOA9=>Q(8), DOA10=>Q(9),
+ DOA11=>Q(10), DOA12=>Q(11), DOA13=>Q(12), DOA14=>Q(13),
+ DOA15=>Q(14), DOA16=>Q(15), DOA17=>open, DOB0=>Q(16),
+ DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>Q(20),
+ DOB5=>Q(21), DOB6=>Q(22), DOB7=>Q(23), DOB8=>open,
+ DOB9=>Q(24), DOB10=>Q(25), DOB11=>Q(26), DOB12=>Q(27),
+ DOB13=>Q(28), DOB14=>Q(29), DOB15=>Q(30), DOB16=>Q(31),
+ DOB17=>open);
+
+ FF_131: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_130: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_129: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_128: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_127: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_126: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_125: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_124: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_123: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_122: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_121: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_120: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_119: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_118: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_13);
+
+ FF_117: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_116: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_115: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_114: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_113: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_112: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_111: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_110: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_109: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_108: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_9);
+
+ FF_107: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_10);
+
+ FF_106: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_11);
+
+ FF_105: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_12);
+
+ FF_104: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_13);
+
+ FF_103: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_102: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_101: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_100: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_99: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_98: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_97: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_96: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_95: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_94: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_93: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_92: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_91: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_12);
+
+ FF_90: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_13, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_13);
+
+ FF_89: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_88: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_87: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_83: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_7);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_8);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_9);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_7);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_8);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_9);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_7);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_8);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_9);
+
+ FF_59: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_58: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_57: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_56: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_55: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_54: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_53: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_52: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_51: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_50: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+ FF_49: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r10);
+
+ FF_48: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r11);
+
+ FF_47: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r12);
+
+ FF_46: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_13, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r13);
+
+ FF_45: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_44: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_43: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_42: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_41: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_40: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_39: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_38: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+ FF_37: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+ FF_36: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+ FF_35: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_34: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_33: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_32: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_31: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_30: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_29: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_28: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_27: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_26: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r29);
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r210);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r211);
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r212);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r13, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r213);
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_gctr_5: CU2
+ port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
+ NC0=>iwcount_10, NC1=>iwcount_11);
+
+ w_gctr_6: CU2
+ port map (CI=>co5, PC0=>wcount_12, PC1=>wcount_13, CO=>co6,
+ NC0=>iwcount_12, NC1=>iwcount_13);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_gctr_4: CU2
+ port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ rfill_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>wcount_r4, B0=>scuba_vlo,
+ B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
+ S1=>rfill_sub_0);
+
+ rfill_1: FSUB2B
+ port map (A0=>wcount_r5, A1=>wcount_r6, B0=>rptr_1, B1=>rptr_2,
+ BI=>co0_2, BOUT=>co1_2, S0=>rfill_sub_1, S1=>rfill_sub_2);
+
+ rfill_2: FSUB2B
+ port map (A0=>wcount_r7, A1=>wcount_r8, B0=>rptr_3, B1=>rptr_4,
+ BI=>co1_2, BOUT=>co2_2, S0=>rfill_sub_3, S1=>rfill_sub_4);
+
+ rfill_3: FSUB2B
+ port map (A0=>wcount_r9, A1=>w_g2b_xor_cluster_0, B0=>rptr_5,
+ B1=>rptr_6, BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5,
+ S1=>rfill_sub_6);
+
+ rfill_4: FSUB2B
+ port map (A0=>wcount_r11, A1=>wcount_r12, B0=>rptr_7, B1=>rptr_8,
+ BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7, S1=>rfill_sub_8);
+
+ rfill_5: FSUB2B
+ port map (A0=>rfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co4_2, BOUT=>open, S0=>rfill_sub_9,
+ S1=>open);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r4,
+ B1=>wcount_r5, CI=>cmp_ci, GE=>co0_3);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r6,
+ B1=>wcount_r7, CI=>co0_3, GE=>co1_3);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r8,
+ B1=>wcount_r9, CI=>co1_3, GE=>co2_3);
+
+ empty_cmp_3: AGEB2
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
+ B1=>wcount_r11, CI=>co2_3, GE=>co3_3);
+
+ empty_cmp_4: AGEB2
+ port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r12,
+ B1=>empty_cmp_clr, CI=>co3_3, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>co0_4, GE=>co1_4);
+
+ full_cmp_2: AGEB2
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w0,
+ B1=>rcount_w1, CI=>co1_4, GE=>co2_4);
+
+ full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w2,
+ B1=>rcount_w3, CI=>co2_4, GE=>co3_4);
+
+ full_cmp_4: AGEB2
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w4,
+ B1=>rcount_w5, CI=>co3_4, GE=>co4_3);
+
+ full_cmp_5: AGEB2
+ port map (A0=>wcount_10, A1=>wcount_11, B0=>r_g2b_xor_cluster_0,
+ B1=>rcount_w7, CI=>co4_3, GE=>co5_1);
+
+ full_cmp_6: AGEB2
+ port map (A0=>wcount_12, A1=>full_cmp_set, B0=>rcount_w8,
+ B1=>full_cmp_clr, CI=>co5_1, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_2bit_to_32bit is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp2m.FSUB2B(V); end for;
+ for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:OR2 use entity ecp2m.OR2(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]
+Family=latticeecp2m
+PartType=LFE2M100E
+PartName=LFE2M100E-5F900C
+SpeedGrade=-5
+Package=FPBGA900
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.3
+ModuleName=fifo_4bit_to_32bit
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/09/2010
+Time=10:52:08
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=4096
+Width=4
+RDepth=512
+RWidth=32
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=1
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.3
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 4096 -width 4 -depth 4096 -rdata_width 32 -regout -no_enable -pe -1 -pf -1 -rfill -e
+
+-- Mon Aug 9 10:52:08 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_4bit_to_32bit is
+ port (
+ Data: in std_logic_vector(3 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ RCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_4bit_to_32bit;
+
+architecture Structure of fifo_4bit_to_32bit is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal wcount_r2: std_logic;
+ signal w_g2b_xor_cluster_2_1: std_logic;
+ signal wcount_r1: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_2: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
+ signal r_g2b_xor_cluster_1: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
+ signal w_gdata_8: std_logic;
+ signal w_gdata_9: std_logic;
+ signal w_gdata_10: std_logic;
+ signal w_gdata_11: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal wptr_12: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal r_gdata_6: std_logic;
+ signal r_gdata_7: std_logic;
+ signal r_gdata_8: std_logic;
+ signal rptr_9: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
+ signal w_gcount_9: std_logic;
+ signal w_gcount_10: std_logic;
+ signal w_gcount_11: std_logic;
+ signal w_gcount_12: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal r_gcount_7: std_logic;
+ signal r_gcount_8: std_logic;
+ signal r_gcount_9: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
+ signal w_gcount_r29: std_logic;
+ signal w_gcount_r9: std_logic;
+ signal w_gcount_r210: std_logic;
+ signal w_gcount_r10: std_logic;
+ signal w_gcount_r211: std_logic;
+ signal w_gcount_r11: std_logic;
+ signal w_gcount_r212: std_logic;
+ signal w_gcount_r12: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal r_gcount_w27: std_logic;
+ signal r_gcount_w7: std_logic;
+ signal r_gcount_w28: std_logic;
+ signal r_gcount_w8: std_logic;
+ signal r_gcount_w29: std_logic;
+ signal r_gcount_w9: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co4: std_logic;
+ signal iwcount_12: std_logic;
+ signal co6: std_logic;
+ signal wcount_12: std_logic;
+ signal co5: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_1: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_1: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_1: std_logic;
+ signal rfill_sub_0: std_logic;
+ signal rptr_0: std_logic;
+ signal scuba_vhi: std_logic;
+ signal rfill_sub_1: std_logic;
+ signal rfill_sub_2: std_logic;
+ signal co0_2: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rfill_sub_3: std_logic;
+ signal rfill_sub_4: std_logic;
+ signal co1_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rfill_sub_5: std_logic;
+ signal rfill_sub_6: std_logic;
+ signal co2_2: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rfill_sub_7: std_logic;
+ signal rfill_sub_8: std_logic;
+ signal co3_2: std_logic;
+ signal rptr_7: std_logic;
+ signal rptr_8: std_logic;
+ signal rfill_sub_9: std_logic;
+ signal co4_2: std_logic;
+ signal rfill_sub_msb: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r3: std_logic;
+ signal wcount_r4: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_r5: std_logic;
+ signal wcount_r6: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_r7: std_logic;
+ signal wcount_r8: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_3: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal wcount_r10: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_r11: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal rcount_8: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_w0: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_w1: std_logic;
+ signal rcount_w2: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_w3: std_logic;
+ signal rcount_w4: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_4: std_logic;
+ signal rcount_w5: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co4_3: std_logic;
+ signal rcount_w7: std_logic;
+ signal rcount_w8: std_logic;
+ signal wcount_10: std_logic;
+ signal wcount_11: std_logic;
+ signal co5_1: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
+ attribute initval of LUT4_28 : label is "0x6996";
+ attribute initval of LUT4_27 : label is "0x6996";
+ attribute initval of LUT4_26 : label is "0x6996";
+ attribute initval of LUT4_25 : label is "0x6996";
+ attribute initval of LUT4_24 : label is "0x6996";
+ attribute initval of LUT4_23 : label is "0x6996";
+ attribute initval of LUT4_22 : label is "0x6996";
+ attribute initval of LUT4_21 : label is "0x6996";
+ attribute initval of LUT4_20 : label is "0x6996";
+ attribute initval of LUT4_19 : label is "0x6996";
+ attribute initval of LUT4_18 : label is "0x6996";
+ attribute initval of LUT4_17 : label is "0x6996";
+ attribute initval of LUT4_16 : label is "0x6996";
+ attribute initval of LUT4_15 : label is "0x6996";
+ attribute initval of LUT4_14 : label is "0x6996";
+ attribute initval of LUT4_13 : label is "0x6996";
+ attribute initval of LUT4_12 : label is "0x6996";
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x6996";
+ attribute initval of LUT4_6 : label is "0x6996";
+ attribute initval of LUT4_5 : label is "0x6996";
+ attribute initval of LUT4_4 : label is "0x6996";
+ attribute initval of LUT4_3 : label is "0x0410";
+ attribute initval of LUT4_2 : label is "0x1004";
+ attribute initval of LUT4_1 : label is "0x0140";
+ attribute initval of LUT4_0 : label is "0x4001";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_4bit_to_32bit.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute REGMODE_A of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "4";
+ attribute GSR of FF_126 : label is "ENABLED";
+ attribute GSR of FF_125 : label is "ENABLED";
+ attribute GSR of FF_124 : label is "ENABLED";
+ attribute GSR of FF_123 : label is "ENABLED";
+ attribute GSR of FF_122 : label is "ENABLED";
+ attribute GSR of FF_121 : label is "ENABLED";
+ attribute GSR of FF_120 : label is "ENABLED";
+ attribute GSR of FF_119 : label is "ENABLED";
+ attribute GSR of FF_118 : label is "ENABLED";
+ attribute GSR of FF_117 : label is "ENABLED";
+ attribute GSR of FF_116 : label is "ENABLED";
+ attribute GSR of FF_115 : label is "ENABLED";
+ attribute GSR of FF_114 : label is "ENABLED";
+ attribute GSR of FF_113 : label is "ENABLED";
+ attribute GSR of FF_112 : label is "ENABLED";
+ attribute GSR of FF_111 : label is "ENABLED";
+ attribute GSR of FF_110 : label is "ENABLED";
+ attribute GSR of FF_109 : label is "ENABLED";
+ attribute GSR of FF_108 : label is "ENABLED";
+ attribute GSR of FF_107 : label is "ENABLED";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t24: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t23: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t22: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t21: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t20: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t19: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t18: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t17: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t16: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t15: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t14: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t13: XOR2
+ port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+ XOR2_t12: XOR2
+ port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+ XOR2_t11: XOR2
+ port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
+
+ XOR2_t10: XOR2
+ port map (A=>wcount_11, B=>wcount_12, Z=>w_gdata_11);
+
+ XOR2_t9: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t8: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t7: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t6: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+ LUT4_28: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
+ AD1=>w_gcount_r211, AD0=>w_gcount_r212,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_27: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
+ AD1=>w_gcount_r27, AD0=>w_gcount_r28,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_26: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>w_gcount_r24,
+ DO0=>w_g2b_xor_cluster_2);
+
+ LUT4_25: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r211, AD2=>w_gcount_r212, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r11);
+
+ LUT4_24: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211,
+ AD1=>w_gcount_r212, AD0=>scuba_vlo, DO0=>wcount_r10);
+
+ LUT4_23: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
+ AD1=>w_gcount_r210, AD0=>wcount_r11, DO0=>wcount_r8);
+
+ LUT4_22: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
+ AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
+
+ LUT4_21: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
+ AD1=>w_gcount_r28, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r6);
+
+ LUT4_20: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r5);
+
+ LUT4_19: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r4);
+
+ LUT4_18: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r23, AD0=>w_gcount_r24, DO0=>wcount_r3);
+
+ LUT4_17: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
+ AD1=>w_gcount_r24, AD0=>scuba_vlo,
+ DO0=>w_g2b_xor_cluster_2_1);
+
+ LUT4_16: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r2);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>w_gcount_r20, DO0=>wcount_r0);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
+ AD1=>r_gcount_w28, AD0=>r_gcount_w29,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>r_gcount_w25,
+ DO0=>r_g2b_xor_cluster_1);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w8);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
+ AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
+ AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+ XOR2_t0: XOR2
+ port map (A=>w_gcount_r212, B=>rptr_9, Z=>rfill_sub_msb);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r212,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r212,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_12, AD2=>wcount_12, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ pdp_ram_0_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 36,
+ DATA_WIDTH_A=> 4)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo,
+ DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
+ DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
+ DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
+ DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
+ ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1,
+ ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5,
+ ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>wptr_8, ADA11=>wptr_9,
+ ADA12=>wptr_10, ADA13=>wptr_11, CEA=>wren_i, CLKA=>WrClock,
+ WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo,
+ CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo,
+ DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo,
+ DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo,
+ DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo,
+ DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo,
+ DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo,
+ DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo,
+ ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>scuba_vlo,
+ ADB4=>scuba_vlo, ADB5=>rptr_0, ADB6=>rptr_1, ADB7=>rptr_2,
+ ADB8=>rptr_3, ADB9=>rptr_4, ADB10=>rptr_5, ADB11=>rptr_6,
+ ADB12=>rptr_7, ADB13=>rptr_8, CEB=>scuba_vhi, CLKB=>RdClock,
+ WEB=>scuba_vlo, CSB0=>rden_i, CSB1=>scuba_vlo,
+ CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>Q(0), DOA1=>Q(1),
+ DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6),
+ DOA7=>Q(7), DOA8=>open, DOA9=>Q(8), DOA10=>Q(9),
+ DOA11=>Q(10), DOA12=>Q(11), DOA13=>Q(12), DOA14=>Q(13),
+ DOA15=>Q(14), DOA16=>Q(15), DOA17=>open, DOB0=>Q(16),
+ DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19), DOB4=>Q(20),
+ DOB5=>Q(21), DOB6=>Q(22), DOB7=>Q(23), DOB8=>open,
+ DOB9=>Q(24), DOB10=>Q(25), DOB11=>Q(26), DOB12=>Q(27),
+ DOB13=>Q(28), DOB14=>Q(29), DOB15=>Q(30), DOB16=>Q(31),
+ DOB17=>open);
+
+ FF_126: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_125: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_124: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_123: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_122: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_121: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_120: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_119: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_118: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_117: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_116: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_115: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_114: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_12);
+
+ FF_113: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_112: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_111: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_110: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_109: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_108: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_107: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_106: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_105: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_104: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_9);
+
+ FF_103: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_10);
+
+ FF_102: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_11);
+
+ FF_101: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_12);
+
+ FF_100: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_99: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_98: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_97: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_96: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_95: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_94: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_93: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_92: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_91: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_90: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_89: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_88: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_12, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_12);
+
+ FF_87: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_85: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_83: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_7);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_8);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_9);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_7);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_8);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_9);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_7);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_8);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_9);
+
+ FF_57: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_56: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_55: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_54: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_53: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_52: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_51: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_50: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_49: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_48: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+ FF_47: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r10);
+
+ FF_46: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r11);
+
+ FF_45: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_12, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r12);
+
+ FF_44: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_43: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_42: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_41: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_40: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_39: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_38: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_37: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+ FF_36: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+ FF_35: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+ FF_34: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_33: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_32: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_31: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_30: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_29: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_28: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_27: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_26: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r29);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r210);
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r211);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r12, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r212);
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_gctr_5: CU2
+ port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
+ NC0=>iwcount_10, NC1=>iwcount_11);
+
+ w_gctr_6: CU2
+ port map (CI=>co5, PC0=>wcount_12, PC1=>scuba_vlo, CO=>co6,
+ NC0=>iwcount_12, NC1=>open);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_gctr_4: CU2
+ port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ rfill_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>wcount_r3, B0=>scuba_vlo,
+ B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
+ S1=>rfill_sub_0);
+
+ rfill_1: FSUB2B
+ port map (A0=>wcount_r4, A1=>wcount_r5, B0=>rptr_1, B1=>rptr_2,
+ BI=>co0_2, BOUT=>co1_2, S0=>rfill_sub_1, S1=>rfill_sub_2);
+
+ rfill_2: FSUB2B
+ port map (A0=>wcount_r6, A1=>wcount_r7, B0=>rptr_3, B1=>rptr_4,
+ BI=>co1_2, BOUT=>co2_2, S0=>rfill_sub_3, S1=>rfill_sub_4);
+
+ rfill_3: FSUB2B
+ port map (A0=>wcount_r8, A1=>w_g2b_xor_cluster_0, B0=>rptr_5,
+ B1=>rptr_6, BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5,
+ S1=>rfill_sub_6);
+
+ rfill_4: FSUB2B
+ port map (A0=>wcount_r10, A1=>wcount_r11, B0=>rptr_7, B1=>rptr_8,
+ BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7, S1=>rfill_sub_8);
+
+ rfill_5: FSUB2B
+ port map (A0=>rfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co4_2, BOUT=>open, S0=>rfill_sub_9,
+ S1=>open);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r3,
+ B1=>wcount_r4, CI=>cmp_ci, GE=>co0_3);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r5,
+ B1=>wcount_r6, CI=>co0_3, GE=>co1_3);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r7,
+ B1=>wcount_r8, CI=>co1_3, GE=>co2_3);
+
+ empty_cmp_3: AGEB2
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
+ B1=>wcount_r10, CI=>co2_3, GE=>co3_3);
+
+ empty_cmp_4: AGEB2
+ port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r11,
+ B1=>empty_cmp_clr, CI=>co3_3, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>scuba_vlo,
+ B1=>rcount_w0, CI=>co0_4, GE=>co1_4);
+
+ full_cmp_2: AGEB2
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w1,
+ B1=>rcount_w2, CI=>co1_4, GE=>co2_4);
+
+ full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w3,
+ B1=>rcount_w4, CI=>co2_4, GE=>co3_4);
+
+ full_cmp_4: AGEB2
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>rcount_w5,
+ B1=>r_g2b_xor_cluster_0, CI=>co3_4, GE=>co4_3);
+
+ full_cmp_5: AGEB2
+ port map (A0=>wcount_10, A1=>wcount_11, B0=>rcount_w7,
+ B1=>rcount_w8, CI=>co4_3, GE=>co5_1);
+
+ full_cmp_6: AGEB2
+ port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
+ B1=>scuba_vlo, CI=>co5_1, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_4bit_to_32bit is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp2m.FSUB2B(V); end for;
+ for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:OR2 use entity ecp2m.OR2(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]
+Family=latticeecp2m
+PartType=LFE2M100E
+PartName=LFE2M100E-5F900C
+SpeedGrade=-5
+Package=FPBGA900
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.3
+ModuleName=fifo_8bit_to_32bit
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=08/09/2010
+Time=10:57:30
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Based
+Depth=2048
+Width=8
+RDepth=512
+RWidth=32
+regout=1
+CtrlByRdEn=0
+EmpFlg=0
+PeMode=Static - Dual Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=0
+PfMode=Static - Dual Threshold
+PfAssert=508
+PfDeassert=506
+RDataCount=1
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.3
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 2048 -width 8 -depth 2048 -rdata_width 32 -regout -no_enable -pe -1 -pf -1 -rfill -e
+
+-- Mon Aug 9 10:57:30 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity fifo_8bit_to_32bit is
+ port (
+ Data: in std_logic_vector(7 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ RCNT: out std_logic_vector(9 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic);
+end fifo_8bit_to_32bit;
+
+architecture Structure of fifo_8bit_to_32bit is
+
+ -- internal signal declarations
+ signal invout_1: std_logic;
+ signal invout_0: std_logic;
+ signal wcount_r1: std_logic;
+ signal w_g2b_xor_cluster_2_1: std_logic;
+ signal wcount_r0: std_logic;
+ signal w_g2b_xor_cluster_2: std_logic;
+ signal w_g2b_xor_cluster_1: std_logic;
+ signal r_g2b_xor_cluster_1: std_logic;
+ signal w_gdata_0: std_logic;
+ signal w_gdata_1: std_logic;
+ signal w_gdata_2: std_logic;
+ signal w_gdata_3: std_logic;
+ signal w_gdata_4: std_logic;
+ signal w_gdata_5: std_logic;
+ signal w_gdata_6: std_logic;
+ signal w_gdata_7: std_logic;
+ signal w_gdata_8: std_logic;
+ signal w_gdata_9: std_logic;
+ signal w_gdata_10: std_logic;
+ signal wptr_0: std_logic;
+ signal wptr_1: std_logic;
+ signal wptr_2: std_logic;
+ signal wptr_3: std_logic;
+ signal wptr_4: std_logic;
+ signal wptr_5: std_logic;
+ signal wptr_6: std_logic;
+ signal wptr_7: std_logic;
+ signal wptr_8: std_logic;
+ signal wptr_9: std_logic;
+ signal wptr_10: std_logic;
+ signal wptr_11: std_logic;
+ signal r_gdata_0: std_logic;
+ signal r_gdata_1: std_logic;
+ signal r_gdata_2: std_logic;
+ signal r_gdata_3: std_logic;
+ signal r_gdata_4: std_logic;
+ signal r_gdata_5: std_logic;
+ signal r_gdata_6: std_logic;
+ signal r_gdata_7: std_logic;
+ signal r_gdata_8: std_logic;
+ signal rptr_9: std_logic;
+ signal w_gcount_0: std_logic;
+ signal w_gcount_1: std_logic;
+ signal w_gcount_2: std_logic;
+ signal w_gcount_3: std_logic;
+ signal w_gcount_4: std_logic;
+ signal w_gcount_5: std_logic;
+ signal w_gcount_6: std_logic;
+ signal w_gcount_7: std_logic;
+ signal w_gcount_8: std_logic;
+ signal w_gcount_9: std_logic;
+ signal w_gcount_10: std_logic;
+ signal w_gcount_11: std_logic;
+ signal r_gcount_0: std_logic;
+ signal r_gcount_1: std_logic;
+ signal r_gcount_2: std_logic;
+ signal r_gcount_3: std_logic;
+ signal r_gcount_4: std_logic;
+ signal r_gcount_5: std_logic;
+ signal r_gcount_6: std_logic;
+ signal r_gcount_7: std_logic;
+ signal r_gcount_8: std_logic;
+ signal r_gcount_9: std_logic;
+ signal w_gcount_r20: std_logic;
+ signal w_gcount_r0: std_logic;
+ signal w_gcount_r21: std_logic;
+ signal w_gcount_r1: std_logic;
+ signal w_gcount_r22: std_logic;
+ signal w_gcount_r2: std_logic;
+ signal w_gcount_r23: std_logic;
+ signal w_gcount_r3: std_logic;
+ signal w_gcount_r24: std_logic;
+ signal w_gcount_r4: std_logic;
+ signal w_gcount_r25: std_logic;
+ signal w_gcount_r5: std_logic;
+ signal w_gcount_r26: std_logic;
+ signal w_gcount_r6: std_logic;
+ signal w_gcount_r27: std_logic;
+ signal w_gcount_r7: std_logic;
+ signal w_gcount_r28: std_logic;
+ signal w_gcount_r8: std_logic;
+ signal w_gcount_r29: std_logic;
+ signal w_gcount_r9: std_logic;
+ signal w_gcount_r210: std_logic;
+ signal w_gcount_r10: std_logic;
+ signal w_gcount_r211: std_logic;
+ signal w_gcount_r11: std_logic;
+ signal r_gcount_w20: std_logic;
+ signal r_gcount_w0: std_logic;
+ signal r_gcount_w21: std_logic;
+ signal r_gcount_w1: std_logic;
+ signal r_gcount_w22: std_logic;
+ signal r_gcount_w2: std_logic;
+ signal r_gcount_w23: std_logic;
+ signal r_gcount_w3: std_logic;
+ signal r_gcount_w24: std_logic;
+ signal r_gcount_w4: std_logic;
+ signal r_gcount_w25: std_logic;
+ signal r_gcount_w5: std_logic;
+ signal r_gcount_w26: std_logic;
+ signal r_gcount_w6: std_logic;
+ signal r_gcount_w27: std_logic;
+ signal r_gcount_w7: std_logic;
+ signal r_gcount_w28: std_logic;
+ signal r_gcount_w8: std_logic;
+ signal r_gcount_w29: std_logic;
+ signal r_gcount_w9: std_logic;
+ signal empty_i: std_logic;
+ signal rRst: std_logic;
+ signal full_i: std_logic;
+ signal iwcount_0: std_logic;
+ signal iwcount_1: std_logic;
+ signal w_gctr_ci: std_logic;
+ signal iwcount_2: std_logic;
+ signal iwcount_3: std_logic;
+ signal co0: std_logic;
+ signal iwcount_4: std_logic;
+ signal iwcount_5: std_logic;
+ signal co1: std_logic;
+ signal iwcount_6: std_logic;
+ signal iwcount_7: std_logic;
+ signal co2: std_logic;
+ signal iwcount_8: std_logic;
+ signal iwcount_9: std_logic;
+ signal co3: std_logic;
+ signal iwcount_10: std_logic;
+ signal iwcount_11: std_logic;
+ signal co5: std_logic;
+ signal wcount_11: std_logic;
+ signal co4: std_logic;
+ signal ircount_0: std_logic;
+ signal ircount_1: std_logic;
+ signal r_gctr_ci: std_logic;
+ signal ircount_2: std_logic;
+ signal ircount_3: std_logic;
+ signal co0_1: std_logic;
+ signal ircount_4: std_logic;
+ signal ircount_5: std_logic;
+ signal co1_1: std_logic;
+ signal ircount_6: std_logic;
+ signal ircount_7: std_logic;
+ signal co2_1: std_logic;
+ signal ircount_8: std_logic;
+ signal ircount_9: std_logic;
+ signal co4_1: std_logic;
+ signal rcount_9: std_logic;
+ signal co3_1: std_logic;
+ signal rfill_sub_0: std_logic;
+ signal rptr_0: std_logic;
+ signal scuba_vhi: std_logic;
+ signal rfill_sub_1: std_logic;
+ signal rfill_sub_2: std_logic;
+ signal co0_2: std_logic;
+ signal rptr_1: std_logic;
+ signal rptr_2: std_logic;
+ signal rfill_sub_3: std_logic;
+ signal rfill_sub_4: std_logic;
+ signal co1_2: std_logic;
+ signal rptr_3: std_logic;
+ signal rptr_4: std_logic;
+ signal rfill_sub_5: std_logic;
+ signal rfill_sub_6: std_logic;
+ signal co2_2: std_logic;
+ signal rptr_5: std_logic;
+ signal rptr_6: std_logic;
+ signal rfill_sub_7: std_logic;
+ signal rfill_sub_8: std_logic;
+ signal co3_2: std_logic;
+ signal rptr_7: std_logic;
+ signal rptr_8: std_logic;
+ signal rfill_sub_9: std_logic;
+ signal co4_2: std_logic;
+ signal rfill_sub_msb: std_logic;
+ signal rden_i: std_logic;
+ signal cmp_ci: std_logic;
+ signal wcount_r2: std_logic;
+ signal wcount_r3: std_logic;
+ signal rcount_0: std_logic;
+ signal rcount_1: std_logic;
+ signal co0_3: std_logic;
+ signal wcount_r4: std_logic;
+ signal wcount_r5: std_logic;
+ signal rcount_2: std_logic;
+ signal rcount_3: std_logic;
+ signal co1_3: std_logic;
+ signal wcount_r6: std_logic;
+ signal wcount_r7: std_logic;
+ signal rcount_4: std_logic;
+ signal rcount_5: std_logic;
+ signal co2_3: std_logic;
+ signal w_g2b_xor_cluster_0: std_logic;
+ signal wcount_r9: std_logic;
+ signal rcount_6: std_logic;
+ signal rcount_7: std_logic;
+ signal co3_3: std_logic;
+ signal wcount_r10: std_logic;
+ signal empty_cmp_clr: std_logic;
+ signal rcount_8: std_logic;
+ signal empty_cmp_set: std_logic;
+ signal empty_d: std_logic;
+ signal empty_d_c: std_logic;
+ signal wren_i: std_logic;
+ signal cmp_ci_1: std_logic;
+ signal wcount_0: std_logic;
+ signal wcount_1: std_logic;
+ signal co0_4: std_logic;
+ signal rcount_w0: std_logic;
+ signal rcount_w1: std_logic;
+ signal wcount_2: std_logic;
+ signal wcount_3: std_logic;
+ signal co1_4: std_logic;
+ signal rcount_w2: std_logic;
+ signal rcount_w3: std_logic;
+ signal wcount_4: std_logic;
+ signal wcount_5: std_logic;
+ signal co2_4: std_logic;
+ signal rcount_w4: std_logic;
+ signal rcount_w5: std_logic;
+ signal wcount_6: std_logic;
+ signal wcount_7: std_logic;
+ signal co3_4: std_logic;
+ signal r_g2b_xor_cluster_0: std_logic;
+ signal rcount_w7: std_logic;
+ signal wcount_8: std_logic;
+ signal wcount_9: std_logic;
+ signal co4_3: std_logic;
+ signal rcount_w8: std_logic;
+ signal full_cmp_clr: std_logic;
+ signal wcount_10: std_logic;
+ signal full_cmp_set: std_logic;
+ signal full_d: std_logic;
+ signal full_d_c: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component AGEB2
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; GE: out std_logic);
+ end component;
+ component AND2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component CU2
+ port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
+ CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
+ end component;
+ component FADD2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; CI: in std_logic; COUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FSUB2B
+ port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
+ B1: in std_logic; BI: in std_logic; BOUT: out std_logic;
+ S0: out std_logic; S1: out std_logic);
+ end component;
+ component FD1P3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ PD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1P3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; SP: in std_logic; CK: in std_logic;
+ CD: in std_logic; Q: out std_logic);
+ end component;
+ component FD1S3BX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; PD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component FD1S3DX
+ -- synopsys translate_off
+ generic (GSR : in String);
+ -- synopsys translate_on
+ port (D: in std_logic; CK: in std_logic; CD: in std_logic;
+ Q: out std_logic);
+ end component;
+ component INV
+ port (A: in std_logic; Z: out std_logic);
+ end component;
+ component OR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component ROM16X1
+ -- synopsys translate_off
+ generic (initval : in String);
+ -- synopsys translate_on
+ port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
+ AD0: in std_logic; DO0: out std_logic);
+ end component;
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component XOR2
+ port (A: in std_logic; B: in std_logic; Z: out std_logic);
+ end component;
+ component DP16KB
+ -- synopsys translate_off
+ generic (GSR : in String; WRITEMODE_B : in String;
+ CSDECODE_B : in std_logic_vector(2 downto 0);
+ CSDECODE_A : in std_logic_vector(2 downto 0);
+ WRITEMODE_A : in String; RESETMODE : in String;
+ REGMODE_B : in String; REGMODE_A : in String;
+ DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
+ -- synopsys translate_on
+ port (DIA0: in std_logic; DIA1: in std_logic;
+ DIA2: in std_logic; DIA3: in std_logic;
+ DIA4: in std_logic; DIA5: in std_logic;
+ DIA6: in std_logic; DIA7: in std_logic;
+ DIA8: in std_logic; DIA9: in std_logic;
+ DIA10: in std_logic; DIA11: in std_logic;
+ DIA12: in std_logic; DIA13: in std_logic;
+ DIA14: in std_logic; DIA15: in std_logic;
+ DIA16: in std_logic; DIA17: in std_logic;
+ ADA0: in std_logic; ADA1: in std_logic;
+ ADA2: in std_logic; ADA3: in std_logic;
+ ADA4: in std_logic; ADA5: in std_logic;
+ ADA6: in std_logic; ADA7: in std_logic;
+ ADA8: in std_logic; ADA9: in std_logic;
+ ADA10: in std_logic; ADA11: in std_logic;
+ ADA12: in std_logic; ADA13: in std_logic;
+ CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
+ CSA0: in std_logic; CSA1: in std_logic;
+ CSA2: in std_logic; RSTA: in std_logic;
+ DIB0: in std_logic; DIB1: in std_logic;
+ DIB2: in std_logic; DIB3: in std_logic;
+ DIB4: in std_logic; DIB5: in std_logic;
+ DIB6: in std_logic; DIB7: in std_logic;
+ DIB8: in std_logic; DIB9: in std_logic;
+ DIB10: in std_logic; DIB11: in std_logic;
+ DIB12: in std_logic; DIB13: in std_logic;
+ DIB14: in std_logic; DIB15: in std_logic;
+ DIB16: in std_logic; DIB17: in std_logic;
+ ADB0: in std_logic; ADB1: in std_logic;
+ ADB2: in std_logic; ADB3: in std_logic;
+ ADB4: in std_logic; ADB5: in std_logic;
+ ADB6: in std_logic; ADB7: in std_logic;
+ ADB8: in std_logic; ADB9: in std_logic;
+ ADB10: in std_logic; ADB11: in std_logic;
+ ADB12: in std_logic; ADB13: in std_logic;
+ CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
+ CSB0: in std_logic; CSB1: in std_logic;
+ CSB2: in std_logic; RSTB: in std_logic;
+ DOA0: out std_logic; DOA1: out std_logic;
+ DOA2: out std_logic; DOA3: out std_logic;
+ DOA4: out std_logic; DOA5: out std_logic;
+ DOA6: out std_logic; DOA7: out std_logic;
+ DOA8: out std_logic; DOA9: out std_logic;
+ DOA10: out std_logic; DOA11: out std_logic;
+ DOA12: out std_logic; DOA13: out std_logic;
+ DOA14: out std_logic; DOA15: out std_logic;
+ DOA16: out std_logic; DOA17: out std_logic;
+ DOB0: out std_logic; DOB1: out std_logic;
+ DOB2: out std_logic; DOB3: out std_logic;
+ DOB4: out std_logic; DOB5: out std_logic;
+ DOB6: out std_logic; DOB7: out std_logic;
+ DOB8: out std_logic; DOB9: out std_logic;
+ DOB10: out std_logic; DOB11: out std_logic;
+ DOB12: out std_logic; DOB13: out std_logic;
+ DOB14: out std_logic; DOB15: out std_logic;
+ DOB16: out std_logic; DOB17: out std_logic);
+ end component;
+ attribute initval : string;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute CSDECODE_B : string;
+ attribute CSDECODE_A : string;
+ attribute WRITEMODE_B : string;
+ attribute WRITEMODE_A : string;
+ attribute RESETMODE : string;
+ attribute REGMODE_B : string;
+ attribute REGMODE_A : string;
+ attribute DATA_WIDTH_B : string;
+ attribute DATA_WIDTH_A : string;
+ attribute GSR : string;
+ attribute initval of LUT4_27 : label is "0x6996";
+ attribute initval of LUT4_26 : label is "0x6996";
+ attribute initval of LUT4_25 : label is "0x6996";
+ attribute initval of LUT4_24 : label is "0x6996";
+ attribute initval of LUT4_23 : label is "0x6996";
+ attribute initval of LUT4_22 : label is "0x6996";
+ attribute initval of LUT4_21 : label is "0x6996";
+ attribute initval of LUT4_20 : label is "0x6996";
+ attribute initval of LUT4_19 : label is "0x6996";
+ attribute initval of LUT4_18 : label is "0x6996";
+ attribute initval of LUT4_17 : label is "0x6996";
+ attribute initval of LUT4_16 : label is "0x6996";
+ attribute initval of LUT4_15 : label is "0x6996";
+ attribute initval of LUT4_14 : label is "0x6996";
+ attribute initval of LUT4_13 : label is "0x6996";
+ attribute initval of LUT4_12 : label is "0x6996";
+ attribute initval of LUT4_11 : label is "0x6996";
+ attribute initval of LUT4_10 : label is "0x6996";
+ attribute initval of LUT4_9 : label is "0x6996";
+ attribute initval of LUT4_8 : label is "0x6996";
+ attribute initval of LUT4_7 : label is "0x6996";
+ attribute initval of LUT4_6 : label is "0x6996";
+ attribute initval of LUT4_5 : label is "0x6996";
+ attribute initval of LUT4_4 : label is "0x6996";
+ attribute initval of LUT4_3 : label is "0x0410";
+ attribute initval of LUT4_2 : label is "0x1004";
+ attribute initval of LUT4_1 : label is "0x0140";
+ attribute initval of LUT4_0 : label is "0x4001";
+ attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_8bit_to_32bit.lpc";
+ attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
+ attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b001";
+ attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000";
+ attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL";
+ attribute GSR of pdp_ram_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC";
+ attribute REGMODE_B of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute REGMODE_A of pdp_ram_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "36";
+ attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "9";
+ attribute GSR of FF_121 : label is "ENABLED";
+ attribute GSR of FF_120 : label is "ENABLED";
+ attribute GSR of FF_119 : label is "ENABLED";
+ attribute GSR of FF_118 : label is "ENABLED";
+ attribute GSR of FF_117 : label is "ENABLED";
+ attribute GSR of FF_116 : label is "ENABLED";
+ attribute GSR of FF_115 : label is "ENABLED";
+ attribute GSR of FF_114 : label is "ENABLED";
+ attribute GSR of FF_113 : label is "ENABLED";
+ attribute GSR of FF_112 : label is "ENABLED";
+ attribute GSR of FF_111 : label is "ENABLED";
+ attribute GSR of FF_110 : label is "ENABLED";
+ attribute GSR of FF_109 : label is "ENABLED";
+ attribute GSR of FF_108 : label is "ENABLED";
+ attribute GSR of FF_107 : label is "ENABLED";
+ attribute GSR of FF_106 : label is "ENABLED";
+ attribute GSR of FF_105 : label is "ENABLED";
+ attribute GSR of FF_104 : label is "ENABLED";
+ attribute GSR of FF_103 : label is "ENABLED";
+ attribute GSR of FF_102 : label is "ENABLED";
+ attribute GSR of FF_101 : label is "ENABLED";
+ attribute GSR of FF_100 : label is "ENABLED";
+ attribute GSR of FF_99 : label is "ENABLED";
+ attribute GSR of FF_98 : label is "ENABLED";
+ attribute GSR of FF_97 : label is "ENABLED";
+ attribute GSR of FF_96 : label is "ENABLED";
+ attribute GSR of FF_95 : label is "ENABLED";
+ attribute GSR of FF_94 : label is "ENABLED";
+ attribute GSR of FF_93 : label is "ENABLED";
+ attribute GSR of FF_92 : label is "ENABLED";
+ attribute GSR of FF_91 : label is "ENABLED";
+ attribute GSR of FF_90 : label is "ENABLED";
+ attribute GSR of FF_89 : label is "ENABLED";
+ attribute GSR of FF_88 : label is "ENABLED";
+ attribute GSR of FF_87 : label is "ENABLED";
+ attribute GSR of FF_86 : label is "ENABLED";
+ attribute GSR of FF_85 : label is "ENABLED";
+ attribute GSR of FF_84 : label is "ENABLED";
+ attribute GSR of FF_83 : label is "ENABLED";
+ attribute GSR of FF_82 : label is "ENABLED";
+ attribute GSR of FF_81 : label is "ENABLED";
+ attribute GSR of FF_80 : label is "ENABLED";
+ attribute GSR of FF_79 : label is "ENABLED";
+ attribute GSR of FF_78 : label is "ENABLED";
+ attribute GSR of FF_77 : label is "ENABLED";
+ attribute GSR of FF_76 : label is "ENABLED";
+ attribute GSR of FF_75 : label is "ENABLED";
+ attribute GSR of FF_74 : label is "ENABLED";
+ attribute GSR of FF_73 : label is "ENABLED";
+ attribute GSR of FF_72 : label is "ENABLED";
+ attribute GSR of FF_71 : label is "ENABLED";
+ attribute GSR of FF_70 : label is "ENABLED";
+ attribute GSR of FF_69 : label is "ENABLED";
+ attribute GSR of FF_68 : label is "ENABLED";
+ attribute GSR of FF_67 : label is "ENABLED";
+ attribute GSR of FF_66 : label is "ENABLED";
+ attribute GSR of FF_65 : label is "ENABLED";
+ attribute GSR of FF_64 : label is "ENABLED";
+ attribute GSR of FF_63 : label is "ENABLED";
+ attribute GSR of FF_62 : label is "ENABLED";
+ attribute GSR of FF_61 : label is "ENABLED";
+ attribute GSR of FF_60 : label is "ENABLED";
+ attribute GSR of FF_59 : label is "ENABLED";
+ attribute GSR of FF_58 : label is "ENABLED";
+ attribute GSR of FF_57 : label is "ENABLED";
+ attribute GSR of FF_56 : label is "ENABLED";
+ attribute GSR of FF_55 : label is "ENABLED";
+ attribute GSR of FF_54 : label is "ENABLED";
+ attribute GSR of FF_53 : label is "ENABLED";
+ attribute GSR of FF_52 : label is "ENABLED";
+ attribute GSR of FF_51 : label is "ENABLED";
+ attribute GSR of FF_50 : label is "ENABLED";
+ attribute GSR of FF_49 : label is "ENABLED";
+ attribute GSR of FF_48 : label is "ENABLED";
+ attribute GSR of FF_47 : label is "ENABLED";
+ attribute GSR of FF_46 : label is "ENABLED";
+ attribute GSR of FF_45 : label is "ENABLED";
+ attribute GSR of FF_44 : label is "ENABLED";
+ attribute GSR of FF_43 : label is "ENABLED";
+ attribute GSR of FF_42 : label is "ENABLED";
+ attribute GSR of FF_41 : label is "ENABLED";
+ attribute GSR of FF_40 : label is "ENABLED";
+ attribute GSR of FF_39 : label is "ENABLED";
+ attribute GSR of FF_38 : label is "ENABLED";
+ attribute GSR of FF_37 : label is "ENABLED";
+ attribute GSR of FF_36 : label is "ENABLED";
+ attribute GSR of FF_35 : label is "ENABLED";
+ attribute GSR of FF_34 : label is "ENABLED";
+ attribute GSR of FF_33 : label is "ENABLED";
+ attribute GSR of FF_32 : label is "ENABLED";
+ attribute GSR of FF_31 : label is "ENABLED";
+ attribute GSR of FF_30 : label is "ENABLED";
+ attribute GSR of FF_29 : label is "ENABLED";
+ attribute GSR of FF_28 : label is "ENABLED";
+ attribute GSR of FF_27 : label is "ENABLED";
+ attribute GSR of FF_26 : label is "ENABLED";
+ attribute GSR of FF_25 : label is "ENABLED";
+ attribute GSR of FF_24 : label is "ENABLED";
+ attribute GSR of FF_23 : label is "ENABLED";
+ attribute GSR of FF_22 : label is "ENABLED";
+ attribute GSR of FF_21 : label is "ENABLED";
+ attribute GSR of FF_20 : label is "ENABLED";
+ attribute GSR of FF_19 : label is "ENABLED";
+ attribute GSR of FF_18 : label is "ENABLED";
+ attribute GSR of FF_17 : label is "ENABLED";
+ attribute GSR of FF_16 : label is "ENABLED";
+ attribute GSR of FF_15 : label is "ENABLED";
+ attribute GSR of FF_14 : label is "ENABLED";
+ attribute GSR of FF_13 : label is "ENABLED";
+ attribute GSR of FF_12 : label is "ENABLED";
+ attribute GSR of FF_11 : label is "ENABLED";
+ attribute GSR of FF_10 : label is "ENABLED";
+ attribute GSR of FF_9 : label is "ENABLED";
+ attribute GSR of FF_8 : label is "ENABLED";
+ attribute GSR of FF_7 : label is "ENABLED";
+ attribute GSR of FF_6 : label is "ENABLED";
+ attribute GSR of FF_5 : label is "ENABLED";
+ attribute GSR of FF_4 : label is "ENABLED";
+ attribute GSR of FF_3 : label is "ENABLED";
+ attribute GSR of FF_2 : label is "ENABLED";
+ attribute GSR of FF_1 : label is "ENABLED";
+ attribute GSR of FF_0 : label is "ENABLED";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ AND2_t23: AND2
+ port map (A=>WrEn, B=>invout_1, Z=>wren_i);
+
+ INV_1: INV
+ port map (A=>full_i, Z=>invout_1);
+
+ AND2_t22: AND2
+ port map (A=>RdEn, B=>invout_0, Z=>rden_i);
+
+ INV_0: INV
+ port map (A=>empty_i, Z=>invout_0);
+
+ OR2_t21: OR2
+ port map (A=>Reset, B=>RPReset, Z=>rRst);
+
+ XOR2_t20: XOR2
+ port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
+
+ XOR2_t19: XOR2
+ port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
+
+ XOR2_t18: XOR2
+ port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
+
+ XOR2_t17: XOR2
+ port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
+
+ XOR2_t16: XOR2
+ port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
+
+ XOR2_t15: XOR2
+ port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
+
+ XOR2_t14: XOR2
+ port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
+
+ XOR2_t13: XOR2
+ port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
+
+ XOR2_t12: XOR2
+ port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
+
+ XOR2_t11: XOR2
+ port map (A=>wcount_9, B=>wcount_10, Z=>w_gdata_9);
+
+ XOR2_t10: XOR2
+ port map (A=>wcount_10, B=>wcount_11, Z=>w_gdata_10);
+
+ XOR2_t9: XOR2
+ port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
+
+ XOR2_t8: XOR2
+ port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
+
+ XOR2_t7: XOR2
+ port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
+
+ XOR2_t6: XOR2
+ port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
+
+ XOR2_t5: XOR2
+ port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
+
+ XOR2_t4: XOR2
+ port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
+
+ XOR2_t3: XOR2
+ port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
+
+ XOR2_t2: XOR2
+ port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
+
+ XOR2_t1: XOR2
+ port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
+
+ LUT4_27: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29,
+ AD1=>w_gcount_r210, AD0=>w_gcount_r211,
+ DO0=>w_g2b_xor_cluster_0);
+
+ LUT4_26: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
+ AD1=>w_gcount_r26, AD0=>w_gcount_r27,
+ DO0=>w_g2b_xor_cluster_1);
+
+ LUT4_25: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
+ AD1=>w_gcount_r22, AD0=>w_gcount_r23,
+ DO0=>w_g2b_xor_cluster_2);
+
+ LUT4_24: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r210, AD2=>w_gcount_r211, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>wcount_r10);
+
+ LUT4_23: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r29, AD2=>w_gcount_r210,
+ AD1=>w_gcount_r211, AD0=>scuba_vlo, DO0=>wcount_r9);
+
+ LUT4_22: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
+ AD1=>w_gcount_r29, AD0=>wcount_r10, DO0=>wcount_r7);
+
+ LUT4_21: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
+ AD1=>w_gcount_r28, AD0=>wcount_r9, DO0=>wcount_r6);
+
+ LUT4_20: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
+ AD1=>w_gcount_r27, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r5);
+
+ LUT4_19: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r4);
+
+ LUT4_18: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r23, AD0=>scuba_vlo, DO0=>wcount_r3);
+
+ LUT4_17: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_gcount_r22, AD0=>w_gcount_r23, DO0=>wcount_r2);
+
+ LUT4_16: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22,
+ AD1=>w_gcount_r23, AD0=>scuba_vlo,
+ DO0=>w_g2b_xor_cluster_2_1);
+
+ LUT4_15: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2_1, AD0=>scuba_vlo, DO0=>wcount_r1);
+
+ LUT4_14: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
+ AD1=>w_g2b_xor_cluster_2, AD0=>scuba_vlo, DO0=>wcount_r0);
+
+ LUT4_13: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
+ AD1=>r_gcount_w28, AD0=>r_gcount_w29,
+ DO0=>r_g2b_xor_cluster_0);
+
+ LUT4_12: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
+ AD1=>r_gcount_w24, AD0=>r_gcount_w25,
+ DO0=>r_g2b_xor_cluster_1);
+
+ LUT4_11: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
+ AD0=>scuba_vlo, DO0=>rcount_w8);
+
+ LUT4_10: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
+ AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
+
+ LUT4_9: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
+ AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
+
+ LUT4_8: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
+ AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
+
+ LUT4_7: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
+ AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
+
+ LUT4_6: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
+
+ LUT4_5: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
+
+ LUT4_4: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x6996")
+ -- synopsys translate_on
+ port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
+ AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
+
+ XOR2_t0: XOR2
+ port map (A=>w_gcount_r211, B=>rptr_9, Z=>rfill_sub_msb);
+
+ LUT4_3: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0410")
+ -- synopsys translate_on
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r211,
+ AD0=>scuba_vlo, DO0=>empty_cmp_set);
+
+ LUT4_2: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x1004")
+ -- synopsys translate_on
+ port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r211,
+ AD0=>scuba_vlo, DO0=>empty_cmp_clr);
+
+ LUT4_1: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x0140")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_set);
+
+ LUT4_0: ROM16X1
+ -- synopsys translate_off
+ generic map (initval=> "0x4001")
+ -- synopsys translate_on
+ port map (AD3=>wptr_11, AD2=>wcount_11, AD1=>r_gcount_w29,
+ AD0=>scuba_vlo, DO0=>full_cmp_clr);
+
+ pdp_ram_0_0_0: DP16KB
+ -- synopsys translate_off
+ generic map (CSDECODE_B=> "001", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL",
+ WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC",
+ REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 36,
+ DATA_WIDTH_A=> 9)
+ -- synopsys translate_on
+ port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2),
+ DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6),
+ DIA7=>Data(7), DIA8=>scuba_vlo, DIA9=>scuba_vlo,
+ DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo,
+ DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo,
+ DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo,
+ ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1,
+ ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5,
+ ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9,
+ ADA13=>wptr_10, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi,
+ CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
+ RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
+ DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
+ DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
+ DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
+ DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
+ DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
+ DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
+ ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>scuba_vlo,
+ ADB5=>rptr_0, ADB6=>rptr_1, ADB7=>rptr_2, ADB8=>rptr_3,
+ ADB9=>rptr_4, ADB10=>rptr_5, ADB11=>rptr_6, ADB12=>rptr_7,
+ ADB13=>rptr_8, CEB=>scuba_vhi, CLKB=>RdClock, WEB=>scuba_vlo,
+ CSB0=>rden_i, CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset,
+ DOA0=>Q(0), DOA1=>Q(1), DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4),
+ DOA5=>Q(5), DOA6=>Q(6), DOA7=>Q(7), DOA8=>open, DOA9=>Q(8),
+ DOA10=>Q(9), DOA11=>Q(10), DOA12=>Q(11), DOA13=>Q(12),
+ DOA14=>Q(13), DOA15=>Q(14), DOA16=>Q(15), DOA17=>open,
+ DOB0=>Q(16), DOB1=>Q(17), DOB2=>Q(18), DOB3=>Q(19),
+ DOB4=>Q(20), DOB5=>Q(21), DOB6=>Q(22), DOB7=>Q(23),
+ DOB8=>open, DOB9=>Q(24), DOB10=>Q(25), DOB11=>Q(26),
+ DOB12=>Q(27), DOB13=>Q(28), DOB14=>Q(29), DOB15=>Q(30),
+ DOB16=>Q(31), DOB17=>open);
+
+ FF_121: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
+ Q=>wcount_0);
+
+ FF_120: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_1);
+
+ FF_119: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_2);
+
+ FF_118: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_3);
+
+ FF_117: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_4);
+
+ FF_116: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_5);
+
+ FF_115: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_6);
+
+ FF_114: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_7);
+
+ FF_113: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_8);
+
+ FF_112: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_9);
+
+ FF_111: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_10);
+
+ FF_110: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>iwcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wcount_11);
+
+ FF_109: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_0);
+
+ FF_108: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_1);
+
+ FF_107: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_2);
+
+ FF_106: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_3);
+
+ FF_105: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_4);
+
+ FF_104: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_5);
+
+ FF_103: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_6);
+
+ FF_102: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_7);
+
+ FF_101: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_8);
+
+ FF_100: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_9);
+
+ FF_99: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gdata_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_10);
+
+ FF_98: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>w_gcount_11);
+
+ FF_97: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_0);
+
+ FF_96: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_1);
+
+ FF_95: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_2);
+
+ FF_94: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_3);
+
+ FF_93: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_4);
+
+ FF_92: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_5);
+
+ FF_91: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_6);
+
+ FF_90: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_7);
+
+ FF_89: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_8);
+
+ FF_88: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_9);
+
+ FF_87: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_10, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_10);
+
+ FF_86: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>wcount_11, SP=>wren_i, CK=>WrClock, CD=>Reset,
+ Q=>wptr_11);
+
+ FF_85: FD1P3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
+ Q=>rcount_0);
+
+ FF_84: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_1);
+
+ FF_83: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_2);
+
+ FF_82: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_3);
+
+ FF_81: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_4);
+
+ FF_80: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_5);
+
+ FF_79: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_6);
+
+ FF_78: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_7);
+
+ FF_77: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_8);
+
+ FF_76: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rcount_9);
+
+ FF_75: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_0);
+
+ FF_74: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_1);
+
+ FF_73: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_2);
+
+ FF_72: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_3);
+
+ FF_71: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_4);
+
+ FF_70: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_5);
+
+ FF_69: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_6);
+
+ FF_68: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_7);
+
+ FF_67: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_8);
+
+ FF_66: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>r_gcount_9);
+
+ FF_65: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_0);
+
+ FF_64: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_1);
+
+ FF_63: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_2);
+
+ FF_62: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_3);
+
+ FF_61: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_4);
+
+ FF_60: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_5);
+
+ FF_59: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_6);
+
+ FF_58: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_7);
+
+ FF_57: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_8);
+
+ FF_56: FD1P3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
+ Q=>rptr_9);
+
+ FF_55: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
+
+ FF_54: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
+
+ FF_53: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
+
+ FF_52: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
+
+ FF_51: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
+
+ FF_50: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
+
+ FF_49: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
+
+ FF_48: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
+
+ FF_47: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
+
+ FF_46: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
+
+ FF_45: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r10);
+
+ FF_44: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r11);
+
+ FF_43: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
+
+ FF_42: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
+
+ FF_41: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
+
+ FF_40: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
+
+ FF_39: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
+
+ FF_38: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
+
+ FF_37: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
+
+ FF_36: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
+
+ FF_35: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
+
+ FF_34: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
+
+ FF_33: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r20);
+
+ FF_32: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r21);
+
+ FF_31: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r22);
+
+ FF_30: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r23);
+
+ FF_29: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r24);
+
+ FF_28: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r25);
+
+ FF_27: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r26);
+
+ FF_26: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r27);
+
+ FF_25: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r28);
+
+ FF_24: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r29);
+
+ FF_23: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r10, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r210);
+
+ FF_22: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>w_gcount_r11, CK=>RdClock, CD=>Reset,
+ Q=>w_gcount_r211);
+
+ FF_21: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
+
+ FF_20: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
+
+ FF_19: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
+
+ FF_18: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
+
+ FF_17: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
+
+ FF_16: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
+
+ FF_15: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
+
+ FF_14: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
+
+ FF_13: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
+
+ FF_12: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
+
+ FF_11: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_0, CK=>RdClock, CD=>rRst, Q=>RCNT(0));
+
+ FF_10: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_1, CK=>RdClock, CD=>rRst, Q=>RCNT(1));
+
+ FF_9: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_2, CK=>RdClock, CD=>rRst, Q=>RCNT(2));
+
+ FF_8: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_3, CK=>RdClock, CD=>rRst, Q=>RCNT(3));
+
+ FF_7: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_4, CK=>RdClock, CD=>rRst, Q=>RCNT(4));
+
+ FF_6: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_5, CK=>RdClock, CD=>rRst, Q=>RCNT(5));
+
+ FF_5: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_6, CK=>RdClock, CD=>rRst, Q=>RCNT(6));
+
+ FF_4: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_7, CK=>RdClock, CD=>rRst, Q=>RCNT(7));
+
+ FF_3: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_8, CK=>RdClock, CD=>rRst, Q=>RCNT(8));
+
+ FF_2: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>rfill_sub_9, CK=>RdClock, CD=>rRst, Q=>RCNT(9));
+
+ FF_1: FD1S3BX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
+
+ FF_0: FD1S3DX
+ -- synopsys translate_off
+ generic map (GSR=> "ENABLED")
+ -- synopsys translate_on
+ port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
+
+ w_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
+ S1=>open);
+
+ w_gctr_0: CU2
+ port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
+ NC0=>iwcount_0, NC1=>iwcount_1);
+
+ w_gctr_1: CU2
+ port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
+ NC0=>iwcount_2, NC1=>iwcount_3);
+
+ w_gctr_2: CU2
+ port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
+ NC0=>iwcount_4, NC1=>iwcount_5);
+
+ w_gctr_3: CU2
+ port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
+ NC0=>iwcount_6, NC1=>iwcount_7);
+
+ w_gctr_4: CU2
+ port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
+ NC0=>iwcount_8, NC1=>iwcount_9);
+
+ w_gctr_5: CU2
+ port map (CI=>co4, PC0=>wcount_10, PC1=>wcount_11, CO=>co5,
+ NC0=>iwcount_10, NC1=>iwcount_11);
+
+ r_gctr_cia: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
+ B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
+ S1=>open);
+
+ r_gctr_0: CU2
+ port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
+ NC0=>ircount_0, NC1=>ircount_1);
+
+ r_gctr_1: CU2
+ port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
+ NC0=>ircount_2, NC1=>ircount_3);
+
+ r_gctr_2: CU2
+ port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
+ NC0=>ircount_4, NC1=>ircount_5);
+
+ r_gctr_3: CU2
+ port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
+ NC0=>ircount_6, NC1=>ircount_7);
+
+ r_gctr_4: CU2
+ port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
+ NC0=>ircount_8, NC1=>ircount_9);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ rfill_0: FSUB2B
+ port map (A0=>scuba_vhi, A1=>wcount_r2, B0=>scuba_vlo,
+ B1=>rptr_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open,
+ S1=>rfill_sub_0);
+
+ rfill_1: FSUB2B
+ port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rptr_1, B1=>rptr_2,
+ BI=>co0_2, BOUT=>co1_2, S0=>rfill_sub_1, S1=>rfill_sub_2);
+
+ rfill_2: FSUB2B
+ port map (A0=>wcount_r5, A1=>wcount_r6, B0=>rptr_3, B1=>rptr_4,
+ BI=>co1_2, BOUT=>co2_2, S0=>rfill_sub_3, S1=>rfill_sub_4);
+
+ rfill_3: FSUB2B
+ port map (A0=>wcount_r7, A1=>w_g2b_xor_cluster_0, B0=>rptr_5,
+ B1=>rptr_6, BI=>co2_2, BOUT=>co3_2, S0=>rfill_sub_5,
+ S1=>rfill_sub_6);
+
+ rfill_4: FSUB2B
+ port map (A0=>wcount_r9, A1=>wcount_r10, B0=>rptr_7, B1=>rptr_8,
+ BI=>co3_2, BOUT=>co4_2, S0=>rfill_sub_7, S1=>rfill_sub_8);
+
+ rfill_5: FSUB2B
+ port map (A0=>rfill_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, BI=>co4_2, BOUT=>open, S0=>rfill_sub_9,
+ S1=>open);
+
+ empty_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
+ CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
+
+ empty_cmp_0: AGEB2
+ port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2,
+ B1=>wcount_r3, CI=>cmp_ci, GE=>co0_3);
+
+ empty_cmp_1: AGEB2
+ port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4,
+ B1=>wcount_r5, CI=>co0_3, GE=>co1_3);
+
+ empty_cmp_2: AGEB2
+ port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r6,
+ B1=>wcount_r7, CI=>co1_3, GE=>co2_3);
+
+ empty_cmp_3: AGEB2
+ port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
+ B1=>wcount_r9, CI=>co2_3, GE=>co3_3);
+
+ empty_cmp_4: AGEB2
+ port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r10,
+ B1=>empty_cmp_clr, CI=>co3_3, GE=>empty_d_c);
+
+ a0: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
+ S1=>open);
+
+ full_cmp_ci_a: FADD2B
+ port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
+ CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
+
+ full_cmp_0: AGEB2
+ port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4);
+
+ full_cmp_1: AGEB2
+ port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0,
+ B1=>rcount_w1, CI=>co0_4, GE=>co1_4);
+
+ full_cmp_2: AGEB2
+ port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2,
+ B1=>rcount_w3, CI=>co1_4, GE=>co2_4);
+
+ full_cmp_3: AGEB2
+ port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w4,
+ B1=>rcount_w5, CI=>co2_4, GE=>co3_4);
+
+ full_cmp_4: AGEB2
+ port map (A0=>wcount_8, A1=>wcount_9, B0=>r_g2b_xor_cluster_0,
+ B1=>rcount_w7, CI=>co3_4, GE=>co4_3);
+
+ full_cmp_5: AGEB2
+ port map (A0=>wcount_10, A1=>full_cmp_set, B0=>rcount_w8,
+ B1=>full_cmp_clr, CI=>co4_3, GE=>full_d_c);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ a1: FADD2B
+ port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
+ B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
+ S1=>open);
+
+ Empty <= empty_i;
+ Full <= full_i;
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of fifo_8bit_to_32bit is
+ for Structure
+ for all:AGEB2 use entity ecp2m.AGEB2(V); end for;
+ for all:AND2 use entity ecp2m.AND2(V); end for;
+ for all:CU2 use entity ecp2m.CU2(V); end for;
+ for all:FADD2B use entity ecp2m.FADD2B(V); end for;
+ for all:FSUB2B use entity ecp2m.FSUB2B(V); end for;
+ for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for;
+ for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for;
+ for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for;
+ for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for;
+ for all:INV use entity ecp2m.INV(V); end for;
+ for all:OR2 use entity ecp2m.OR2(V); end for;
+ for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for;
+ for all:VHI use entity ecp2m.VHI(V); end for;
+ for all:VLO use entity ecp2m.VLO(V); end for;
+ for all:XOR2 use entity ecp2m.XOR2(V); end for;
+ for all:DP16KB use entity ecp2m.DP16KB(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+library IEEE;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.all;
+use work.version.all;
+use ieee.std_logic_arith.all;
+
+entity multiplicity is
+
+ port (
+ RESET : in std_logic;
+ CLK : in std_logic;
+ SIGNAL_IN : in std_logic_vector(5 downto 0);
+ SIGNAL_OUT : out std_logic_vector(8 downto 0)
+ );
+end multiplicity;
+
+architecture multiplicity of multiplicity is
+ component edge_to_pulse
+ port (
+ clock : in std_logic;
+ en_clk : in std_logic;
+ signal_in : in std_logic;
+ pulse : out std_logic);
+ end component;
+ signal signal_out_i : std_logic_vector(8 downto 0);
+ signal signal_out_buf_sync : std_logic_vector(8 downto 0);
+ signal signal_out_buf : std_logic_vector(8 downto 0);
+ signal sample_mult_signal : std_logic;
+ signal mult_signal_en : std_logic;
+begin
+--there is assumption that the input signals are aligned with proper delay and
+--width settings - in that case signals from the same event should be within 20
+--ns range
+
+ ENABLE_MULT_SIGNAL : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' or SIGNAL_IN = 0 then --when event finished mult. should
+ --go to 0
+ mult_signal_en <= '0';
+ elsif SIGNAL_IN /= 0 then --there is a mult.signal
+ mult_signal_en <= '1';
+ end if;
+ end if;
+ end process ENABLE_MULT_SIGNAL;
+
+ MULT_SAMPLE_PULSE : edge_to_pulse port map (
+ clock => CLK,
+ en_clk => '1',
+ signal_in => mult_signal_en,
+ pulse => sample_mult_signal --20 ns after input has
+ --changed(mult.is settled after 20ns)
+ );
+
+ MAKE_FINAL_MULT : process (CLK, RESET)
+ begin
+ if rising_edge(CLK) then
+ if RESET = '1' then
+ signal_out_i <= (others => '0');
+ elsif sample_mult_signal = '1' then --after 20 ns the mult. signal is sampled
+ signal_out_i <= signal_out_buf_sync;
+ else
+ signal_out_i <= (others => '0');
+ end if;
+ end if;
+ end process MAKE_FINAL_MULT;
+ SIGNAL_OUT <= signal_out_i;
+
+ MULT1: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ case SIGNAL_IN is
+ when "000001" => signal_out_buf_sync(0) <= '1';
+ when "000010" => signal_out_buf_sync(0) <= '1';
+ when "000100" => signal_out_buf_sync(0) <= '1';
+ when "001000" => signal_out_buf_sync(0) <= '1';
+ when "010000" => signal_out_buf_sync(0) <= '1';
+ when "100000" => signal_out_buf_sync(0) <= '1';
+ when others => signal_out_buf_sync(0) <= '0';
+ end case;
+ end if;
+ end process MULT1;
+
+ MULT2: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ case SIGNAL_IN is
+ when "000011" => signal_out_buf_sync(1) <= '1';
+ when "000101" => signal_out_buf_sync(1) <= '1';
+ when "001001" => signal_out_buf_sync(1) <= '1';
+ when "010001" => signal_out_buf_sync(1) <= '1';
+ when "100001" => signal_out_buf_sync(1) <= '1';
+ when "000110" => signal_out_buf_sync(1) <= '1';
+ when "001010" => signal_out_buf_sync(1) <= '1';
+ when "010010" => signal_out_buf_sync(1) <= '1';
+ when "100010" => signal_out_buf_sync(1) <= '1';
+ when "001100" => signal_out_buf_sync(1) <= '1';
+ when "010100" => signal_out_buf_sync(1) <= '1';
+ when "100100" => signal_out_buf_sync(1) <= '1';
+ when "011000" => signal_out_buf_sync(1) <= '1';
+ when "101000" => signal_out_buf_sync(1) <= '1';
+ when "110000" => signal_out_buf_sync(1) <= '1';
+ when others => signal_out_buf_sync(1) <= '0';
+ end case;
+ end if;
+ end process MULT2;
+
+ MULT3: process (CLK)
+ begin
+ if rising_edge(CLK) then
+ case SIGNAL_IN is
+ when "111000" => signal_out_buf_sync(2) <= '1';
+ when "110100" => signal_out_buf_sync(2) <= '1';
+ when "110010" => signal_out_buf_sync(2) <= '1';
+ when "110001" => signal_out_buf_sync(2) <= '1';
+ when "101001" => signal_out_buf_sync(2) <= '1';
+ when "100101" => signal_out_buf_sync(2) <= '1';
+ when "100011" => signal_out_buf_sync(2) <= '1';
+ when "011100" => signal_out_buf_sync(2) <= '1';
+ when "011010" => signal_out_buf_sync(2) <= '1';
+ when "011001" => signal_out_buf_sync(2) <= '1';
+ when "010101" => signal_out_buf_sync(2) <= '1';
+ when "010011" => signal_out_buf_sync(2) <= '1';
+ when "001110" => signal_out_buf_sync(2) <= '1';
+ when "001101" => signal_out_buf_sync(2) <= '1';
+ when "001011" => signal_out_buf_sync(2) <= '1';
+ when "000111" => signal_out_buf_sync(2) <= '1';
+ when "101100" => signal_out_buf_sync(2) <= '1';
+ when "101010" => signal_out_buf_sync(2) <= '1';
+ when "100110" => signal_out_buf_sync(2) <= '1';
+ when "010110" => signal_out_buf_sync(2) <= '1';
+ when others => signal_out_buf_sync(2) <= '0';
+ end case;
+ end if;
+ end process MULT3;
+
+ MULT4: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ case SIGNAL_IN is
+ when "111100" => signal_out_buf_sync(3) <= '1';
+ when "111010" => signal_out_buf_sync(3) <= '1';
+ when "110110" => signal_out_buf_sync(3) <= '1';
+ when "101110" => signal_out_buf_sync(3) <= '1';
+ when "011110" => signal_out_buf_sync(3) <= '1';
+ when "111001" => signal_out_buf_sync(3) <= '1';
+ when "110101" => signal_out_buf_sync(3) <= '1';
+ when "101101" => signal_out_buf_sync(3) <= '1';
+ when "011101" => signal_out_buf_sync(3) <= '1';
+ when "110011" => signal_out_buf_sync(3) <= '1';
+ when "101011" => signal_out_buf_sync(3) <= '1';
+ when "011011" => signal_out_buf_sync(3) <= '1';
+ when "100111" => signal_out_buf_sync(3) <= '1';
+ when "010111" => signal_out_buf_sync(3) <= '1';
+ when "001111" => signal_out_buf_sync(3) <= '1';
+ when others => signal_out_buf_sync(3) <= '0';
+ end case;
+ end if;
+ end process MULT4;
+
+ MULT5: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ case SIGNAL_IN is
+ when "011111" => signal_out_buf_sync(4) <= '1';
+ when "101111" => signal_out_buf_sync(4) <= '1';
+ when "110111" => signal_out_buf_sync(4) <= '1';
+ when "111011" => signal_out_buf_sync(4) <= '1';
+ when "111101" => signal_out_buf_sync(4) <= '1';
+ when "111110" => signal_out_buf_sync(4) <= '1';
+ when others => signal_out_buf_sync(4) <= '0';
+ end case;
+ end if;
+ end process MULT5;
+
+ MULT6: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ case SIGNAL_IN is
+ when "111111" => signal_out_buf_sync(5) <= '1';
+ when others => signal_out_buf_sync(5) <= '0';
+ end case;
+ end if;
+ end process MULT6;
+
+ MULT2_NO_NEIGHBOUR: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ case SIGNAL_IN is
+ when "101000" => signal_out_buf_sync(6) <= '1';
+ when "100100" => signal_out_buf_sync(6) <= '1';
+ when "100010" => signal_out_buf_sync(6) <= '1';
+ when "010100" => signal_out_buf_sync(6) <= '1';
+ when "010010" => signal_out_buf_sync(6) <= '1';
+ when "010001" => signal_out_buf_sync(6) <= '1';
+ when "001010" => signal_out_buf_sync(6) <= '1';
+ when "001001" => signal_out_buf_sync(6) <= '1';
+ when "000101" => signal_out_buf_sync(6) <= '1';
+ when others => signal_out_buf_sync(6) <= '0';
+ end case;
+ end if;
+ end process MULT2_NO_NEIGHBOUR;
+
+ MULT3_NO_NEIGHBOUR: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ case SIGNAL_IN is
+ when "101010" => signal_out_buf_sync(7) <= '1';
+ when "010101" => signal_out_buf_sync(7) <= '1';
+ when others => signal_out_buf_sync(7) <= '0';
+ end case;
+ end if;
+ end process MULT3_NO_NEIGHBOUR;
+
+ MULT2_OPPOSITE: process(CLK)
+ begin
+ if rising_edge(CLK) then
+ case SIGNAL_IN is
+ when "100100" => signal_out_buf_sync(8) <= '1';
+ when "010010" => signal_out_buf_sync(8) <= '1';
+ when "001001" => signal_out_buf_sync(8) <= '1';
+ when others => signal_out_buf_sync(8) <= '0';
+ end case;
+ end if;
+ end process MULT2_OPPOSITE;
+
+
+
+end multiplicity;
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA40EP1
+PartName=LFSCM3GA40EP1-7FF1020C
+SpeedGrade=-7
+Package=FFBGA1020
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.1
+ModuleName=pll_in200_out40
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=11/04/2010
+Time=12:27:41
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+Clki_freq=100
+U_OFrq=40
+OP_Tol=0.0
+ClkOP_Freq= 40.000000
+U_SFrq=100
+OS_Tol=0.0
+ClkOS_Freq= 100.000000
+Phase=0
+FineDelay=0
+FeedbackClk=Internal
+Frequency=100
+enSpectrum=0
+smiport=0
+enRSTN=0
+Clki_boosting=DEL0
+Clkfb_boosting=DEL0
+Clki_fine=0
+Clkfb_fine=0
+enSpread=0
+modulation=1
+Desired=30
+Actual=30
+lock=Frequency
+enGSR=0
+VcoRate= 600.000000
+Bandwidth= 5.262395
+enHighBand=0
+enBypassP=0
+enBypassS=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.1
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n pll_in200_out40 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 100 -mfreq 40 -nfreq 100 -clkos_fdel 0 -fb 0 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e
+
+-- Thu Nov 4 12:27:42 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity pll_in200_out40 is
+ generic (
+ SMI_OFFSET : in String := "0x410"
+ );
+ port (
+ clk: in std_logic;
+ clkop: out std_logic;
+ clkos: out std_logic;
+ lock: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in200_out40 : entity is true;
+end pll_in200_out40;
+
+architecture Structure of pll_in200_out40 is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal clkos_t: std_logic;
+ signal fb: std_logic;
+ signal clkop_t: std_logic;
+ signal clk_t: std_logic;
+
+ attribute module_type : string;
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EHXPLLA
+ generic (SMI_OFFSET : in String
+ -- synopsys translate_off
+ ; GSR : in String; CLKOS_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; CLKOS_FDEL : in Integer;
+ CLKFB_FDEL : in Integer; CLKI_FDEL : in Integer;
+ CLKOS_MODE : in String; CLKOP_MODE : in String;
+ PHASEADJ : in Integer; CLKOS_VCODEL : in Integer
+ -- synopsys translate_on
+ );
+ port (SMIADDR9: in std_logic; SMIADDR8: in std_logic;
+ SMIADDR7: in std_logic; SMIADDR6: in std_logic;
+ SMIADDR5: in std_logic; SMIADDR4: in std_logic;
+ SMIADDR3: in std_logic; SMIADDR2: in std_logic;
+ SMIADDR1: in std_logic; SMIADDR0: in std_logic;
+ SMIRD: in std_logic; SMIWR: in std_logic;
+ SMICLK: in std_logic; SMIWDATA: in std_logic;
+ SMIRSTN: in std_logic; CLKI: in std_logic;
+ CLKFB: in std_logic; RSTN: in std_logic;
+ CLKOS: out std_logic; CLKOP: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic;
+ SMIRDATA: out std_logic);
+ end component;
+ attribute module_type of EHXPLLA : component is "EHXPLLA";
+ attribute ip_type : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute VCO_LOWERFREQ : string;
+ attribute GMCFREQSEL : string;
+ attribute GSR : string;
+ attribute SPREAD_DIV2 : string;
+ attribute SPREAD_DIV1 : string;
+ attribute SPREAD_DRIFT : string;
+ attribute SPREAD : string;
+ attribute CLKFB_FDEL : string;
+ attribute CLKI_FDEL : string;
+ attribute CLKFB_PDEL : string;
+ attribute CLKI_PDEL : string;
+ attribute LF_RESISTOR : string;
+ attribute LF_IX5UA : string;
+ attribute CLKOS_FDEL : string;
+ attribute CLKOS_VCODEL : string;
+ attribute PHASEADJ : string;
+ attribute CLKOS_MODE : string;
+ attribute CLKOP_MODE : string;
+ attribute CLKOS_DIV : string;
+ attribute CLKOP_DIV : string;
+ attribute CLKFB_DIV : string;
+ attribute CLKI_DIV : string;
+ attribute ip_type of pll_in200_out40_0_0 : label is "EHXPLLA";
+ attribute FREQUENCY_PIN_CLKOS of pll_in200_out40_0_0 : label is "100.000000";
+ attribute FREQUENCY_PIN_CLKOP of pll_in200_out40_0_0 : label is "40.000000";
+ attribute FREQUENCY_PIN_CLKI of pll_in200_out40_0_0 : label is "100.000000";
+ attribute VCO_LOWERFREQ of pll_in200_out40_0_0 : label is "DISABLED";
+ attribute GMCFREQSEL of pll_in200_out40_0_0 : label is "HIGH";
+ attribute GSR of pll_in200_out40_0_0 : label is "ENABLED";
+ attribute SPREAD_DIV2 of pll_in200_out40_0_0 : label is "2";
+ attribute SPREAD_DIV1 of pll_in200_out40_0_0 : label is "2";
+ attribute SPREAD_DRIFT of pll_in200_out40_0_0 : label is "1";
+ attribute SPREAD of pll_in200_out40_0_0 : label is "DISABLED";
+ attribute CLKFB_FDEL of pll_in200_out40_0_0 : label is "0";
+ attribute CLKI_FDEL of pll_in200_out40_0_0 : label is "0";
+ attribute CLKFB_PDEL of pll_in200_out40_0_0 : label is "DEL0";
+ attribute CLKI_PDEL of pll_in200_out40_0_0 : label is "DEL0";
+ attribute LF_RESISTOR of pll_in200_out40_0_0 : label is "0b111010";
+ attribute LF_IX5UA of pll_in200_out40_0_0 : label is "31";
+ attribute CLKOS_FDEL of pll_in200_out40_0_0 : label is "0";
+ attribute CLKOS_VCODEL of pll_in200_out40_0_0 : label is "0";
+ attribute PHASEADJ of pll_in200_out40_0_0 : label is "0";
+ attribute CLKOS_MODE of pll_in200_out40_0_0 : label is "DIV";
+ attribute CLKOP_MODE of pll_in200_out40_0_0 : label is "DIV";
+ attribute CLKOS_DIV of pll_in200_out40_0_0 : label is "6";
+ attribute CLKOP_DIV of pll_in200_out40_0_0 : label is "15";
+ attribute CLKFB_DIV of pll_in200_out40_0_0 : label is "6";
+ attribute CLKI_DIV of pll_in200_out40_0_0 : label is "1";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ pll_in200_out40_0_0: EHXPLLA
+ generic map (SMI_OFFSET=> SMI_OFFSET
+ -- synopsys translate_off
+ , GSR=> "ENABLED", CLKFB_FDEL=> 0, CLKI_FDEL=> 0,
+ CLKOS_FDEL=> 0, CLKOS_VCODEL=> 0, PHASEADJ=> 0, CLKOS_MODE=> "DIV",
+ CLKOP_MODE=> "DIV", CLKOS_DIV=> 6, CLKOP_DIV=> 15, CLKFB_DIV=> 6,
+ CLKI_DIV=> 1
+ -- synopsys translate_on
+ )
+ port map (SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo,
+ SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo,
+ SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo,
+ SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo,
+ SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo,
+ SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo,
+ SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>fb, RSTN=>scuba_vhi,
+ CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock, CLKINTFB=>fb,
+ SMIRDATA=>open);
+
+ clkos <= clkos_t;
+ clkop <= clkop_t;
+ clk_t <= clk;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of pll_in200_out40 is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:EHXPLLA use entity SCM.EHXPLLA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module Version: 5.2
+--/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n pll_in200_out400 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 200 -mfreq 400 -nfreq 100 -clkos_fdel 0 -fb 1 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e
+
+-- Wed Nov 9 10:40:07 2011
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity pll_in200_out400 is
+ generic (
+ SMI_OFFSET : in String := "0x410"
+ );
+ port (
+ clk: in std_logic;
+ clkop: out std_logic;
+ clkos: out std_logic;
+ lock: out std_logic);
+ attribute dont_touch : boolean;
+ attribute dont_touch of pll_in200_out400 : entity is true;
+end pll_in200_out400;
+
+architecture Structure of pll_in200_out400 is
+
+ -- internal signal declarations
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal clkos_t: std_logic;
+ signal clkop_t: std_logic;
+ signal clk_t: std_logic;
+
+ attribute module_type : string;
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EHXPLLA
+ generic (SMI_OFFSET : in String
+ -- synopsys translate_off
+ ; GSR : in String; CLKOS_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; CLKOS_FDEL : in Integer;
+ CLKFB_FDEL : in Integer; CLKI_FDEL : in Integer;
+ CLKOS_MODE : in String; CLKOP_MODE : in String;
+ PHASEADJ : in Integer; CLKOS_VCODEL : in Integer
+ -- synopsys translate_on
+ );
+ port (SMIADDR9: in std_logic; SMIADDR8: in std_logic;
+ SMIADDR7: in std_logic; SMIADDR6: in std_logic;
+ SMIADDR5: in std_logic; SMIADDR4: in std_logic;
+ SMIADDR3: in std_logic; SMIADDR2: in std_logic;
+ SMIADDR1: in std_logic; SMIADDR0: in std_logic;
+ SMIRD: in std_logic; SMIWR: in std_logic;
+ SMICLK: in std_logic; SMIWDATA: in std_logic;
+ SMIRSTN: in std_logic; CLKI: in std_logic;
+ CLKFB: in std_logic; RSTN: in std_logic;
+ CLKOS: out std_logic; CLKOP: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic;
+ SMIRDATA: out std_logic);
+ end component;
+ attribute module_type of EHXPLLA : component is "EHXPLLA";
+ attribute ip_type : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute VCO_LOWERFREQ : string;
+ attribute GMCFREQSEL : string;
+ attribute GSR : string;
+ attribute SPREAD_DIV2 : string;
+ attribute SPREAD_DIV1 : string;
+ attribute SPREAD_DRIFT : string;
+ attribute SPREAD : string;
+ attribute CLKFB_FDEL : string;
+ attribute CLKI_FDEL : string;
+ attribute CLKFB_PDEL : string;
+ attribute CLKI_PDEL : string;
+ attribute LF_RESISTOR : string;
+ attribute LF_IX5UA : string;
+ attribute CLKOS_FDEL : string;
+ attribute CLKOS_VCODEL : string;
+ attribute PHASEADJ : string;
+ attribute CLKOS_MODE : string;
+ attribute CLKOP_MODE : string;
+ attribute CLKOS_DIV : string;
+ attribute CLKOP_DIV : string;
+ attribute CLKFB_DIV : string;
+ attribute CLKI_DIV : string;
+ attribute ip_type of pll_in200_out400_0_0 : label is "EHXPLLA";
+ attribute FREQUENCY_PIN_CLKOS of pll_in200_out400_0_0 : label is "100.000000";
+ attribute FREQUENCY_PIN_CLKOP of pll_in200_out400_0_0 : label is "400.000000";
+ attribute FREQUENCY_PIN_CLKI of pll_in200_out400_0_0 : label is "200.000000";
+ attribute VCO_LOWERFREQ of pll_in200_out400_0_0 : label is "DISABLED";
+ attribute GMCFREQSEL of pll_in200_out400_0_0 : label is "HIGH";
+ attribute GSR of pll_in200_out400_0_0 : label is "ENABLED";
+ attribute SPREAD_DIV2 of pll_in200_out400_0_0 : label is "2";
+ attribute SPREAD_DIV1 of pll_in200_out400_0_0 : label is "2";
+ attribute SPREAD_DRIFT of pll_in200_out400_0_0 : label is "1";
+ attribute SPREAD of pll_in200_out400_0_0 : label is "DISABLED";
+ attribute CLKFB_FDEL of pll_in200_out400_0_0 : label is "0";
+ attribute CLKI_FDEL of pll_in200_out400_0_0 : label is "0";
+ attribute CLKFB_PDEL of pll_in200_out400_0_0 : label is "DEL0";
+ attribute CLKI_PDEL of pll_in200_out400_0_0 : label is "DEL0";
+ attribute LF_RESISTOR of pll_in200_out400_0_0 : label is "0b111101";
+ attribute LF_IX5UA of pll_in200_out400_0_0 : label is "31";
+ attribute CLKOS_FDEL of pll_in200_out400_0_0 : label is "0";
+ attribute CLKOS_VCODEL of pll_in200_out400_0_0 : label is "0";
+ attribute PHASEADJ of pll_in200_out400_0_0 : label is "0";
+ attribute CLKOS_MODE of pll_in200_out400_0_0 : label is "DIV";
+ attribute CLKOP_MODE of pll_in200_out400_0_0 : label is "DIV";
+ attribute CLKOS_DIV of pll_in200_out400_0_0 : label is "4";
+ attribute CLKOP_DIV of pll_in200_out400_0_0 : label is "1";
+ attribute CLKFB_DIV of pll_in200_out400_0_0 : label is "2";
+ attribute CLKI_DIV of pll_in200_out400_0_0 : label is "1";
+ attribute syn_keep : boolean;
+ attribute syn_noprune : boolean;
+ attribute syn_noprune of Structure : architecture is true;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ pll_in200_out400_0_0: EHXPLLA
+ generic map (SMI_OFFSET=> SMI_OFFSET
+ -- synopsys translate_off
+ , GSR=> "ENABLED", CLKFB_FDEL=> 0, CLKI_FDEL=> 0,
+ CLKOS_FDEL=> 0, CLKOS_VCODEL=> 0, PHASEADJ=> 0, CLKOS_MODE=> "DIV",
+ CLKOP_MODE=> "DIV", CLKOS_DIV=> 4, CLKOP_DIV=> 1, CLKFB_DIV=> 2,
+ CLKI_DIV=> 1
+ -- synopsys translate_on
+ )
+ port map (SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo,
+ SMIADDR7=>scuba_vlo, SMIADDR6=>scuba_vlo,
+ SMIADDR5=>scuba_vlo, SMIADDR4=>scuba_vlo,
+ SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo,
+ SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo,
+ SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo,
+ SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>clkop_t,
+ RSTN=>scuba_vhi, CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock,
+ CLKINTFB=>open, SMIRDATA=>open);
+
+ clkos <= clkos_t;
+ clkop <= clkop_t;
+ clk_t <= clk;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of pll_in200_out400 is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:EHXPLLA use entity SCM.EHXPLLA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA15EP1
+PartName=LFSCM3GA15EP1-5F256C
+SpeedGrade=-5
+Package=FPBGA256
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=RAM_DP
+CoreRevision=6.1
+ModuleName=ram_register
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=07/15/2010
+Time=18:46:31
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+RAddress=2
+RData=32
+WAddress=2
+WData=32
+enByte=0
+ByteSize=9
+adPipeline=0
+inPipeline=0
+outPipeline=1
+MOR=0
+InData=Registered
+AdControl=Registered
+MemFile=
+MemFormat=orca
+Reset=Sync
+GSR=Enabled
+Pad=0
+EnECC=0
+Optimization=Speed
+Pipeline=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 6.1
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n ram_register -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type bram -wp 10 -rp 0011 -num_rows 2 -data_width 32 -rdata_width 32 -read_reg1 outreg -sync_reset -memfile /home/marek/ctsaddon/regmem.mem -memformat hex -cascade -1 -e
+
+-- Fri Aug 13 16:27:53 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity ram_register is
+ port (
+ WrAddress: in std_logic_vector(0 downto 0);
+ RdAddress: in std_logic_vector(0 downto 0);
+ Data: in std_logic_vector(31 downto 0);
+ WE: in std_logic;
+ RdClock: in std_logic;
+ RdClockEn: in std_logic;
+ Reset: in std_logic;
+ WrClock: in std_logic;
+ WrClockEn: in std_logic;
+ Q: out std_logic_vector(31 downto 0));
+end ram_register;
+
+architecture Structure of ram_register is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component PDP16KA
+ -- synopsys translate_off
+ generic (INITVAL_00 : in String; INITVAL_01 : in String;
+ INITVAL_02 : in String; INITVAL_03 : in String;
+ INITVAL_04 : in String; INITVAL_05 : in String;
+ INITVAL_06 : in String; INITVAL_07 : in String;
+ INITVAL_08 : in String; INITVAL_09 : in String;
+ INITVAL_0A : in String; INITVAL_0B : in String;
+ INITVAL_0C : in String; INITVAL_0D : in String;
+ INITVAL_0E : in String; INITVAL_0F : in String;
+ INITVAL_10 : in String; INITVAL_11 : in String;
+ INITVAL_12 : in String; INITVAL_13 : in String;
+ INITVAL_14 : in String; INITVAL_15 : in String;
+ INITVAL_16 : in String; INITVAL_17 : in String;
+ INITVAL_18 : in String; INITVAL_19 : in String;
+ INITVAL_1A : in String; INITVAL_1B : in String;
+ INITVAL_1C : in String; INITVAL_1D : in String;
+ INITVAL_1E : in String; INITVAL_1F : in String;
+ INITVAL_20 : in String; INITVAL_21 : in String;
+ INITVAL_22 : in String; INITVAL_23 : in String;
+ INITVAL_24 : in String; INITVAL_25 : in String;
+ INITVAL_26 : in String; INITVAL_27 : in String;
+ INITVAL_28 : in String; INITVAL_29 : in String;
+ INITVAL_2A : in String; INITVAL_2B : in String;
+ INITVAL_2C : in String; INITVAL_2D : in String;
+ INITVAL_2E : in String; INITVAL_2F : in String;
+ INITVAL_30 : in String; INITVAL_31 : in String;
+ INITVAL_32 : in String; INITVAL_33 : in String;
+ INITVAL_34 : in String; INITVAL_35 : in String;
+ INITVAL_36 : in String; INITVAL_37 : in String;
+ INITVAL_38 : in String; INITVAL_39 : in String;
+ INITVAL_3A : in String; INITVAL_3B : in String;
+ INITVAL_3C : in String; INITVAL_3D : in String;
+ INITVAL_3E : in String; INITVAL_3F : in String;
+ GSR : in String;
+ CSDECODE_R : in std_logic_vector(2 downto 0);
+ CSDECODE_W : in std_logic_vector(2 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ ADW0: in std_logic; ADW1: in std_logic;
+ ADW2: in std_logic; ADW3: in std_logic;
+ ADW4: in std_logic; ADW5: in std_logic;
+ ADW6: in std_logic; ADW7: in std_logic;
+ ADW8: in std_logic; ADW9: in std_logic;
+ ADW10: in std_logic; ADW11: in std_logic;
+ ADW12: in std_logic; ADW13: in std_logic;
+ CEW: in std_logic; CLKW: in std_logic; WE: in std_logic;
+ CSW0: in std_logic; CSW1: in std_logic;
+ CSW2: in std_logic; ADR0: in std_logic;
+ ADR1: in std_logic; ADR2: in std_logic;
+ ADR3: in std_logic; ADR4: in std_logic;
+ ADR5: in std_logic; ADR6: in std_logic;
+ ADR7: in std_logic; ADR8: in std_logic;
+ ADR9: in std_logic; ADR10: in std_logic;
+ ADR11: in std_logic; ADR12: in std_logic;
+ ADR13: in std_logic; CER: in std_logic;
+ CLKR: in std_logic; CSR0: in std_logic;
+ CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic);
+ end component;
+ attribute MEM_LPC_FILE : string;
+ attribute MEM_INIT_FILE : string;
+ attribute INITVAL_3F : string;
+ attribute INITVAL_3E : string;
+ attribute INITVAL_3D : string;
+ attribute INITVAL_3C : string;
+ attribute INITVAL_3B : string;
+ attribute INITVAL_3A : string;
+ attribute INITVAL_39 : string;
+ attribute INITVAL_38 : string;
+ attribute INITVAL_37 : string;
+ attribute INITVAL_36 : string;
+ attribute INITVAL_35 : string;
+ attribute INITVAL_34 : string;
+ attribute INITVAL_33 : string;
+ attribute INITVAL_32 : string;
+ attribute INITVAL_31 : string;
+ attribute INITVAL_30 : string;
+ attribute INITVAL_2F : string;
+ attribute INITVAL_2E : string;
+ attribute INITVAL_2D : string;
+ attribute INITVAL_2C : string;
+ attribute INITVAL_2B : string;
+ attribute INITVAL_2A : string;
+ attribute INITVAL_29 : string;
+ attribute INITVAL_28 : string;
+ attribute INITVAL_27 : string;
+ attribute INITVAL_26 : string;
+ attribute INITVAL_25 : string;
+ attribute INITVAL_24 : string;
+ attribute INITVAL_23 : string;
+ attribute INITVAL_22 : string;
+ attribute INITVAL_21 : string;
+ attribute INITVAL_20 : string;
+ attribute INITVAL_1F : string;
+ attribute INITVAL_1E : string;
+ attribute INITVAL_1D : string;
+ attribute INITVAL_1C : string;
+ attribute INITVAL_1B : string;
+ attribute INITVAL_1A : string;
+ attribute INITVAL_19 : string;
+ attribute INITVAL_18 : string;
+ attribute INITVAL_17 : string;
+ attribute INITVAL_16 : string;
+ attribute INITVAL_15 : string;
+ attribute INITVAL_14 : string;
+ attribute INITVAL_13 : string;
+ attribute INITVAL_12 : string;
+ attribute INITVAL_11 : string;
+ attribute INITVAL_10 : string;
+ attribute INITVAL_0F : string;
+ attribute INITVAL_0E : string;
+ attribute INITVAL_0D : string;
+ attribute INITVAL_0C : string;
+ attribute INITVAL_0B : string;
+ attribute INITVAL_0A : string;
+ attribute INITVAL_09 : string;
+ attribute INITVAL_08 : string;
+ attribute INITVAL_07 : string;
+ attribute INITVAL_06 : string;
+ attribute INITVAL_05 : string;
+ attribute INITVAL_04 : string;
+ attribute INITVAL_03 : string;
+ attribute INITVAL_02 : string;
+ attribute INITVAL_01 : string;
+ attribute INITVAL_00 : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute GSR : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute MEM_LPC_FILE of ram_register_0_0_0 : label is "ram_register.lpc";
+ attribute MEM_INIT_FILE of ram_register_0_0_0 : label is "regmem.mem";
+ attribute INITVAL_3F of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_3E of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_3D of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_3C of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_3B of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_3A of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_39 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_38 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_37 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_36 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_35 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_34 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_33 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_32 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_31 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_30 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_2F of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_2E of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_2D of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_2C of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_2B of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_2A of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_29 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_28 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_27 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_26 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_25 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_24 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_23 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_22 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_21 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_20 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1F of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1E of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1D of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1C of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1B of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_1A of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_19 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_18 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_17 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_16 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_15 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_14 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_13 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_12 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_11 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_10 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_0F of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_0E of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_0D of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_0C of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_0B of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_0A of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_09 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_08 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_07 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_06 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_05 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_04 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_03 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_02 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_01 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute INITVAL_00 of ram_register_0_0_0 : label is "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000";
+ attribute CSDECODE_R of ram_register_0_0_0 : label is "0b000";
+ attribute CSDECODE_W of ram_register_0_0_0 : label is "0b001";
+ attribute GSR of ram_register_0_0_0 : label is "DISABLED";
+ attribute RESETMODE of ram_register_0_0_0 : label is "SYNC";
+ attribute REGMODE of ram_register_0_0_0 : label is "OUTREG";
+ attribute DATA_WIDTH_R of ram_register_0_0_0 : label is "36";
+ attribute DATA_WIDTH_W of ram_register_0_0_0 : label is "36";
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ ram_register_0_0_0: PDP16KA
+ -- synopsys translate_off
+ generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_03=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_02=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_01=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ INITVAL_00=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
+ CSDECODE_R=> "000", CSDECODE_W=> "001", GSR=> "DISABLED",
+ RESETMODE=> "SYNC", REGMODE=> "OUTREG", DATA_WIDTH_R=> 36,
+ DATA_WIDTH_W=> 36)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
+ DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
+ DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
+ DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
+ DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
+ DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ ADW0=>scuba_vhi, ADW1=>scuba_vhi, ADW2=>scuba_vhi,
+ ADW3=>scuba_vhi, ADW4=>scuba_vlo, ADW5=>WrAddress(0),
+ ADW6=>scuba_vlo, ADW7=>scuba_vlo, ADW8=>scuba_vlo,
+ ADW9=>scuba_vlo, ADW10=>scuba_vlo, ADW11=>scuba_vlo,
+ ADW12=>scuba_vlo, ADW13=>scuba_vlo, CEW=>WrClockEn,
+ CLKW=>WrClock, WE=>scuba_vhi, CSW0=>WE, CSW1=>scuba_vlo,
+ CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
+ ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
+ ADR5=>RdAddress(0), ADR6=>scuba_vlo, ADR7=>scuba_vlo,
+ ADR8=>scuba_vlo, ADR9=>scuba_vlo, ADR10=>scuba_vlo,
+ ADR11=>scuba_vlo, ADR12=>scuba_vlo, ADR13=>scuba_vlo,
+ CER=>RdClockEn, CLKR=>RdClock, CSR0=>scuba_vlo,
+ CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18),
+ DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23),
+ DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28),
+ DO11=>Q(29), DO12=>Q(30), DO13=>Q(31), DO14=>open,
+ DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1),
+ DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6),
+ DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
+ DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
+ DO34=>Q(16), DO35=>Q(17));
+
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of ram_register is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:PDP16KA use entity SCM.PDP16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+00000000
+00000000
--- /dev/null
+00000000
+00000000
\ No newline at end of file
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA15EP1
+PartName=LFSCM3GA15EP1-5F256C
+SpeedGrade=-5
+Package=FPBGA256
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.3
+ModuleName=scm_fifo_16bit_to_32bit
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=10/18/2010
+Time=12:34:05
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=512
+RWidth=32
+WDepth=1024
+WWidth=16
+regout=1
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.3
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n scm_fifo_16bit_to_32bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 16 -rwidth 32 -regout -no_enable -pe 10 -pf 508 -e
+
+-- Mon Oct 18 12:34:05 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity scm_fifo_16bit_to_32bit is
+ port (
+ Data: in std_logic_vector(15 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end scm_fifo_16bit_to_32bit;
+
+architecture Structure of scm_fifo_16bit_to_32bit is
+
+ -- internal signal declarations
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of scm_fifo_16bit_to_32bit_0_0 : label is "0b011111111100001";
+ attribute FULLPOINTER of scm_fifo_16bit_to_32bit_0_0 : label is "0b011111111110001";
+ attribute AFPOINTER1 of scm_fifo_16bit_to_32bit_0_0 : label is "0b001111110100001";
+ attribute AFPOINTER of scm_fifo_16bit_to_32bit_0_0 : label is "0b001111110110001";
+ attribute AEPOINTER1 of scm_fifo_16bit_to_32bit_0_0 : label is "0b000000101111111";
+ attribute AEPOINTER of scm_fifo_16bit_to_32bit_0_0 : label is "0b000000101011111";
+ attribute RESETMODE of scm_fifo_16bit_to_32bit_0_0 : label is "ASYNC";
+ attribute REGMODE of scm_fifo_16bit_to_32bit_0_0 : label is "OUTREG";
+ attribute CSDECODE_R of scm_fifo_16bit_to_32bit_0_0 : label is "0b11";
+ attribute CSDECODE_W of scm_fifo_16bit_to_32bit_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of scm_fifo_16bit_to_32bit_0_0 : label is "36";
+ attribute DATA_WIDTH_W of scm_fifo_16bit_to_32bit_0_0 : label is "18";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scm_fifo_16bit_to_32bit_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "011111111100001", FULLPOINTER=> "011111111110001",
+ AFPOINTER1=> "001111110100001", AFPOINTER=> "001111110110001",
+ AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 18)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
+ DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
+ DI15=>Data(15), DI16=>scuba_vlo, DI17=>scuba_vlo,
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
+ EMPTYI=>Empty_int, CSR0=>RdEn, CSR1=>scuba_vhi, WE=>WrEn,
+ RE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset,
+ RPRST=>RPReset, DO0=>Q(16), DO1=>Q(17), DO2=>Q(18),
+ DO3=>Q(19), DO4=>Q(20), DO5=>Q(21), DO6=>Q(22), DO7=>Q(23),
+ DO8=>Q(24), DO9=>Q(25), DO10=>Q(26), DO11=>Q(27),
+ DO12=>Q(28), DO13=>Q(29), DO14=>Q(30), DO15=>Q(31),
+ DO16=>open, DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2),
+ DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7),
+ DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11),
+ DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15),
+ DO34=>open, DO35=>open, EF=>Empty_int, AEF=>AlmostEmpty,
+ AFF=>AlmostFull, FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of scm_fifo_16bit_to_32bit is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA15EP1
+PartName=LFSCM3GA15EP1-5F256C
+SpeedGrade=-5
+Package=FPBGA256
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.3
+ModuleName=scm_fifo_1bit_to_32bit
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=10/18/2010
+Time=12:28:40
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=512
+RWidth=32
+WDepth=16384
+WWidth=1
+regout=1
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.3
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n scm_fifo_1bit_to_32bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 16384 -width 1 -rwidth 32 -regout -no_enable -pe 10 -pf 508 -e
+
+-- Mon Oct 18 12:28:42 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity scm_fifo_1bit_to_32bit is
+ port (
+ Data: in std_logic_vector(0 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end scm_fifo_1bit_to_32bit;
+
+architecture Structure of scm_fifo_1bit_to_32bit is
+
+ -- internal signal declarations
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of scm_fifo_1bit_to_32bit_0_0 : label is "0b011111111111111";
+ attribute FULLPOINTER of scm_fifo_1bit_to_32bit_0_0 : label is "0b100000000000000";
+ attribute AFPOINTER1 of scm_fifo_1bit_to_32bit_0_0 : label is "0b000000111111011";
+ attribute AFPOINTER of scm_fifo_1bit_to_32bit_0_0 : label is "0b000000111111100";
+ attribute AEPOINTER1 of scm_fifo_1bit_to_32bit_0_0 : label is "0b000000101111111";
+ attribute AEPOINTER of scm_fifo_1bit_to_32bit_0_0 : label is "0b000000101011111";
+ attribute RESETMODE of scm_fifo_1bit_to_32bit_0_0 : label is "ASYNC";
+ attribute REGMODE of scm_fifo_1bit_to_32bit_0_0 : label is "OUTREG";
+ attribute CSDECODE_R of scm_fifo_1bit_to_32bit_0_0 : label is "0b11";
+ attribute CSDECODE_W of scm_fifo_1bit_to_32bit_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of scm_fifo_1bit_to_32bit_0_0 : label is "36";
+ attribute DATA_WIDTH_W of scm_fifo_1bit_to_32bit_0_0 : label is "1";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scm_fifo_1bit_to_32bit_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "011111111111111", FULLPOINTER=> "100000000000000",
+ AFPOINTER1=> "000000111111011", AFPOINTER=> "000000111111100",
+ AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 1)
+ -- synopsys translate_on
+ port map (DI0=>scuba_vlo, DI1=>scuba_vlo, DI2=>scuba_vlo,
+ DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
+ DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
+ DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(0),
+ DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
+ DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
+ EMPTYI=>Empty_int, CSR0=>RdEn, CSR1=>scuba_vhi, WE=>WrEn,
+ RE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset,
+ RPRST=>RPReset, DO0=>Q(16), DO1=>Q(17), DO2=>Q(18),
+ DO3=>Q(19), DO4=>Q(20), DO5=>Q(21), DO6=>Q(22), DO7=>Q(23),
+ DO8=>open, DO9=>Q(24), DO10=>Q(25), DO11=>Q(26), DO12=>Q(27),
+ DO13=>Q(28), DO14=>Q(29), DO15=>Q(30), DO16=>Q(31),
+ DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
+ DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>open,
+ DO27=>Q(8), DO28=>Q(9), DO29=>Q(10), DO30=>Q(11),
+ DO31=>Q(12), DO32=>Q(13), DO33=>Q(14), DO34=>Q(15),
+ DO35=>open, EF=>Empty_int, AEF=>AlmostEmpty, AFF=>AlmostFull,
+ FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of scm_fifo_1bit_to_32bit is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA15EP1
+PartName=LFSCM3GA15EP1-5F256C
+SpeedGrade=-5
+Package=FPBGA256
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.3
+ModuleName=scm_fifo_2bit_to_32bit
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=10/18/2010
+Time=12:29:17
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=512
+RWidth=32
+WDepth=8192
+WWidth=2
+regout=1
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.3
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n scm_fifo_2bit_to_32bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 8192 -width 2 -rwidth 32 -regout -no_enable -pe 10 -pf 508 -e
+
+-- Mon Oct 18 12:29:17 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity scm_fifo_2bit_to_32bit is
+ port (
+ Data: in std_logic_vector(1 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end scm_fifo_2bit_to_32bit;
+
+architecture Structure of scm_fifo_2bit_to_32bit is
+
+ -- internal signal declarations
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of scm_fifo_2bit_to_32bit_0_0 : label is "0b011111111111101";
+ attribute FULLPOINTER of scm_fifo_2bit_to_32bit_0_0 : label is "0b011111111111111";
+ attribute AFPOINTER1 of scm_fifo_2bit_to_32bit_0_0 : label is "0b000001111110101";
+ attribute AFPOINTER of scm_fifo_2bit_to_32bit_0_0 : label is "0b000001111110111";
+ attribute AEPOINTER1 of scm_fifo_2bit_to_32bit_0_0 : label is "0b000000101111111";
+ attribute AEPOINTER of scm_fifo_2bit_to_32bit_0_0 : label is "0b000000101011111";
+ attribute RESETMODE of scm_fifo_2bit_to_32bit_0_0 : label is "ASYNC";
+ attribute REGMODE of scm_fifo_2bit_to_32bit_0_0 : label is "OUTREG";
+ attribute CSDECODE_R of scm_fifo_2bit_to_32bit_0_0 : label is "0b11";
+ attribute CSDECODE_W of scm_fifo_2bit_to_32bit_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of scm_fifo_2bit_to_32bit_0_0 : label is "36";
+ attribute DATA_WIDTH_W of scm_fifo_2bit_to_32bit_0_0 : label is "2";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scm_fifo_2bit_to_32bit_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "011111111111101", FULLPOINTER=> "011111111111111",
+ AFPOINTER1=> "000001111110101", AFPOINTER=> "000001111110111",
+ AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 2)
+ -- synopsys translate_on
+ port map (DI0=>scuba_vlo, DI1=>Data(1), DI2=>scuba_vlo,
+ DI3=>scuba_vlo, DI4=>scuba_vlo, DI5=>scuba_vlo,
+ DI6=>scuba_vlo, DI7=>scuba_vlo, DI8=>scuba_vlo,
+ DI9=>scuba_vlo, DI10=>scuba_vlo, DI11=>Data(0),
+ DI12=>scuba_vlo, DI13=>scuba_vlo, DI14=>scuba_vlo,
+ DI15=>scuba_vlo, DI16=>scuba_vlo, DI17=>scuba_vlo,
+ DI18=>scuba_vlo, DI19=>scuba_vlo, DI20=>scuba_vlo,
+ DI21=>scuba_vlo, DI22=>scuba_vlo, DI23=>scuba_vlo,
+ DI24=>scuba_vlo, DI25=>scuba_vlo, DI26=>scuba_vlo,
+ DI27=>scuba_vlo, DI28=>scuba_vlo, DI29=>scuba_vlo,
+ DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo,
+ DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
+ FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi,
+ EMPTYI=>Empty_int, CSR0=>RdEn, CSR1=>scuba_vhi, WE=>WrEn,
+ RE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset,
+ RPRST=>RPReset, DO0=>Q(16), DO1=>Q(17), DO2=>Q(18),
+ DO3=>Q(19), DO4=>Q(20), DO5=>Q(21), DO6=>Q(22), DO7=>Q(23),
+ DO8=>open, DO9=>Q(24), DO10=>Q(25), DO11=>Q(26), DO12=>Q(27),
+ DO13=>Q(28), DO14=>Q(29), DO15=>Q(30), DO16=>Q(31),
+ DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
+ DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>open,
+ DO27=>Q(8), DO28=>Q(9), DO29=>Q(10), DO30=>Q(11),
+ DO31=>Q(12), DO32=>Q(13), DO33=>Q(14), DO34=>Q(15),
+ DO35=>open, EF=>Empty_int, AEF=>AlmostEmpty, AFF=>AlmostFull,
+ FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of scm_fifo_2bit_to_32bit is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA15EP1
+PartName=LFSCM3GA15EP1-5F256C
+SpeedGrade=-5
+Package=FPBGA256
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.3
+ModuleName=scm_fifo_4bit_to_32bit
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=10/18/2010
+Time=12:29:51
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=512
+RWidth=32
+WDepth=4096
+WWidth=4
+regout=1
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.3
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n scm_fifo_4bit_to_32bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 4096 -width 4 -rwidth 32 -regout -no_enable -pe 10 -pf 508 -e
+
+-- Mon Oct 18 12:29:51 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity scm_fifo_4bit_to_32bit is
+ port (
+ Data: in std_logic_vector(3 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end scm_fifo_4bit_to_32bit;
+
+architecture Structure of scm_fifo_4bit_to_32bit is
+
+ -- internal signal declarations
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of scm_fifo_4bit_to_32bit_0_0 : label is "0b011111111111001";
+ attribute FULLPOINTER of scm_fifo_4bit_to_32bit_0_0 : label is "0b011111111111101";
+ attribute AFPOINTER1 of scm_fifo_4bit_to_32bit_0_0 : label is "0b000011111101001";
+ attribute AFPOINTER of scm_fifo_4bit_to_32bit_0_0 : label is "0b000011111101101";
+ attribute AEPOINTER1 of scm_fifo_4bit_to_32bit_0_0 : label is "0b000000101111111";
+ attribute AEPOINTER of scm_fifo_4bit_to_32bit_0_0 : label is "0b000000101011111";
+ attribute RESETMODE of scm_fifo_4bit_to_32bit_0_0 : label is "ASYNC";
+ attribute REGMODE of scm_fifo_4bit_to_32bit_0_0 : label is "OUTREG";
+ attribute CSDECODE_R of scm_fifo_4bit_to_32bit_0_0 : label is "0b11";
+ attribute CSDECODE_W of scm_fifo_4bit_to_32bit_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of scm_fifo_4bit_to_32bit_0_0 : label is "36";
+ attribute DATA_WIDTH_W of scm_fifo_4bit_to_32bit_0_0 : label is "4";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scm_fifo_4bit_to_32bit_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "011111111111001", FULLPOINTER=> "011111111111101",
+ AFPOINTER1=> "000011111101001", AFPOINTER=> "000011111101101",
+ AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 4)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>scuba_vlo, DI5=>scuba_vlo, DI6=>scuba_vlo,
+ DI7=>scuba_vlo, DI8=>scuba_vlo, DI9=>scuba_vlo,
+ DI10=>scuba_vlo, DI11=>scuba_vlo, DI12=>scuba_vlo,
+ DI13=>scuba_vlo, DI14=>scuba_vlo, DI15=>scuba_vlo,
+ DI16=>scuba_vlo, DI17=>scuba_vlo, DI18=>scuba_vlo,
+ DI19=>scuba_vlo, DI20=>scuba_vlo, DI21=>scuba_vlo,
+ DI22=>scuba_vlo, DI23=>scuba_vlo, DI24=>scuba_vlo,
+ DI25=>scuba_vlo, DI26=>scuba_vlo, DI27=>scuba_vlo,
+ DI28=>scuba_vlo, DI29=>scuba_vlo, DI30=>scuba_vlo,
+ DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo,
+ DI34=>scuba_vlo, DI35=>scuba_vlo, FULLI=>Full_int,
+ CSW0=>scuba_vhi, CSW1=>scuba_vhi, EMPTYI=>Empty_int,
+ CSR0=>RdEn, CSR1=>scuba_vhi, WE=>WrEn, RE=>scuba_vhi,
+ CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, RPRST=>RPReset,
+ DO0=>Q(16), DO1=>Q(17), DO2=>Q(18), DO3=>Q(19), DO4=>Q(20),
+ DO5=>Q(21), DO6=>Q(22), DO7=>Q(23), DO8=>open, DO9=>Q(24),
+ DO10=>Q(25), DO11=>Q(26), DO12=>Q(27), DO13=>Q(28),
+ DO14=>Q(29), DO15=>Q(30), DO16=>Q(31), DO17=>open,
+ DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4),
+ DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>open, DO27=>Q(8),
+ DO28=>Q(9), DO29=>Q(10), DO30=>Q(11), DO31=>Q(12),
+ DO32=>Q(13), DO33=>Q(14), DO34=>Q(15), DO35=>open,
+ EF=>Empty_int, AEF=>AlmostEmpty, AFF=>AlmostFull,
+ FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of scm_fifo_4bit_to_32bit is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+[Device]
+Family=latticescm
+PartType=LFSCM3GA15EP1
+PartName=LFSCM3GA15EP1-5F256C
+SpeedGrade=-5
+Package=FPBGA256
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=FIFO_DC
+CoreRevision=5.3
+ModuleName=scm_fifo_8bit_to_32bit
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=10/18/2010
+Time=12:33:20
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+FIFOImp=EBR Only
+RDepth=512
+RWidth=32
+WDepth=2048
+WWidth=8
+regout=1
+CtrlByRdEn=0
+EmpFlg=1
+PeMode=Static - Single Threshold
+PeAssert=10
+PeDeassert=12
+FullFlg=1
+PfMode=Static - Single Threshold
+PfAssert=508
+PfDeassert=506
+Reset=Async
+RDataCount=0
+WDataCount=0
+EnECC=0
--- /dev/null
+-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
+-- Module Version: 5.3
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n scm_fifo_8bit_to_32bit -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 2048 -width 8 -rwidth 32 -regout -no_enable -pe 10 -pf 508 -e
+
+-- Mon Oct 18 12:33:21 2010
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library SCM;
+use SCM.COMPONENTS.all;
+-- synopsys translate_on
+
+entity scm_fifo_8bit_to_32bit is
+ port (
+ Data: in std_logic_vector(7 downto 0);
+ WrClock: in std_logic;
+ RdClock: in std_logic;
+ WrEn: in std_logic;
+ RdEn: in std_logic;
+ Reset: in std_logic;
+ RPReset: in std_logic;
+ Q: out std_logic_vector(31 downto 0);
+ Empty: out std_logic;
+ Full: out std_logic;
+ AlmostEmpty: out std_logic;
+ AlmostFull: out std_logic);
+end scm_fifo_8bit_to_32bit;
+
+architecture Structure of scm_fifo_8bit_to_32bit is
+
+ -- internal signal declarations
+ signal Empty_int: std_logic;
+ signal Full_int: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component FIFO16KA
+ -- synopsys translate_off
+ generic (FULLPOINTER1 : in std_logic_vector(14 downto 0);
+ FULLPOINTER : in std_logic_vector(14 downto 0);
+ AFPOINTER1 : in std_logic_vector(14 downto 0);
+ AEPOINTER1 : in std_logic_vector(14 downto 0);
+ AFPOINTER : in std_logic_vector(14 downto 0);
+ AEPOINTER : in std_logic_vector(14 downto 0);
+ CSDECODE_R : in std_logic_vector(1 downto 0);
+ CSDECODE_W : in std_logic_vector(1 downto 0);
+ RESETMODE : in String; REGMODE : in String;
+ DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
+ -- synopsys translate_on
+ port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
+ DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
+ DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
+ DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
+ DI12: in std_logic; DI13: in std_logic;
+ DI14: in std_logic; DI15: in std_logic;
+ DI16: in std_logic; DI17: in std_logic;
+ DI18: in std_logic; DI19: in std_logic;
+ DI20: in std_logic; DI21: in std_logic;
+ DI22: in std_logic; DI23: in std_logic;
+ DI24: in std_logic; DI25: in std_logic;
+ DI26: in std_logic; DI27: in std_logic;
+ DI28: in std_logic; DI29: in std_logic;
+ DI30: in std_logic; DI31: in std_logic;
+ DI32: in std_logic; DI33: in std_logic;
+ DI34: in std_logic; DI35: in std_logic;
+ FULLI: in std_logic; CSW0: in std_logic;
+ CSW1: in std_logic; EMPTYI: in std_logic;
+ CSR0: in std_logic; CSR1: in std_logic; WE: in std_logic;
+ RE: in std_logic; CLKW: in std_logic; CLKR: in std_logic;
+ RST: in std_logic; RPRST: in std_logic;
+ DO0: out std_logic; DO1: out std_logic;
+ DO2: out std_logic; DO3: out std_logic;
+ DO4: out std_logic; DO5: out std_logic;
+ DO6: out std_logic; DO7: out std_logic;
+ DO8: out std_logic; DO9: out std_logic;
+ DO10: out std_logic; DO11: out std_logic;
+ DO12: out std_logic; DO13: out std_logic;
+ DO14: out std_logic; DO15: out std_logic;
+ DO16: out std_logic; DO17: out std_logic;
+ DO18: out std_logic; DO19: out std_logic;
+ DO20: out std_logic; DO21: out std_logic;
+ DO22: out std_logic; DO23: out std_logic;
+ DO24: out std_logic; DO25: out std_logic;
+ DO26: out std_logic; DO27: out std_logic;
+ DO28: out std_logic; DO29: out std_logic;
+ DO30: out std_logic; DO31: out std_logic;
+ DO32: out std_logic; DO33: out std_logic;
+ DO34: out std_logic; DO35: out std_logic;
+ EF: out std_logic; AEF: out std_logic; AFF: out std_logic;
+ FF: out std_logic);
+ end component;
+ attribute FULLPOINTER1 : string;
+ attribute FULLPOINTER : string;
+ attribute AFPOINTER1 : string;
+ attribute AFPOINTER : string;
+ attribute AEPOINTER1 : string;
+ attribute AEPOINTER : string;
+ attribute RESETMODE : string;
+ attribute REGMODE : string;
+ attribute CSDECODE_R : string;
+ attribute CSDECODE_W : string;
+ attribute DATA_WIDTH_R : string;
+ attribute DATA_WIDTH_W : string;
+ attribute FULLPOINTER1 of scm_fifo_8bit_to_32bit_0_0 : label is "0b011111111110001";
+ attribute FULLPOINTER of scm_fifo_8bit_to_32bit_0_0 : label is "0b011111111111001";
+ attribute AFPOINTER1 of scm_fifo_8bit_to_32bit_0_0 : label is "0b000111111010001";
+ attribute AFPOINTER of scm_fifo_8bit_to_32bit_0_0 : label is "0b000111111011001";
+ attribute AEPOINTER1 of scm_fifo_8bit_to_32bit_0_0 : label is "0b000000101111111";
+ attribute AEPOINTER of scm_fifo_8bit_to_32bit_0_0 : label is "0b000000101011111";
+ attribute RESETMODE of scm_fifo_8bit_to_32bit_0_0 : label is "ASYNC";
+ attribute REGMODE of scm_fifo_8bit_to_32bit_0_0 : label is "OUTREG";
+ attribute CSDECODE_R of scm_fifo_8bit_to_32bit_0_0 : label is "0b11";
+ attribute CSDECODE_W of scm_fifo_8bit_to_32bit_0_0 : label is "0b11";
+ attribute DATA_WIDTH_R of scm_fifo_8bit_to_32bit_0_0 : label is "36";
+ attribute DATA_WIDTH_W of scm_fifo_8bit_to_32bit_0_0 : label is "9";
+ attribute syn_keep : boolean;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scm_fifo_8bit_to_32bit_0_0: FIFO16KA
+ -- synopsys translate_off
+ generic map (FULLPOINTER1=> "011111111110001", FULLPOINTER=> "011111111111001",
+ AFPOINTER1=> "000111111010001", AFPOINTER=> "000111111011001",
+ AEPOINTER1=> "000000101111111", AEPOINTER=> "000000101011111",
+ RESETMODE=> "ASYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11",
+ CSDECODE_W=> "11", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 9)
+ -- synopsys translate_on
+ port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
+ DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
+ DI8=>scuba_vlo, DI9=>scuba_vlo, DI10=>scuba_vlo,
+ DI11=>scuba_vlo, DI12=>scuba_vlo, DI13=>scuba_vlo,
+ DI14=>scuba_vlo, DI15=>scuba_vlo, DI16=>scuba_vlo,
+ DI17=>scuba_vlo, DI18=>scuba_vlo, DI19=>scuba_vlo,
+ DI20=>scuba_vlo, DI21=>scuba_vlo, DI22=>scuba_vlo,
+ DI23=>scuba_vlo, DI24=>scuba_vlo, DI25=>scuba_vlo,
+ DI26=>scuba_vlo, DI27=>scuba_vlo, DI28=>scuba_vlo,
+ DI29=>scuba_vlo, DI30=>scuba_vlo, DI31=>scuba_vlo,
+ DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo,
+ DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi,
+ CSW1=>scuba_vhi, EMPTYI=>Empty_int, CSR0=>RdEn,
+ CSR1=>scuba_vhi, WE=>WrEn, RE=>scuba_vhi, CLKW=>WrClock,
+ CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>Q(16),
+ DO1=>Q(17), DO2=>Q(18), DO3=>Q(19), DO4=>Q(20), DO5=>Q(21),
+ DO6=>Q(22), DO7=>Q(23), DO8=>open, DO9=>Q(24), DO10=>Q(25),
+ DO11=>Q(26), DO12=>Q(27), DO13=>Q(28), DO14=>Q(29),
+ DO15=>Q(30), DO16=>Q(31), DO17=>open, DO18=>Q(0), DO19=>Q(1),
+ DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6),
+ DO25=>Q(7), DO26=>open, DO27=>Q(8), DO28=>Q(9), DO29=>Q(10),
+ DO30=>Q(11), DO31=>Q(12), DO32=>Q(13), DO33=>Q(14),
+ DO34=>Q(15), DO35=>open, EF=>Empty_int, AEF=>AlmostEmpty,
+ AFF=>AlmostFull, FF=>Full_int);
+
+ Empty <= Empty_int;
+ Full <= Full_int;
+end Structure;
+
+-- synopsys translate_off
+library SCM;
+configuration Structure_CON of scm_fifo_8bit_to_32bit is
+ for Structure
+ for all:VHI use entity SCM.VHI(V); end for;
+ for all:VLO use entity SCM.VLO(V); end for;
+ for all:FIFO16KA use entity SCM.FIFO16KA(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+
+# This file is used by the simulation model as well as the ispLEVER bitstream
+# generation process to automatically initialize the PCSC quad to the mode
+# selected in the IPexpress. This file is expected to be modified by the
+# end user to adjust the PCSC quad to the final design requirements.
+
+DEVICE_NAME "LFE2M20E"
+PROTOCOL "GIGE"
+CH0_MODE "SINGLE"
+CH1_MODE "DISABLE"
+CH2_MODE "DISABLE"
+CH3_MODE "DISABLE"
+PLL_SRC "CORE_TXREFCLK"
+DATARANGE "MEDHIGH"
+CH0_CDR_SRC "CORE_RXREFCLK"
+CH0_DATA_WIDTH "16"
+CH0_REFCK_MULT "20X"
+#REFCLK_RATE 100
+#FPGAINTCLK_RATE 100
+CH0_TDRV_AMP "0"
+CH0_TX_PRE "DISABLE"
+CH0_RTERM_TX "50"
+CH0_RX_EQ "DISABLE"
+CH0_RTERM_RX "50"
+CH0_RX_DCC "DC"
+LOS_THRESHOLD "0"
+PLL_TERM "50"
+PLL_DCC "DC"
+PLL_LOL_SET "0"
+CH0_TX_SB "NORMAL"
+CH0_RX_SB "NORMAL"
+CH0_8B10B "NORMAL"
+COMMA_A "1100000101"
+COMMA_B "0011111010"
+COMMA_M "1111111111"
+CH0_COMMA_ALIGN "AUTO"
+CH0_CTC_BYP "NORMAL"
+CC_MATCH1 "0000000000"
+CC_MATCH2 "0000000000"
+CC_MATCH3 "0110111100"
+CC_MATCH4 "0001010000"
+CC_MATCH_MODE "MATCH_3_4"
+CC_MIN_IPG "3"
+CCHMARK "9"
+CCLMARK "7"
+OS_REFCK2CORE "1"
+OS_PLLQCLKPORTS "0"
+OS_INT_ALL "0"
+
--- /dev/null
+\r
+# This file is used by the simulation model as well as the ispLEVER bitstream\r
+# generation process to automatically initialize the PCS quad to the mode\r
+# selected in the IPexpress. This file is expected to be modified by the\r
+# end user to adjust the PCS quad to the final design requirements.\r
+# channel_0 is in "8b10b" mode\r
+# channel_1 is in "Disabled" mode\r
+# channel_2 is in "Disabled" mode\r
+# channel_3 is in "Disabled" mode\r
+\r
+ch0 13 03 # Powerup Channel 0 TX/RX\r
+ch0 00 01 # link state machine enabled\r
+quad 00 00 # some standard settings?\r
+quad 01 E4 # RX clock select\r
+quad 28 50 # Reference clock multiplier\r
+quad 29 01 # set to 01\r
+quad 02 00 # ref_pclk source is ch0, rxa_pclk is ch0, rxb_pclk is ch0\r
+quad 04 00 # MCA enable 4 channels\r
+\r
+quad 18 10 # 8b10b Mode\r
+\r
+quad 14 FF # Word Alignment Mask [7:0]\r
+quad 15 05 # +ve K [7:0] -> COMMA_A = 11_0000_0101\r
+quad 16 FA # -ve K [7:0] -> COMMA_B = 00_1111_1010\r
+quad 17 3C # upper bits of CA,CB,CM\r
+\r
+quad 0D 97 # Watermark level on CTC: 9 high, 7 low\r
+quad 0E 0B # insertion/deletion control of CTC: two char matching\r
+quad 11 BC # /I2/ pattern for CTC match (K28.5)\r
+quad 12 50 # (D16.2) \r
+quad 13 04 # (use comma)\r
+\r
+quad 19 0C # Disable word_align_en port, FPGA bus width is 16-bit/20-bit\r
+ch0 14 90 # 16% pre-emphasis \r
+ch0 15 10 # +6dB equalization\r
+\r
+# These lines must appear last in the autoconfig file. These lines apply the correct \r
+# reset sequence to the PCS block upon bitstream configuration\r
+quad 41 00 # de-assert serdes_rst\r
+quad 40 ff # assert datapath reset for all channels\r
+quad 40 00 # de-assert datapath reset for all channels\r
+\r
+\r
+\r
--- /dev/null
+#!/usr/bin/perl
+###########################################
+# Script file to compy vhd files to the simulation directory and to make
+# all needed changes:
+# uncomments lines where at the beginning is --sim
+# comments lines where at the end is --no_sim--
+###########################################
+#
+# M.Palka
+#
+use FileHandle;
+use strict;
+use warnings;
+
+my $c="cp -u *.vhd simulation/";
+system($c);
+
+chdir "simulation";
+
+my $temptext;
+my $fh = new FileHandle("< cts_cal_screset_gen.vhd");
+my $fh1 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh>)
+{
+ $temptext = $_;
+ $temptext =~ s/--sim--//;
+ if($temptext =~ /--no_sim--/)
+ {
+ $temptext = "--".$temptext;
+ }
+ print {$fh1} $temptext;
+}
+$fh -> close;
+$fh1 -> close;
+
+$c="cp temp_perl.vhd cts_cal_screset_gen.vhd";
+system($c);
+
+
+
+my $fh4 = new FileHandle("< cts_fpga1.vhd");
+my $fh5 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh4>)
+{
+ $temptext = $_;
+ $temptext =~ s/--sim--//;
+ if($temptext =~ /--no_sim--/)
+ {
+ $temptext = "--".$temptext;
+ }
+ print {$fh5} $temptext;
+}
+$fh4 -> close;
+$fh5 -> close;
+$c="cp temp_perl.vhd cts_fpga1.vhd";
+system($c);
+
+
+$c="cp ~/trbnet/trb_net_components.vhd .";
+system($c);
+my $fh6 = new FileHandle("< trb_net_components.vhd");
+my $fh7 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh6>)
+{
+ $temptext = $_;
+ $temptext =~ s/--simcts--//;
+ if($temptext =~ /--no_sim--/)
+ {
+ $temptext = "--".$temptext;
+ }
+ print {$fh7} $temptext;
+}
+$fh6 -> close;
+$fh7 -> close;
+$c="cp temp_perl.vhd trb_net_components.vhd";
+system($c);
+
+
+$c="cp ~/trbnet/media_interfaces/trb_net16_med_ecp_sfp_gbe.vhd .";
+system($c);
+my $fh8 = new FileHandle("< trb_net16_med_ecp_sfp_gbe.vhd");
+my $fh9 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh8>)
+{
+ $temptext = $_;
+ $temptext =~ s/--sim--//;
+ if($temptext =~ /--no_sim--/)
+ {
+ $temptext = "--".$temptext;
+ }
+ print {$fh9} $temptext;
+}
+$fh8 -> close;
+$fh9 -> close;
+$c="cp temp_perl.vhd trb_net16_med_ecp_sfp_gbe.vhd";
+system($c);
+
+
+
+
+
+$c="cp ~/trbnet/media_interfaces/trb_net16_lsm_sfp.vhd .";
+system($c);
+my $fh10 = new FileHandle("< trb_net16_lsm_sfp.vhd");
+my $fh11 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh10>)
+{
+ $temptext = $_;
+ $temptext =~ s/--sim--//;
+ if($temptext =~ /--no_sim--/)
+ {
+ $temptext = "--".$temptext;
+ }
+ print {$fh11} $temptext;
+}
+$fh10 -> close;
+$fh11 -> close;
+$c="cp temp_perl.vhd trb_net16_lsm_sfp.vhd";
+system($c);
+
+
+
+
+
+
+
+my $fh12 = new FileHandle("< cts_fpga2.vhd");
+my $fh13 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh12>)
+{
+ $temptext = $_;
+ $temptext =~ s/--sim--//;
+ if($temptext =~ /--no_sim--/)
+ {
+ $temptext = "--".$temptext;
+ }
+ print {$fh13} $temptext;
+}
+$fh12 -> close;
+$fh13 -> close;
+$c="cp temp_perl.vhd cts_fpga2.vhd";
+system($c);
+
+
+my $fh14 = new FileHandle("< cts_set_width.vhd");
+my $fh15 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh14>)
+{
+ $temptext = $_;
+ $temptext =~ s/--sim--//;
+ if($temptext =~ /--no_sim--/)
+ {
+ $temptext = "--".$temptext;
+ }
+ print {$fh15} $temptext;
+}
+$fh14 -> close;
+$fh15 -> close;
+$c="cp temp_perl.vhd cts_set_width.vhd";
+system($c);
+
+my $fh16 = new FileHandle("< ddr2_busses.vhd");
+my $fh17 = new FileHandle("> temp_perl.vhd");
+
+while(<$fh16>)
+{
+ $temptext = $_;
+ $temptext =~ s/--sim--//;
+ if($temptext =~ /--no_sim--/)
+ {
+ $temptext = "--".$temptext;
+ }
+ print {$fh17} $temptext;
+}
+$fh16 -> close;
+$fh17 -> close;
+$c="cp temp_perl.vhd ddr2_busses.vhd";
+system($c);
+
+
--- /dev/null
+
+--## attention, automatically generated. Don't change by hand.
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.std_logic_ARITH.ALL;
+USE IEEE.std_logic_UNSIGNED.ALL;
+use ieee.numeric_std.all;
+
+package version is
+
+ constant VERSION_NUMBER_TIME : integer := 1325593830;
+
+end package version;
--- /dev/null
+#!/usr/bin/perl -w
+
+use strict;
+use Data::Dumper;
+use List::Util qw(max);
+use Getopt::Long;
+
+my $opt_all = 0;
+my $opt_help = 0;
+
+my $resultOpt = GetOptions ('a|all' => \$opt_all,
+ 'h|help' => \$opt_help);
+
+if($opt_help){
+ &help();
+ exit(0);
+}
+
+my %addr2sig = (
+ '000' => '0000',
+ '001' => '0001',
+ '010' => '0010',
+ '011' => '0100',
+ '100' => '1000',
+ '101' => '1001',
+ '110' => '1010',
+ '111' => '0101'
+);
+
+my $addr2sig_href = \%addr2sig;
+
+my @signals;
+my $signals_aref = \@signals;
+my @overflow;
+my $overflow_aref = \@overflow;
+
+if($opt_all){
+ print "#sig1 val sig2 rem div sig2 rem div\n";
+ print "#bin dec bin bin dec hex hex hex\n";
+}
+
+&generate();
+
+exit(0);
+
+################### END OF MAIN ###################
+
+sub generate()
+{
+ #- loop over addresses (0...111111)
+ foreach my $addr (0..63){
+ my $str = &dec2bin($addr);
+
+ my $first3bins;
+ my $last3bins;
+
+ if( $str =~ /\d{2}(\d{3})(\d{3})/ ){
+ $first3bins = $2;
+ $last3bins = $1;
+ }
+
+ unless( defined $first3bins && defined $last3bins ){
+ print "Three first or/and last bits undefined. Exit.\n";
+ exit(1);
+ }
+
+ my $signal = $addr2sig_href->{$last3bins} .
+ $addr2sig_href->{$first3bins};
+
+ my $ext_sig;
+ my $ov_flow;
+
+ #- Loop over values for signal length extentions
+ foreach my $val (0..31){
+
+ #- Bit mask
+ my $bit1 = '00000001';
+
+ if( &bin2dec($signal) ){
+
+ #- Loop over all 8 bits in a given signal
+ while( 1 ){
+ if( &bin2dec( $bit1 & $signal ) ){
+ #- If bit1 mask matches '1' in the signal
+ # we extend the signal length for this bit
+ # by the value of 'val'
+ &extendSigLength( $bit1, $val );
+ }
+
+ #- If we reach the last bit in the mask, we quit the loop
+ last if( &bin2dec('10000000') == &bin2dec($bit1) );
+
+ #- Shift '1' in the mask
+ $bit1 = shiftLeft( $bit1 );
+ }
+
+ $ext_sig = &makeNewSignal();
+ $ov_flow = max @$overflow_aref;
+ }
+ else{
+ $ext_sig = '00000000';
+ $ov_flow = 0;
+ }
+
+ #if( $signals_aref ){
+ # print Dumper $signals_aref;
+ #}
+
+ &printResult($signal, $ext_sig, $ov_flow, $val);
+
+ $signals_aref = ();
+ $overflow_aref = ();
+
+ #sleep 1;
+ }
+ }
+}
+
+sub printResult()
+{
+ my ($sig1_bin, $sig2_bin, $ovflow_dec, $val) = @_;
+
+ my $divsion = int( $ovflow_dec / 8 );
+ my $remainder = $ovflow_dec % 8;
+
+ my $rem_bin = &remainder2Bin($remainder);
+
+ my $sig2_hex = bin2hex($sig2_bin);
+ my $rem_hex = bin2hex($rem_bin);
+
+ my $div_hex = dec2hex($divsion);
+
+ if($opt_all){
+ print sprintf("%s %02d %s %s %d ", $sig1_bin, $val, $sig2_bin, $rem_bin, $divsion);
+ }
+ print sprintf("%02s %02s %1x\n", $sig2_hex, $rem_hex, $div_hex);
+}
+
+sub dec2hex()
+{
+ my ($dec) = @_;
+
+ my $hex = unpack("H*", pack("N", $dec));
+
+ return $hex;
+}
+
+sub bin2hex()
+{
+ my ($binary) = @_;
+
+ my $int = unpack("N", pack("B32", substr("0" x 32 . $binary, -32)));
+ my $hex = sprintf("%x", $int );
+
+ return $hex;
+}
+
+sub remainder2Bin()
+{
+ my ($numOf1s) = @_;
+
+ return '00000000' if( $numOf1s == 0 );
+
+ my $tmp;
+
+ foreach my $one (1..$numOf1s){
+ $tmp = $tmp . '1';
+ }
+
+ my $dec = &bin2dec($tmp);
+ my $bin = &dec2bin($dec);
+
+ return $bin;
+}
+
+sub extendSigLength()
+{
+ my ($bit1, $val) = @_;
+
+ my $ov_flow = 0;
+
+ foreach my $i (0..$val){
+
+ if( &bin2dec($bit1) <= &bin2dec('10000000') ){
+ push( @$signals_aref, $bit1 );
+
+ if( &bin2dec($bit1) < &bin2dec('10000000') ){
+ $bit1 = shiftLeft( $bit1 );
+ }
+
+ if( $i > 0 && ($signals_aref->[-1] eq $signals_aref->[-2]) ){
+ $ov_flow++;
+ }
+ }
+ }
+
+ push( @$overflow_aref, $ov_flow );
+}
+
+sub makeNewSignal()
+{
+ #- Extended signal
+ my $sig_ext = '00000000';
+ my $ext_dec = &bin2dec( $sig_ext );
+
+ #- Sum up all sinlge signals
+ foreach my $sig (@$signals_aref){
+ $sig_ext = $sig_ext | $sig;
+ }
+
+ return $sig_ext;
+}
+
+sub shiftLeft()
+{
+ my ($bin1) = @_;
+
+ my $dec1 = &bin2dec($bin1);
+ my $dec2 = $dec1 << 1;
+ my $bin2 = &dec2bin($dec2);
+
+ return $bin2;
+}
+
+sub dec2bin()
+{
+ my ($dec) = @_;
+
+ my $str = unpack("B32", pack("C", $dec));
+
+ return $str;
+}
+
+sub dec2bin_new()
+{
+ my ($dec, $nbits) = @_;
+
+ my $str;
+
+ if( $nbits == 8 ){
+ #- Returning string with 8-bits
+ $str = unpack("B32", pack("C", $dec));
+ }
+ elsif( $nbits == 64 ){
+ #- Returning string with 64-bits
+ $str = unpack("B32", pack("Q", $dec));
+ }
+ else{
+ print "Length of bits must be ether 8 or 64. Exit.\n";
+ exit(1);
+ }
+
+ #$str =~ s/^0+(?=\d)//; # otherwise you'll get leading zeros
+
+ return $str;
+}
+
+sub bin2dec()
+{
+ my ($bin) = @_;
+
+ return unpack("N", pack("B32", substr("0" x 32 . $bin, -32)));
+}
+
+sub help()
+{
+
+ print "\n";
+ print << 'EOF';
+widthGenerator.pl
+
+ This script generates signals with extended width for the CTS
+ (Central Trigger System) accordning to the following format (in Hex):
+ <8-bit signal> <8-bit reminder> <2-bit integer result of division>
+
+ Signal is extended by the value in the range 0-31.
+ For example, signal 00010010 and value 2 result in extended signal
+ 01111110 with reminder 00000000 and 00 or in hex 7e 00 0.
+ For the signal 00010010 and value 12 we get 11111110 with reminder
+ 00000001 and 01 or in hex fe 01 1.
+
+ The mapping between memory addresses and signals is given in %addr2sig hash.
+
+Usage:
+
+ Command line: widthGenerator.pl
+ Without args : Generate hex output for the extended signals.
+ [-a|--all] : Show additional numbers in bin and hex formats.
+
+Examples:
+
+ For the debugging run: widthGenerator.pl -a
+ It will generate an extended output like:
+ #sig1 val sig2 rem div sig2 rem div
+ #bin dec bin bin dec hex hex hex
+ 00000000 00 00000000 00000000 0 00 00 0
+ 00000000 01 00000000 00000000 0 00 00 0
+ .............................................
+ 00000001 16 11111111 00000001 1 ff 01 1
+ 00000001 17 11111111 00000011 1 ff 03 1
+ 00000001 18 11111111 00000111 1 ff 07 1
+ .............................................
+
+ where
+ sig1 : Initial signal in binary format.
+ val : Value for signal extension in decimal format.
+ sig2 : Extended signal in binary format.
+ rem : Remainder after devision by 8 in binary format.
+ div : Integer number of devisions by 8 in decimal format.
+ sig2 : Extended signal in hex format.
+ rem : Remainder after devision by 8 in hex format.
+ div : Integer number of devisions by 8 in hex format.
+
+ The final extended signal output: sig2(hex)+rem(hex)+div(hex)
+
+EOF
+}
--- /dev/null
+#!/usr/bin/perl -w
+
+use strict;
+use Data::Dumper;
+use List::Util qw(max);
+use Getopt::Long;
+
+my $opt_all = 0;
+my $opt_help = 0;
+
+my $resultOpt = GetOptions ('a|all' => \$opt_all,
+ 'h|help' => \$opt_help);
+
+if($opt_help){
+ &help();
+ exit(0);
+}
+
+# Maximum number of addresses which lead to none zero result
+my $maxNrOfAddr = 8;
+
+my $maxProlong = 31;
+
+my %addr2sig = (
+ 0 => '00000000',
+ 1 => '00000001',
+ 2 => '00000010',
+ 3 => '00000100',
+ 4 => '00001000',
+ 5 => '00010000',
+ 6 => '00100000',
+ 7 => '01000000',
+ 8 => '10000000'
+ );
+
+my $addr2sig_href = \%addr2sig;
+
+#- Map number of remaining ones to hex numbers
+my %mapRemain2hex = (
+ 0 => '0',
+ 1 => '1',
+ 2 => '3',
+ 3 => '7',
+ 4 => 'f',
+ 5 => 'f',
+ 6 => 'f',
+ 7 => 'f',
+ 8 => 'f',
+ 9 => 'f'
+ );
+
+my $mapRemain2hex_href = \%mapRemain2hex;
+
+&printAddresses();
+#&getProlongSig(0x80, 31);
+
+exit(0);
+
+############### END OF MAIN #################
+
+sub help()
+{
+ print "\n";
+ print << 'EOF';
+widthGenerator2.pl
+
+ This script generates signals with extended width for the CTS
+ (Central Trigger System) accordning to the following format:
+
+ Prolongation Signal Result
+ 31 - 0 7 - 0 -> 35 - 0
+ 000......000 00..00 00..00000000
+ 000......000 00..01 00..00000001
+
+ 000......000 10..00 00..10000000
+ 000......000 11..00 00..00000000 <---
+
+ 000......001 00..01 00..00000011
+ 000......011 00..01 00..00001111
+
+ Only Signlas from 0x0 to 0x8 produce the result.
+ Signals from 0x9 to 0xf result in zeros as indicated by arrow.
+
+ The result is printed in hex.
+
+EOF
+}
+
+sub printAddresses()
+{
+ foreach my $prolong (0..$maxProlong){
+
+ #- Get decimal value which corresponds
+ # to a number of ones 111..11 equal to $prolong.
+ my $prolDec = &getProlongBits($prolong);
+ my $prolBin = &dec2bin($prolDec);
+
+ foreach my $var (0..15){
+ my $remain = 0;
+
+ if( $var <= $maxNrOfAddr ){
+
+ my $sigBin = $addr2sig_href->{$var};
+ my $sigDec = &bin2dec($sigBin);
+ my $sigProlDec = &getProlongSig($sigDec, $prolong, \$remain);
+ my $sigProlBin = &dec2bin( $sigProlDec );
+
+ printf("%01s%08x\n", $mapRemain2hex_href->{$remain}, $sigProlDec);
+
+ #printf("%031s %08s %036s %012s 0x%09x 0x%s\n", $prolBin, $sigBin, $sigProlBin, $sigProlDec, $sigProlDec, $mapRemain2hex_href->{$remain});
+ }
+ else{
+
+ printf("%01s%08x\n", 0, 0);
+ #printf("%031s %08s %036s %012s 0x%09x 0x%x\n", 0, 0, 0, 0, 0, $remain);
+ }
+ }
+ }
+}
+
+sub getProlongSig()
+{
+ my ($sig, $nrOfOnes, $remain) = @_;
+
+ my $retval = $sig;
+
+ my $do_remain = 1;
+ $do_remain = 0 if($sig == 0);
+
+ foreach my $one (1..$nrOfOnes){
+ $sig = $sig << 1;
+ $retval = $retval | $sig;
+
+ $$remain++ if($sig == 0 && $do_remain);
+
+ #print "retval: $retval one: $one remain: $remain\n";
+ }
+
+ return $retval;
+}
+
+sub getProlongBits()
+{
+ my ($nrOfOnes) = @_;
+
+ return $nrOfOnes if($nrOfOnes == 0);
+ return $nrOfOnes if($nrOfOnes == 1);
+
+ my $retval = 1;
+
+ foreach my $one (2..$nrOfOnes){
+ $retval = $retval | ($retval << 1);
+ }
+
+ return $retval;
+}
+
+sub bin2hex()
+{
+ my $int = unpack("N", pack("B32", substr("0" x 32 . shift, -32)));
+ return sprintf("%x", $int );
+}
+
+sub hex2bin()
+{
+ my ($hex) = @_;
+
+ die "hex2bin(): indefined hex variable!" unless( defined $hex );
+
+ $hex = $1 if( $hex =~ /0x(\w+)/ );
+
+ return sprintf "%032b", hex( $hex );
+}
+
+sub dec2bin
+{
+ my $str = unpack("B32", pack("N", shift));
+ $str =~ s/^0+(?=\d)//; # otherwise you'll get leading zeros
+ return $str;
+}
+
+sub bin2dec
+{
+ return unpack("N", pack("B32", substr("0" x 32 . shift, -32)));
+}
+
jspc29 / ctsaddon.git / commitdiff