signal input_data : std_logic_vector(18 downto 0);
signal sclk_r, sclk_rr : std_logic;
signal last_valid : std_logic;
+ signal last_flag : std_logic;
+ signal chiptime : unsigned(15 downto 0);
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
SPI_MISO_IN => spi_miso,
SPI_CLK_OUT => spi_clk,
--Header
- HEADER_IO => HDR_IO,
+ HEADER_IO => open, --HDR_IO,
--LCD
LCD_DATA_IN => lcd_data,
--ADC
---------------------------------------------------------------------------
sclk_r <= CLK_IN when rising_edge(clk_sys);
sclk_rr <= sclk_r when rising_edge(clk_sys);
-input_data <= VALID_IN & CMD_IN & ADDRPIX_IN when rising_edge(clk_sys);
+input_data <= VALID_IN & CMD_IN(7) & '0' & CMD_IN(5 downto 4) & ADDRPIX_IN when rising_edge(clk_sys);
THE_READER : process begin
wait until rising_edge(clk_sys);
fifo_write <= '0';
- if sclk_r = '1' and sclk_rr = '0' then
+ if sclk_r = '0' and sclk_rr = '1' then
+ last_flag <= input_data(17);
+ if fwd_do_send = '1' and fifo_full = '0' then
+ if input_data(17) = '1' and last_flag = '0' then
+ fifo_data_in <= x"000" & "000" & input_data(18 downto 14) & std_logic_vector(chiptime);
+ fifo_write <= '1';
+ end if;
+ end if;
+
+ elsif sclk_r = '1' and sclk_rr = '0' then
last_valid <= input_data(18);
+ chiptime <= chiptime + 1;
+
if fwd_do_send = '1' and fifo_full = '0' then
- if input_data(18) = '1' then
- fifo_data_in <= x"0" & x"000" & input_data(17 downto 14) & "00" & input_data(13 downto 0);
+ if input_data(18) = '1' then
+ fifo_data_in <= x"000" & "000" & input_data(18 downto 14) & "00" & input_data(13 downto 0);
fifo_write <= '1';
elsif last_valid = '1' then
fifo_data_in <= x"0FFFFFFFF";
-- Test data
---------------------------------------------------------------------------
+
+gen_test_pulse : if 1 = 1 generate
+ signal pulse, pulse_r : std_logic;
+ signal cnt : unsigned(1 downto 0);
+ signal outp : std_logic;
+begin
+ PROC_TRG_PULSE : process begin
+ wait until rising_edge(clk_sys);
+ pulse <= CMD_IN(6);
+ pulse_r <= pulse;
+ if pulse = '0' then
+ outp <= '0';
+ end if;
+ if pulse = '1' and pulse_r = '0' then
+ cnt <= cnt + 1;
+ if cnt = 3 then
+ outp <= '1';
+ end if;
+ end if;
+ end process;
+
+ HDR_IO(1) <= outp;
+
+end generate;
+
+
end architecture;