constant INIT_ADDRESS : std_logic_vector := x"F3CE";
constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"61"; --61 with GbE, 60 without
- constant INCLUDE_UART : integer := c_NO; -- was c_YES
- constant INCLUDE_SPI : integer := c_NO; -- was c_YES
+ constant INCLUDE_UART : integer := c_NO;
+ constant INCLUDE_SPI : integer := c_NO;
constant INCLUDE_LCD : integer := c_NO;
- constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; -- was c_YES
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO;
--input monitor and trigger generation logic
- constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; -- was c_YES
- constant INCLUDE_STATISTICS : integer := c_NO; -- was c_YES
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_NO;
+ constant INCLUDE_STATISTICS : integer := c_NO;
constant TRIG_GEN_INPUT_NUM : integer := 22+32;
constant TRIG_GEN_OUTPUT_NUM : integer := 4;
constant MONITOR_INPUT_NUM : integer := 22+32;
-- port 10: SFP1 (inner) trigger
-- port 11: internal sctrl
- constant INTERFACE_NUM_ARR : hub_mii_t := (11,10);
- constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,0,0,0,0,0, 1,1,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0, 1,1,1,0,0,0,0,0));
- constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,1,1,1,1,1, 0,1,1,0,0,0,0,0),
- (1,1,1,1,1,1,1,1,1, 1,0,0,0,0,0,0,0));
- constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,0,0,0,0,0, 1,0,0,0,0,0,0,0),
- (0,0,0,0,0,0,0,0,0, 0,1,1,0,0,0,0,0));
+ constant INTERFACE_NUM_ARR : hub_mii_t := (6,5); -- number of SerDes links
+ constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0, 1,1,0,0,0,0,0,0,0,0,0,0,0),
+ (0,0,0,0, 1,1,1,0,0,0,0,0,0,0,0,0,0));
+ constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1, 0,1,1,0,0,0,0,0,0,0,0,0,0),
+ (1,1,1,1, 1,0,0,0,0,0,0,0,0,0,0,0,0));
+ constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0, 1,0,0,0,0,0,0,0,0,0,0,0,0),
+ (0,0,0,0, 0,1,1,0,0,0,0,0,0,0,0,0,0));
-
- constant INTERFACE_NUM : integer;
+ constant INTERFACE_NUM : integer;
constant MII_IS_UPLINK : hub_ct;
constant MII_IS_DOWNLINK : hub_ct;
constant MII_IS_UPLINK_ONLY : hub_ct;
package body config is
--compute correct configuration mode
- constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector(
HW_INFO_BASE );
- constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
- constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
- constant CFG_MODE : integer := INCLUDE_GBE;
- constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE);
+ constant CFG_MODE : integer := INCLUDE_GBE;
+ constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE);
constant MII_IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE);
constant MII_IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE);
constant MII_IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE);
port map(
INT_CLK_IN => CLK_CORE_PCLK,
EXT_CLK_IN => CLK_EXT_PLL_LEFT,
- NET_CLK_FULL_IN => med2int(9).clk_full,
- NET_CLK_HALF_IN => med2int(9).clk_half,
+ NET_CLK_FULL_IN => med2int(4).clk_full,
+ NET_CLK_HALF_IN => med2int(4).clk_half,
RESET_FROM_NET => reset_from_net_i,
SEND_RESET_IN => send_reset_i,
DEBUG_OUT => debug_clock_reset
);
- reset_from_net_i <= med2int(9).stat_op(13) or external_reset_delayed(4) ;
- send_reset_i <= med2int(9).stat_op(15); --int2med(0).ctrl_op(15) or;
+ reset_from_net_i <= med2int(4).stat_op(13) or external_reset_delayed(4);
+ send_reset_i <= med2int(4).stat_op(15);
---------------------------------------------------------------------------
-- TrbNet Uplink
---------------------------------------------------------------------------
-THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync_4_slave3 --PCSB
+THE_MEDIA_INT_MIXED : entity work.med_ecp3_sfp_sync --PCSB
generic map(
- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_YES),
- IS_USED => (c_YES, c_YES, c_YES, c_YES)
+ SERDES_NUM => 3,
+ IS_SYNC_SLAVE => c_YES
)
port map(
CLK_REF_FULL => clk_full_osc,
RESET => reset_i,
CLEAR => clear_i,
--Internal Connection
- MEDIA_MED2INT(0) => med2int(7),
- MEDIA_MED2INT(1) => med2int(6),
- MEDIA_MED2INT(2) => med2int(5),
- MEDIA_MED2INT(3) => med2int(9),
- MEDIA_INT2MED(0) => int2med(7),
- MEDIA_INT2MED(1) => int2med(6),
- MEDIA_INT2MED(2) => int2med(5),
- MEDIA_INT2MED(3) => int2med(9),
+ MEDIA_MED2INT => med2int(4),
+ MEDIA_INT2MED => int2med(4),
--Sync operation
RX_DLM => open,
RX_DLM_WORD => open,
TX_DLM => open,
TX_DLM_WORD => open,
--SFP Connection
- SD_PRSNT_N_IN(0) => backplane_rx_present(7),
- SD_LOS_IN(0) => backplane_rx_present(7),
- SD_TXDIS_OUT(0) => backplane_tx_present(7),
- SD_PRSNT_N_IN(1) => backplane_rx_present(6),
- SD_LOS_IN(1) => backplane_rx_present(6),
- SD_TXDIS_OUT(1) => backplane_tx_present(6),
- SD_PRSNT_N_IN(2) => backplane_rx_present(5),
- SD_LOS_IN(2) => backplane_rx_present(5),
- SD_TXDIS_OUT(2) => backplane_tx_present(5),
- SD_PRSNT_N_IN(3) => SFP_MOD0(1),
- SD_LOS_IN(3) => SFP_LOS(1),
- SD_TXDIS_OUT(3) => SFP_TX_DIS(1),
+ SD_PRSNT_N_IN => SFP_MOD0(1),
+ SD_LOS_IN => SFP_LOS(1),
+ SD_TXDIS_OUT => SFP_TX_DIS(1),
--Control Interface
BUS_RX => bussci2_rx,
BUS_TX => bussci2_tx,
RESET => reset_i,
CLEAR => clear_i,
--Internal Connection
- MEDIA_MED2INT => med2int(10), --10 or 8
- MEDIA_INT2MED => int2med(10),
+ MEDIA_MED2INT => med2int(5),
+ MEDIA_INT2MED => int2med(5),
--Sync operation
RX_DLM => open,
RX_DLM_WORD => open,
CTRL_DEBUG => open
);
-THE_MEDIA_4_DOWN2 : entity work.med_ecp3_sfp_sync_4 --PCSC
- generic map(
- IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO),
- IS_USED => (c_YES, c_YES, c_NO, c_NO)
- )
- port map(
- CLK_REF_FULL => clk_full_osc,
- CLK_INTERNAL_FULL => clk_full_osc,
- SYSCLK => clk_sys,
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection
- MEDIA_MED2INT(0) => med2int(4),
- MEDIA_MED2INT(1) => med2int(8),
- MEDIA_INT2MED(0) => int2med(4),
- MEDIA_INT2MED(1) => int2med(8),
- --Sync operation
- RX_DLM => open,
- RX_DLM_WORD => open,
- TX_DLM => open,
- TX_DLM_WORD => open,
- --SFP Connection
- SD_PRSNT_N_IN(0) => backplane_rx_present(4),
- SD_PRSNT_N_IN(1) => backplane_rx_present(8),
- SD_PRSNT_N_IN(2) => '1',
- SD_PRSNT_N_IN(3) => '1',
- SD_LOS_IN(0) => backplane_rx_present(4),
- SD_LOS_IN(1) => backplane_rx_present(8),
- SD_LOS_IN(2) => '1',
- SD_LOS_IN(3) => '1',
- SD_TXDIS_OUT(0) => backplane_tx_present(4),
- SD_TXDIS_OUT(1) => backplane_tx_present(8),
- SD_TXDIS_OUT(2) => open,
- SD_TXDIS_OUT(3) => open,
- --Control Interface
- BUS_RX => bussci3_rx,
- BUS_TX => bussci3_tx,
- -- Status and control port
- STAT_DEBUG => open,
- CTRL_DEBUG => open
- );
- gen_ready_signals : for i in 0 to 8 generate
- backplane_rx_present(i) <= BACK_SLAVE_READY(i);
- BACK_MASTER_READY(i) <= backplane_tx_present(i) or SFP_LOS(1);
+GEN_READY_SIGNALS : for i in 0 to 4 generate
+ backplane_rx_present(i) <= BACK_SLAVE_READY(i);
+ BACK_MASTER_READY(i) <= backplane_tx_present(i) or SFP_LOS(1);
- monitor_inputs_i(i*2+1 downto i*2) <= BACK_TRIG2(i) & BACK_TRIG1(i);
- trigger_inputs_i(i*2+1 downto i*2) <= BACK_TRIG2(i) & BACK_TRIG1(i);
- end generate;
+ monitor_inputs_i(i*2+1 downto i*2) <= BACK_TRIG2(i) & BACK_TRIG1(i);
+ trigger_inputs_i(i*2+1 downto i*2) <= BACK_TRIG2(i) & BACK_TRIG1(i);
+end generate GEN_READY_SIGNALS;
---------------------------------------------------------------------------
-- GbE
---------------------------------------------------------------------------
-gen_noGBE : if INCLUDE_GBE = 0 generate
+gen_noGBE : if INCLUDE_GBE = c_NO generate
busgbeip_tx.unknown <= busgbeip_rx.read or busgbeip_rx.write;
busgbereg_tx.unknown <= busgbereg_rx.read or busgbereg_rx.write;
end generate;
-gen_GBE : if INCLUDE_GBE = 1 generate
+gen_GBE : if INCLUDE_GBE = c_YES generate
signal external_reset_i : std_logic;
begin
GBE : entity work.gbe_wrapper
NUMBER_OF_GBE_LINKS => 4,
LINKS_ACTIVE => "0001",
- LINK_HAS_READOUT => "0001",
- LINK_HAS_SLOWCTRL => "0001",
- LINK_HAS_DHCP => "0001",
- LINK_HAS_ARP => "0001",
- LINK_HAS_PING => "0001"
+ LINK_HAS_READOUT => "0001",
+ LINK_HAS_SLOWCTRL => "0001",
+ LINK_HAS_DHCP => "0001",
+ LINK_HAS_ARP => "0001",
+ LINK_HAS_PING => "0001"
)
port map(
CLK_SYS_IN => clk_sys,
trigger_inputs_i(21 downto 18) <= (others => '0');
trigger_inputs_i(53 downto 22) <= INP(95 downto 64);
- spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5);
+ spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5);
DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4);
DAC_OUT_CS(6 downto 5) <= spi_cs(5 downto 4);
DAC_OUT_SDO(6 downto 5) <= spi_mosi(5 downto 4);
LED_RED <= not sed_error_i;
LED_YELLOW <= debug_clock_reset(2);
LED_WHITE <= led;
- LED_SFP_GREEN(1) <= not med2int(9).stat_op(9); --SFP Link Status
- LED_SFP_RED(1) <= not (med2int(9).stat_op(10) or med2int(9).stat_op(11)); --SFP RX/TX
+ LED_SFP_GREEN(1) <= not med2int(4).stat_op(9); --SFP Link Status
+ LED_SFP_RED(1) <= not (med2int(4).stat_op(10) or med2int(4).stat_op(11)); --SFP RX/TX
gen_led_nogbe : if INCLUDE_GBE = c_NO generate
- LED_SFP_GREEN(0) <= not med2int(10).stat_op(9); --SFP Link Status
- LED_SFP_RED(0) <= not (med2int(10).stat_op(10) or med2int(10).stat_op(11)); --SFP RX/TX
+ LED_SFP_GREEN(0) <= not med2int(5).stat_op(9); --SFP Link Status
+ LED_SFP_RED(0) <= not (med2int(5).stat_op(10) or med2int(5).stat_op(11)); --SFP RX/TX
end generate;
gen_led_gbe : if INCLUDE_GBE = c_YES generate
LED_SFP_GREEN(0) <= '1';
led(0) <= time_counter(26) and time_counter(16);
led(1) <= not (clear_i or reset_i);
- TEST_LINE(0) <= med2int(9).stat_op(13);
- TEST_LINE(1) <= med2int(9).stat_op(15);
- TEST_LINE(2) <= clear_i;
- TEST_LINE(3) <= reset_i;
- TEST_LINE(4) <= med2int(9).dataready;
- TEST_LINE(5) <= int2med(9).dataready;
- TEST_LINE(6) <= med2int(7).dataready;
- TEST_LINE(7) <= int2med(7).dataready;
-
+-- TEST_LINE(0) <= med2int(4).stat_op(13);
+-- TEST_LINE(1) <= med2int(4).stat_op(15);
+-- TEST_LINE(2) <= clear_i;
+-- TEST_LINE(3) <= reset_i;
+-- TEST_LINE(4) <= med2int(4).dataready;
+-- TEST_LINE(5) <= int2med(4).dataready;
+-- TEST_LINE(6) <= med2int(2).dataready;
+-- TEST_LINE(7) <= int2med(2).dataready;
+ TEST_LINE <= (others => '0');
+
end architecture;
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