change trbnet_reset sleep time to 2s in case of TRB3 design, all others are 8s still

diff --git a/libtrbnet/trbnet.c b/libtrbnet/trbnet.c
index f954851bc82434c9afcc20092dbe92b8c5b6fc26..8cfc2cbe4de894509c3b2158cf932d3f37cc2c04 100644 (file)
--- a/libtrbnet/trbnet.c
+++ b/libtrbnet/trbnet.c
@@ -1,4 +1,4 @@
-#define TRBNET_VERSION "4.42"
+#define TRBNET_VERSION "4.43"
 
 #ifdef ETRAX
 const char trbnet_version[] = "Revision " TRBNET_VERSION " Local Etrax";
@@ -2912,7 +2912,8 @@ int fpga_register_write(uint32_t reg_address, uint32_t value)
   return status;
 }
 
-#ifdef PEXOR
+/* NOT TRB3 */
+#ifdef PEXOR   
 int fpga_register_read_mem(uint32_t reg_address,
                            uint32_t* data,
                            unsigned int size)
@@ -3006,8 +3007,8 @@ int com_reset()
   return 0;
 }
 
-#else /* NOT TRB3 */
-
+#else 
+/* TRB3 */
 int trb_ipu_data_read(uint8_t type,
                       uint8_t trg_info,
                       uint8_t trg_random,
@@ -3082,7 +3083,7 @@ int network_reset()
     return -1;
   }
 
-  sleep(8);
+  sleep(2);
 
   return status;
 }