additional wait state to compensate fifo read issue while write procedure via DCA

diff --git a/src/cri_trbnet_dca_bridge.vhd b/src/cri_trbnet_dca_bridge.vhd
index f84303b2161521ebd77154eb7bb4db4b73151661..67df8b5e102a2ef7bb16cf98d567cd3f89bf59bc 100644 (file)
--- a/src/cri_trbnet_dca_bridge.vhd
+++ b/src/cri_trbnet_dca_bridge.vhd
@@ -50,7 +50,7 @@ signal reset_dca : std_logic;
 
 attribute syn_encoding : string;
 
-type dissect_states is (IDLE, GET_DCA_DATA, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, CHECK_RESPONSE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP);
+type dissect_states is (IDLE, GET_DCA_DATA, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, CHECK_RESPONSE, WAIT_CNTR, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP);
 signal dissect_current_state, dissect_next_state : dissect_states;
 attribute syn_encoding of dissect_current_state: signal is "onehot";
 
@@ -126,6 +126,8 @@ signal preload_word_tx_fifo : std_logic;
 
 signal tx_data_out          : std_logic_vector(31 downto 0);
 
+signal wait_cnt             : unsigned(1 downto 0) := "00";
+
 begin
   reset_dca <= not RST_N_DCA;
 
@@ -371,6 +373,13 @@ begin
       tx_fifo_rd           <= '0';
       preload_word_tx_fifo <= '0';
     end if;
+    
+    if (dissect_current_state = WAIT_CNTR) then
+      wait_cnt <= wait_cnt + 1;
+    else 
+      wait_cnt <= "00";
+    end if;
+    
   end if;
 end process TX_FIFO_READ_PROC;
 
@@ -516,9 +525,15 @@ begin
       
     when CHECK_RESPONSE =>
       state <= x"7";
-      dissect_next_state <= WAIT_FOR_LOAD;
+      dissect_next_state <= WAIT_CNTR;
+    
+    when WAIT_CNTR =>
+      if wait_cnt = 2 then
+        dissect_next_state <= WAIT_FOR_LOAD;
+      else
+        dissect_next_state <= WAIT_CNTR;
+      end if;
     
-
     when WAIT_FOR_LOAD =>
       state <= x"8";
       if preload_word_tx_fifo = '1' then