updated trb3sc and slow control registers

diff --git a/trb3/Trb3scBasics.tex b/trb3/Trb3scBasics.tex
index 6ad1242bb22a5f981a0a1b3822492d0345f6a0bd..622a143a44b7ee023cb32e0a0f17762c0918f15f 100644 (file)
--- a/trb3/Trb3scBasics.tex
+++ b/trb3/Trb3scBasics.tex
@@ -57,6 +57,9 @@ JGPIO is available for any general purpose I/O. All lines are LVCMOS25. By defau
   \end{tabular}
 \end{center}
 
+SPI channels 0 to 3 are linked to the AddOn connector (e.g. four Padiwa chains), channels 4 and 5 are used on additional KEL connectors. Channel 6 is reserved for JGPIO.
+
+
 \subsubsection{Serial Links}
 By default, SFP1 is used for GbE, SFP2 for TrbNet. SFP2 must be removed if the board is to be used on a backplane as slave module. Removing the SFP selects the backpanel as TrbNet input.
 

diff --git a/trb3/sctrladdresses.tex b/trb3/sctrladdresses.tex
index 57f3be463517ba6129c26bcc3ce16c8184c0af3e..cab5c8b9a43759ff6ea47766bd25f2951f0523f9 100644 (file)
--- a/trb3/sctrladdresses.tex
+++ b/trb3/sctrladdresses.tex
@@ -18,6 +18,7 @@ D000 -- D13F & Flash & Control for SPI Flash of FPGA [\ref{flashprog}]\\
 D200         & Rom & Flash Rom Switch \\
 D300         & TrgIn & Selection for trigger and clock input on CTS \\
 D400 -- D41F & SPI & SPI Interface for DAC and Padiwa \\
+D480 -- D4FF & Adc & On-board monitoring of voltages or currents \\
 D500 -- D5FF & SED & Soft Error Detection \\
 D600 -- D6FF & Uart & Serial Uart Interface \\
 E000 -- FFFF & Debugging & Memories and Registers for Debugging \\