32 bit counters for injection length and pause. Additional register to start injections.

diff --git a/mupix/Mupix8/sources/MupixBoardDAC.vhd b/mupix/Mupix8/sources/MupixBoardDAC.vhd
index 103df86925542af2ce8b66764190f0ca9977f787..41f4541afc943259d121434dbe5099d714c37233 100644 (file)
--- a/mupix/Mupix8/sources/MupixBoardDAC.vhd
+++ b/mupix/Mupix8/sources/MupixBoardDAC.vhd
@@ -78,8 +78,8 @@ architecture RTL of MupixBoardDAC is
        port(
                rst                  : in  std_logic;
        clk                  : in  std_logic;
-       pulse_length         : in  std_logic_vector(15 downto 0); 
-       pulse_pause          : in  std_logic_vector(15 downto 0);
+       pulse_length         : in  std_logic_vector(31 downto 0); 
+       pulse_pause          : in  std_logic_vector(31 downto 0);
        pulse_start          : in  std_logic;
        pulse_o              : out std_logic 
        );
@@ -106,7 +106,7 @@ architecture RTL of MupixBoardDAC is
        signal spi_clk_adc : std_logic;
        
        signal pulse_start_i : std_logic := '0';
-       signal pulse_length_i, pulse_pause_i  : std_logic_vector(15 downto 0) := (others => '0');
+       signal pulse_length_i, pulse_pause_i  : std_logic_vector(31 downto 0) := (others => '0');
        
 begin
        
@@ -187,7 +187,9 @@ begin
        --0x0096: start write threshold and injection dacs bit
        --0x0097: write config adc
        --0x0098: read adc data
-       --0x0099: injection length (31:16) and pause (15:0) 
+       --0x0099: injection length 
+       --0x009a: injection pause
+       --0x009b: start injection pulse
        -----------------------------------------------------------------------------
        SLV_BUS_HANDLER : process(clk)
        begin                               -- process SLV_BUS_HANDLER
@@ -199,7 +201,7 @@ begin
                        start_write_threshold <= '0';
                        start_write_temperature <= '0';
                        start_write_adc       <= '0';
-                       pulse_start_i <= '0';
+                       pulse_start_i         <= '0';
 
                        if SLV_READ_IN = '1' then
                                case SLV_ADDR_IN is
@@ -228,8 +230,10 @@ begin
                                                SLV_DATA_OUT              <= spi_data_out_adc;
                                                SLV_ACK_OUT               <= '1';
                                        when x"0099" =>
-                                               SLV_DATA_OUT(31 downto 16) <= pulse_length_i;
-                                               SLV_DATA_OUT(15 downto 0)  <= pulse_length_i;
+                                               SLV_DATA_OUT(31 downto 0) <= pulse_length_i;
+                                               SLV_ACK_OUT                <= '1';
+                                       when x"009a" =>
+                                               SLV_DATA_OUT(31 downto 0)  <= pulse_pause_i;
                                                SLV_ACK_OUT                <= '1';
                                        when others =>
                                                SLV_UNKNOWN_ADDR_OUT <= '1';
@@ -255,9 +259,13 @@ begin
                                                start_write_adc       <= '1';
                                                SLV_ACK_OUT           <= '1';
                                        when x"0099" =>
+                                               pulse_length_i <= SLV_DATA_IN;
+                                               SLV_ACK_OUT    <= '1';
+                                       when x"009a" =>
+                                               pulse_pause_i  <= SLV_DATA_IN;
+                                               SLV_ACK_OUT    <= '1';
+                                       when x"009b" =>
                                                pulse_start_i  <= '1';
-                                               pulse_length_i <= SLV_DATA_IN(31 downto 16);
-                                               pulse_pause_i  <= SLV_DATA_IN(15 downto 0);
                                                SLV_ACK_OUT    <= '1';
                                        when others =>
                                                SLV_UNKNOWN_ADDR_OUT <= '1';

diff --git a/mupix/Mupix8/sources/TestpulseGenerator.vhd b/mupix/Mupix8/sources/TestpulseGenerator.vhd
index fb9f4734bafb2d7b4867985c932bf0d0040e2a4c..16400a7a2046aa6a8b29c93eea29e480bf517900 100644 (file)
--- a/mupix/Mupix8/sources/TestpulseGenerator.vhd
+++ b/mupix/Mupix8/sources/TestpulseGenerator.vhd
@@ -11,8 +11,8 @@ entity injection_generator is
   port (
     rst                  : in  std_logic;--! reset input
     clk                  : in  std_logic;--! clock input
-    pulse_length         : in  std_logic_vector(15 downto 0); --! length of injection pulse
-    pulse_pause          : in  std_logic_vector(15 downto 0); --! pause between pulses
+    pulse_length         : in  std_logic_vector(31 downto 0); --! length of injection pulse
+    pulse_pause          : in  std_logic_vector(31 downto 0); --! pause between pulses
     pulse_start          : in  std_logic;--! start generation of pulse
     pulse_o              : out std_logic --! output signal to mupix board
     );
@@ -23,7 +23,7 @@ architecture rtl of injection_generator is
 
        type injection_generator_type is (idle, gen, pause);
        signal injection_generator_fsm : injection_generator_type := idle;  
-       signal length_counter, pause_counter : unsigned(15 downto 0) := (others => '0');
+       signal length_counter, pause_counter : unsigned(31 downto 0) := (others => '0');
        
 begin